WO2005117115A1 - Puces a lignes utiles et lignes fictives - Google Patents

Puces a lignes utiles et lignes fictives Download PDF

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Publication number
WO2005117115A1
WO2005117115A1 PCT/IB2005/051600 IB2005051600W WO2005117115A1 WO 2005117115 A1 WO2005117115 A1 WO 2005117115A1 IB 2005051600 W IB2005051600 W IB 2005051600W WO 2005117115 A1 WO2005117115 A1 WO 2005117115A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
lines
line
useful
dummy
Prior art date
Application number
PCT/IB2005/051600
Other languages
English (en)
Inventor
Heimo Scheucher
Claus Grzyb
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2005117115A1 publication Critical patent/WO2005117115A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a chip, which chip has a substrate and an integrated circuit having a plurality of active circuit components that is provided on the substrate, and which chip has a passivating layer, and which chip has, between the integrated circuit and the passivating layer, a plurality of layer-like line zones, in which line zones useful lines are provided and between which line zones layer- like isolating zones are provided to isolate the line zones and the useful lines contained therein from one another electrically, which useful lines are intended to connect active circuit components of the integrated circuit and to pass on useful signals and which isolating zones are provided with through-holes, in which through- holes are provided vias by means of which two useful lines situated in immediately adjoining line zones are connected together by an electrically conductive connection.
  • a chip of the design set out in the first paragraph above has been marketed in many variant versions and is therefore known.
  • the problem that, at greater or lesser cost in terms of time, money and effort, at least one of its many functions can be reverse engineered, or in other words spied out, in an undesirable way, because access to the various useful lines is possible in successive steps by applying etching processes that follow one another in an intelligent sequence, thus enabling at least one function of the known chip to be determined with the help of a large number of probe steps. Any such unwanted determining of at least one of its functions is extremely problematic, particularly when secret data is stored in the chip.
  • a field of application where the unwanted determining of a function of a chip is especially critical is that of data carriers suitable for and arranged for contactless communication, such as, for example.
  • Chip cards or vehicle immobilizers because in these areas of application particularly unpleasant and severe disadvantages can arise for the user concerned if unauthorized persons succeed in reverse engineering an important function of the chip.
  • US patent document US 5,861,662 A attention may for example be drawn to US patent document US 5,861,662 A.
  • connecting bond wires of this kind can be cleared out of the way by shifting them mechanically, thus enabling larger spacings to be obtained between the connecting bond wires, which makes access for probe needles easier.
  • the connecting bond wires provided in the chip package can, with relative ease, be removed and replaced by other bypassing lines, which is likewise undesirable with a view to having protection that is as good as possible against any unwanted spying out of a function of a chip.
  • the production of connecting bond wires of this kind means additional costs, which has a disadvantageous effect on the cost of producing a chip package containing a chip worth protecting.
  • a chip which chip has a substrate and an integrated circuit, having a plurality of active circuit components, that is provided on the substrate, and which chip has a passivating layer, and which chip has a plurality of layer- like line zones between the integrated circuit and the passivating layer, in which line zones useful lines are provided and between which line zones layer-like isolating zones are provided to isolate the line zones and the useful lines contained therein from one another electrically, which useful lines are intended to connect active circuit components of the integrated circuit and to pass on useful signals and which isolating zones are provided with through-holes, in which through-holes are provided vias by means of which two useful lines situated in immediately adjoining line
  • a further advantage of the provisions according to the invention is that the production of the protective means requires virtually no additional effort or expenditure, because the production of the dummy lines that are provided as protective means is possible, and is performed, simultaneously with the production of useful lines that are present anyway, which means that the production of the dummy lines merely imposes additional costs for material but no additional procedural costs, which is advantageous with a view to producing a chip as inexpensively as possible.
  • the making of the provisions according to the invention ensures a considerably higher level of protection than in the case of the known solution because dummy lines provided in accordance with the invention can be produced to particularly small widths and at particularly small spacings - as is already known for useful lines - thus making it virtually impossible for probe needles to be passed through between two useful lines or dummy lines.
  • Nor other bypass lines can replace dummy lines provided in accordance with the invention.
  • a chip according to the invention it has proved very advantageous if the dummy lines are provided in addition to the useful lines in at least one line zone.
  • An arrangement of this kind has proved advantageous with a view to providing protection against any spying out of at least one function of chip because this arrangement calls for only very little effort and expenditure for its implementation.
  • An arrangement of this kind has proved particularly advantageous because there is then already a strong barrier against any unwanted spying out of at least one function of a chip according to the invention in a region of a chip of this kind that is situated very far towards the exterior.
  • a chip according to the invention it has proved very advantageous if at least some of the dummy lines provided in a line zone each have an electrically conductive connection to at least one via, which at least one via extends from the line zone to the line zone that is adjacent to it and that is situated nearer to the integrated circuit. What is achieved in this way is that the presence of useful vias can be simulated, which makes a major contribution to making it considerably more difficult for at least one function of a chip according to the invention to be spied out.
  • the at least one via has an electrically conductive connection to a dummy line in the adjacent line zone situated nearer to the integrated circuit and consequently dummy lines are provided in at least two line zones.
  • What is obtained in this way is a further obstacle to any unwanted spying out of at least one function of a chip according to the invention, because, in a spying-out operation, at least two line zones have to be spied out and overcome.
  • dummy lines are provided in all the line zones that are present.
  • a chip according to the invention it has also proved very advantageous if some of the dummy lines are at a given potential when the chip is operating.
  • An arrangement of this kind is particularly advantageous because the application of a given potential to dummy lines provides particularly effective assistance with the pretence that dummy lines are useful lines.
  • the application of a given potential to dummy lines is also useful against crosswalk to said dummy lines. It is very advantageous in this case if what is selected as the given potential is the ground potential. It has also proved very advantageous if, in addition to the active circuit components, stock circuit components are also included in the integrated circuit and if at least some of the stock circuit components are connected to at least one dummy line and, when the chip is operating, are at at least one given potential.
  • Fig. 1 is a schematic cross-section showing part of a known prior-art chip.
  • Fig. 2 is a view from above of a chip according to a first embodiment of the invention, which chip has five line zones arranged one above the other that are shown in Fig. 2.
  • Fig. 3 is a cross-section through part of the chip shown in Fig. 2, taken on the thick line shown in Fig. 2.
  • Fig. 4 is a view similar to Fig. 2, showing the chip of Figs. 2 and 3 but showing only the topmost, fifth line zone and the fourth line zone situated below it and showing, in these zones, all the useful lines and some of the dummy lines.
  • Fig. 5 is a view similar to Fig.
  • Fig. 2 shows the chip of Figs. 2, 3 and 4 but showing only the topmost, fifth line zone and the fourth line zone situated below it and showing, in these zones, only all the useful lines.
  • Fig. 6 is a view similar to Figs. 2 and 4, showing a chip according to a second embodiment of the invention but showing only one line zone and showing, in this line zone, both all of the useful lines and all of the dummy lines.
  • Fig. 7 is a view similar to Figs. 2, 4, 5 and 6 showing the chip of Fig. 6 but showing one line zone and showing, in this line zone, only all the useful lines.
  • Fig. 1 shows part of a known prior-art chip 1, which chip 1 is produced on the basis of silicon. It should be mentioned that such a chip might also be produced on the basis of a polymer material.
  • the chip 1 has a substrate 2 that may also be referred to as a base member.
  • Produced on the substrate 2 is an integrated circuit 3 that is only indicated very schematically in Fig. 1.
  • the production and configuring of an integrated circuit 3 of this kind is generally familiar to those skilled in the art and therefore does not need to be described in any greater detail in the present connection.
  • the integrated circuit 3 contains a plurality of circuit components 4 and, in addition to the active circuit components 4, stock or "X-box" circuit components 5.
  • the active circuit components 4 are provided in the integrated circuit 3 in such a way that they are active when the integrated circuit 3 is operating and are used to perform the various functions of the integrated circuit 3.
  • the stock circuit components 5 were originally provided only for stock purposes and are used, if required, as active circuit components. This measure has long been known to those skilled in the art and for this reason there is no need for it to be considered in any greater detail here.
  • the chip 1 On its face region remote from the substrate 2, the chip 1 is provided with a passivating layer 6.
  • the passivating layer 6 is often also referred to as a protective layer or covering layer.
  • the passivating layer 6 is intended and arranged to protect the parts of the chip 1 that are situated beneath it.
  • the passivating layer 6 is preferably composed of silicon nitride (SiN) but may also be produced from other materials.
  • through-holes 7 through which through-holes 7 electrically conductive chip contacts (pads) PAD1, PAD2, PAD3 and PAD4 are accessible, which is likewise something that is generally familiar.
  • the chip 1 has a total of five layer-like lines zones MEI, ME2, ME3, ME4 and ME5. To isolate the line zone MEI from the integrated circuit 3 electrically, and to isolate the line zones MEI to ME5 from one another electrically, layer-like isolating zones ISl, IS2, IS3, IS4 and IS5 are provided.
  • Isolating zones ISl, IS2, IS3, IS4 and IS5 are composed of an isolating layer of non- conductive oxide, which is also intended for planarizing purposes.
  • line zones MEI to ME5 Provided in the line zones MEI to ME5 are useful lines LI, L2, L3, L4, L5, L6, L7, L8, L9, L10, Lll, L12, L13, L14, L15, L16 and L17.
  • the above-mentioned pads are formed by means of the useful lines L14, L15, L16 and L17 situated in the topmost, fifth line zone ME5.
  • the useful lines in each line zone MEI to ME5 preferably extend in one direction and parallel to one another.
  • the useful lines in two mutually adjacent line zones preferably extend perpendicularly to one another in this case.
  • the useful lines are isolated from one another by means of the isolating zones ISl to IS5.
  • the useful lines are intended for connecting the active components 4 of the integrated circuit 3 and for passing on useful signals.
  • some of the useful lines in different line zones MEI to ME5 are connected together electrically, where this is required.
  • the isolating zones ISl to IS5 are provided with through- holes but these have not been given reference numerals in Fig. 1 so that the clarity of the drawing will not be reduced unnecessarily.
  • Provided in the through-holes in the isolating zones ISl to IS5 are through-lines that are often referred to by those skilled in the art as "vias". In Fig.
  • Spying out of this kind can be performed by etching away, in successive steps, zones lying one above the other, or by etching away, in successive steps, small parts of successive zones, measurements being made, after each etching operation has been performed, at what is termed a tip measuring point by means of so-called probe needles, a process which is referred to by those skilled in the art as "probing".
  • the design of the chip 1 shown in Fig. 2 is made such that the chip 1 is provided in its interior with protective means 10, which protective means 10 are intended and arranged to provide protection against any unwanted spying out of at least one of the many functions of the chip.
  • the protective means 10 are implemented in this case by means of dummy lines, of which dummy lines only some of those actually present are identified in Figs. 2, 3 and 4 by the references DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8, DL9, DL10, DL11, DL12 and DL13. Only some of the dummy lines actually provided are shown in Figs. 2 and 4, so that there are no additional obstacles to the intelligibility of these Figures, and particularly that of Fig. 2. In the chip 1 that is actually produced, the dummy lines are so tightly packed that virtually the entire area of a line zone is filled with lines, so that what exists is a grille structure covering virtually the whole area.
  • the dummy lines DLl and DL2 provided in the topmost, fifth line zone ME5 each have an electrically conductive connection to at least one via, with dummy line DLl having an electrically conductive connection to two vias TLl and TL2 and the second dummy line DL2 having an electrically conductive connection to one via TL3.
  • the three vias TLl, TL2 and TL3 extend from the fifth line zone ME5 to the fourth line zone ME4 that is situated adjacent the latter and closer to the integrated circuit 3, with via TLl having an electrically conductive connection to the dummy line DL3 situated in the fourth line zone ME4, via TL2 having an electrically conductive connection to the dummy line DL6 situated in the fourth line zone ME4, and via TL3 having an electrically conductive connection to the dummy line DL7 situated in the fourth line zone ME4.
  • the wiring of the chip 1 With regard to what is termed the wiring of the chip 1, it should also be mentioned that, for passing on signals when the chip 1 is operating, useful lines that extend in line zones lying at deeper levels are selected for signals that are of great importance and consequently have a great need for security. It should also be mentioned that in ordinary chips the wiring density per line zone is often a maximum of 50 %. Because of the additional provision of the dummy lines, it becomes possible in a chip according to the invention for a wiring density of up to close to 100 % to be obtained in each line zone MEI to ME5. This makes possible or ensures a particularly high level of protection against any unwanted spying out.
  • Figs. 6 and 7 is part of a further chip 1 according to the invention, only the seventh line zone ME7 being shown in detail. It can clearly be seen from these two Figures how the arrangements in this seventh line zone ME7 differ from one another in respect of dummy lines being, or not being, provided.
  • Fig. 6 are shown both the useful lines and the dummy lines in the seventh line zone ME7, whereas in Fig.
  • a voltage source is provided that is separated in an especially secure manner from the other active circuit components of the integrated circuit 3 and that makes available a given potential.
  • some of the dummy lines are at the given potential at least when the chip is operating, in which case the said voltage source is then activated.
  • all the dummy lines are at the given potential. Due to the fact that some or all of the dummy lines are at the given potential, the advantage is obtained that a greater pretence can be made that dummy lines are useful lines.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Dans une puce (1) présentant un substrat (2) et un circuit intégré (3) produit sur le substrat (2), une pluralité de zones de lignes (MEI, ME2, ME3, ME4, ME5) sont situées l'une sur l'autre, isolées par des zones isolantes (IS1, IS2, IS3, IS4, IS5), les unes des autres, dans lesquelles les zones de ligne sont utilisées comme des lignes utiles et des lignes fictives, ces dernières servant à fournir une protection contre un espionnage non souhaité d'au moins une fonction de la puce. Selon l'invention, il n'y a aucune liaison électroconductrice entre les lignes fictives et les composants du circuit (4) actif du circuit intégré (3) et par conséquent aucun signal utile n'apparaît sur les lignes fictives, lorsque la puce (1) fonctionne.
PCT/IB2005/051600 2004-05-28 2005-05-17 Puces a lignes utiles et lignes fictives WO2005117115A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04102406 2004-05-28
EP04102406.8 2004-05-28

Publications (1)

Publication Number Publication Date
WO2005117115A1 true WO2005117115A1 (fr) 2005-12-08

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PCT/IB2005/051600 WO2005117115A1 (fr) 2004-05-28 2005-05-17 Puces a lignes utiles et lignes fictives

Country Status (1)

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WO (1) WO2005117115A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009031057A3 (fr) * 2007-09-04 2009-06-04 Nds Ltd Puce de sécurité
US9620456B2 (en) 2007-07-12 2017-04-11 Nxp B.V. Integrated circuits on a wafer and methods for manufacturing integrated circuits
EP3166139A1 (fr) * 2015-11-03 2017-05-10 Nxp B.V. Circuit intégré et son procédé de fabrication
US9741671B1 (en) 2016-11-10 2017-08-22 Nxp B.V. Semiconductor die with backside protection
US11177210B2 (en) 2019-12-31 2021-11-16 Nxp B.V. Integrated circuit with non-functional structures

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920402A (en) * 1988-02-15 1990-04-24 Mitsubishi Denki Kabushiki Kaisha Integrated circuit device
EP0409256A2 (fr) * 1989-07-21 1991-01-23 Kabushiki Kaisha Toshiba Dispositif à circuit intégré semi-conducteur et procédé pour sa fabrication
US5883000A (en) * 1995-05-03 1999-03-16 Lsi Logic Corporation Circuit device interconnection by direct writing of patterns therein
JP2001284357A (ja) * 2000-03-30 2001-10-12 Sony Corp 半導体装置
JP2003196158A (ja) * 2001-12-26 2003-07-11 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置
US20030205816A1 (en) * 2000-11-23 2003-11-06 Marcus Janke Integrated circuit configuration with analysis protection and method for producing the configuration
WO2004038800A2 (fr) * 2002-10-21 2004-05-06 Hrl Laboratories, Llc Circuit integre multicouche a rubans conducteurs exterieurs

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920402A (en) * 1988-02-15 1990-04-24 Mitsubishi Denki Kabushiki Kaisha Integrated circuit device
EP0409256A2 (fr) * 1989-07-21 1991-01-23 Kabushiki Kaisha Toshiba Dispositif à circuit intégré semi-conducteur et procédé pour sa fabrication
US5883000A (en) * 1995-05-03 1999-03-16 Lsi Logic Corporation Circuit device interconnection by direct writing of patterns therein
JP2001284357A (ja) * 2000-03-30 2001-10-12 Sony Corp 半導体装置
US20030205816A1 (en) * 2000-11-23 2003-11-06 Marcus Janke Integrated circuit configuration with analysis protection and method for producing the configuration
JP2003196158A (ja) * 2001-12-26 2003-07-11 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置
WO2004038800A2 (fr) * 2002-10-21 2004-05-06 Hrl Laboratories, Llc Circuit integre multicouche a rubans conducteurs exterieurs

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 2002, no. 02 2 April 2002 (2002-04-02) *
PATENT ABSTRACTS OF JAPAN vol. 2003, no. 11 5 November 2003 (2003-11-05) *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9620456B2 (en) 2007-07-12 2017-04-11 Nxp B.V. Integrated circuits on a wafer and methods for manufacturing integrated circuits
WO2009031057A3 (fr) * 2007-09-04 2009-06-04 Nds Ltd Puce de sécurité
CN101803018B (zh) * 2007-09-04 2013-01-16 Nds有限公司 安全芯片
US8410583B2 (en) 2007-09-04 2013-04-02 Nds Limited Security chip
EP3166139A1 (fr) * 2015-11-03 2017-05-10 Nxp B.V. Circuit intégré et son procédé de fabrication
US10115676B2 (en) 2015-11-03 2018-10-30 Nxp B.V. Integrated circuit and method of making an integrated circuit
US9741671B1 (en) 2016-11-10 2017-08-22 Nxp B.V. Semiconductor die with backside protection
US11177210B2 (en) 2019-12-31 2021-11-16 Nxp B.V. Integrated circuit with non-functional structures

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