WO2000019490A2 - Cellule de remplissage fictive pour la reduction de l'interaction intercouche - Google Patents

Cellule de remplissage fictive pour la reduction de l'interaction intercouche Download PDF

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Publication number
WO2000019490A2
WO2000019490A2 PCT/US1999/016794 US9916794W WO0019490A2 WO 2000019490 A2 WO2000019490 A2 WO 2000019490A2 US 9916794 W US9916794 W US 9916794W WO 0019490 A2 WO0019490 A2 WO 0019490A2
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WO
WIPO (PCT)
Prior art keywords
layer
dummy fill
pattern
circuit
areas
Prior art date
Application number
PCT/US1999/016794
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English (en)
Other versions
WO2000019490A3 (fr
Inventor
Robert Zwingman
Aniruddha Joshi
Original Assignee
Conexant Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Conexant Systems, Inc. filed Critical Conexant Systems, Inc.
Publication of WO2000019490A2 publication Critical patent/WO2000019490A2/fr
Publication of WO2000019490A3 publication Critical patent/WO2000019490A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates generally to semiconductor wafer manufacturing techniques. More particularly, the present invention relates to dummy fill patterns that reduce layer-to-layer interaction such as capacitance.
  • dummy fill is utilized to increase the uniformity of an insulator layer during chemical mechanical polishing.
  • prior art semiconductor patterns for a given material layer 100 typically include circuitry patterns 102 that define those areas on layer 100 that will remain after etching.
  • the circuitry areas 102 may serve different functions depending upon the particular material layer 100.
  • circuitry areas 102 may define the semiconductor devices, e.g., transistors, formed on an active layer.
  • circuitry areas 102 may define metal lines used for interconnecting the active devices.
  • Layer 100 also includes a dummy fill pattern 104 formed from the same material as circuitry areas 102.
  • layer 100 may exhibit an uneven surface topology after chemical mechanical polishing due to the "valleys" formed between the circuitry areas 102. Accordingly, dummy fill pattern 104 may be employed such that the surface topology is evenly polished. As shown in FIG. 1, dummy fill pattern 104 does not overlap circuitry areas 102; this is necessary to maintain the electrical integrity of the integrated circuits formed on the semiconductor wafer.
  • Prior art techniques often begin with a symmetrical and evenly spaced dummy fill configuration and remove or subtract an appropriate amount of dummy fill to accommodate active circuitry areas 102.
  • the circuitry areas 102 and dummy fill pattern 104 are typically defined by respective data files.
  • the data files are processed until the final mask pattern for the given material layer 100 is completed.
  • the portions of dummy fill remaining on a given material layer may affect the electrical performance of the integrated circuits by way of layer-to-layer interactions.
  • the dummy fill on one layer may introduce unwanted capacitance (e.g., between the circuitry on one material layer and the circuitry on a different material layer, between two circuit lines on the same material layer, or between the circuitry on one material layer and the dummy fill on a different material layer).
  • FIG. 1 shows a circuit line 106 for a material layer other than layer 100, as projected onto layer 100. Those portions of line 106 that overlap portions of dummy fill 104 can be a source of unwanted layer-to-layer interaction.
  • Another advantage of the present invention is that a dummy fill technique is provided that reduces the layer-to-layer interaction in a semiconductor circuit.
  • Another advantage is that the present invention provides a dummy fill technique that considers the electrical performance of the semiconductor circuit in addition to the manufacturing requirements associated with the chemical mechanical polishing process.
  • a further advantage is that a preferred dummy fill pattern can be generated in accordance with the present invention without a significant increase in computational load or manufacturing cost over prior art techniques.
  • An exemplary method involves: (1) obtaining a circuit pattern associated with circuit areas for the first material layer; (2) generating a dummy fill pattern for the first layer, wherein the dummy fill pattern is configured to reduce unwanted electronic interaction between the material on the first and second layers, and wherein the dummy fill pattern does not overlap areas on the first layer associated with the circuit pattern; and (3) producing a mask pattern for the first layer by combining data representing the circuit areas with data representing the dummy fill pattern.
  • FIG. 1 is a top view of a portion of a mask pattern illustrating a prior art dummy fill technique
  • FIG. 2 is a schematic representation of an exemplary dummy fill cell that may be employed to design mask patterns for a multi-layered semiconductor device
  • FIG. 3 is a schematic representation of an exemplary dummy fill cell array
  • FIG. 4 is a schematic representation of an exemplary dummy fill cell having overlapping regions associated with different material layers
  • FIG. 5 is a flow diagram of a mask generation process according to the present invention.
  • FIG. 6 is a flow diagram of a mask production process according to the present invention.
  • FIG. 7 depicts exemplary circuit patterns for a number of material layers associated with a semiconductor device
  • FIG. 8 illustrates various combined circuit patterns and corresponding dummy fill patterns associated with the production of a mask pattern.
  • dummy fill techniques do not contemplate the possible layer-to-layer interactions caused by the dummy fill present on a given material layer.
  • Conventional dummy fill design methodologies focus on the manufacturing process, e.g., enhancing the chemical mechanical polishing results while preventing interactions between dummy fill and circuit lines on a single layer, rather than the electrical performance of the semiconductor circuit as a whole (which includes contributions from layer-to-layer interactions such as stray capacitances).
  • a dummy fill cell is employed to produce a mask for patterning of a material layer associated with a multi-layered semiconductor device.
  • the metal layers may be formed from any suitable conductive or semiconductive material, e.g., polysilicon, aluminum, copper, or the like.
  • the various metal layers may be formed from the same or any number of different materials. For the sake of convenience, a "metal-1" layer is considered to be the first metal layer, a “metal-2” layer is considered to be the next metal layer above the metal-1 layer, and so forth.
  • a dummy fill cell 200 is utilized to design the dummy fill pattern for the various material layers of the semiconductor device.
  • the exemplary cell 200 shown in FIG. 2 only includes regions associated with an active layer 202, a polysilicon layer 204, a metal-1 layer 206, and a metal-2 layer 208. It should be appreciated that cell 200 may include more, less, or alternative regions as dictated by the particular semiconductor device.
  • dummy fill cell 200 preferably includes at least one region associated with each material layer that is to include dummy fill.
  • cell 200 may be configured to account for the interaction of a layer that does not have dummy fill applied but could still interact with other layers. For example, if dummy fill is not to be applied at the polysilicon layer, the dummy fill cell 200 may nonetheless include polysilicon region 204. This arrangement will result in the elimination of dummy active and dummy metal-1 directly below and above any polysilicon circuitry.
  • Cell 200 is preferably configured to minimize the amount of "overlap" between regions associated with material layers that are prone to interaction.
  • the polysilicon layer may interact with the underlying active layer and/or the abovelying metal-1 layer.
  • the metal-1 layer may interact with the underlying polysilicon layer and/or the abovelying metal-2 layer.
  • the techniques of the present invention may be utilized to compensate for "higher order" layer-to-layer interactions between any two material layers, regardless of the number of intervening layers therebetween.
  • the dummy fill cell design may also be responsive to a number of other parameters, such as the distance between the layers and any minimum dummy fill density restrictions.
  • an array 300 (see FIG. 3) of dummy fill cells 200 is used as a foundation for the design of the dummy fill pattern for each of the respective material layers. Then, those regions of dummy fill cells 200 associated with the particular material layer are isolated and used to form the dummy fill pattern for that layer. For example, if dummy fill array 300 is utilized to generate the dummy fill pattern for the metal-1 layer, then the metal-1 layer will only include dummy fill associated with regions 206 (see FIG. 2).
  • the simple configuration of cell 200 ensures that layer-to-layer interaction between the various dummy fill patterns is optimally reduced because there is no overlap between the different regions 202, 204, 206, 208.
  • Dummy fill cell 200 may be alternatively shaped and sized to suit the particular application.
  • regions 202, 204, 206, and 208 may be offset or staggered within cell 200 rather than symmetrical as depicted in FIG. 2.
  • the regions within cell 200 may be configured in accordance with a preferred dummy fill density for one or more of the material layers. Consequently, the simple non-overlapping configuration shown in FIG. 2 may not be appropriate for all applications because the effective dummy fill density for each layer may be too low (which can lead to nonuniform polishing).
  • FIG. 4 depicts an alternate dummy fill cell 400 that includes overlapping regions associated with the various material layers. As described above, overlapping regions may be necessary to provide a suitable dummy fill density for the material layers.
  • cell 400 includes regions associated with four metal layers. In particular, cell 400 includes regions associated with a polysilicon layer 402, a metal-1 layer 404, a metal-2 layer 406, a metal-3 layer 408, a metal-4 layer 410, and a metal-5 layer 412. As shown in FIG. 4, region 410 overlaps region 404 and region 412 overlaps regions 408 and 404.
  • region 410 metal-4
  • region 404 metal-1
  • region 404 metal-1
  • the overlapping associated with region 412 may be tolerable.
  • an amount of overlap between neighboring layers may be inevitable; the particular dummy fill cell may be suitably designed with such overlap in mind to thereby reduce the negative layer-to-layer interaction caused by the dummy fill.
  • the dummy fill cell may be suitably designed to contemplate the specific materials utilized for the various layers and the relative likelihood of interaction between such materials.
  • FIG. 5 depicts an exemplary mask pattern generation process 500 in accordance with the present invention.
  • Process 500 may be performed by a suitable computer to generate mask patterns for the various material layers within a semiconductor device.
  • Process 500 may begin with a task 502, which defines a suitable dummy fill cell for the particular semiconductor device.
  • Exemplary design parameters for the dummy fill cell include the desired dummy fill density for each material layer, the composition of the materials used for each layer, the circuit pattern for the various layers, the thickness of inter-layer dielectrics, and process parameters associated with the chemical mechanical polishing procedure (as described above).
  • a specific dummy fill cell may be utilized for more than one semiconductor device design.
  • a practical dummy fill cell preferably has at least a first portion associated with a first dummy fill material (for the first material layer) and a second portion associated with a second dummy fill material (for the second material layer).
  • the first and second portions or regions are configured to reduce unwanted electronic interaction between the first and second material layers, as described above.
  • a task 504 is conducted to form an array of the dummy fill cells designed during task 502.
  • the individual dummy fill cells may be arranged in any suitable manner within the array.
  • the individual dummy fill cells may be "tightly" configured or arranged with space between them according to the desired dummy fill density and other design parameters.
  • An exemplary dummy fill array is shown in FIG. 3.
  • a task 506 may be performed to obtain a circuit pattern associated with circuit areas for a first material layer.
  • circuit areas are the actual boundaries of the devices, circuits, line, traces, or the like, to be formed on the given material layer.
  • Circuit areas may be defined by data obtained during the design of the semiconductor circuit.
  • a circuit pattern associated with the circuit areas may be utilized during the generation of the mask pattern.
  • the circuit pattern may represent an oversized version of the circuit areas. The oversizing ensures that any dummy fill on the same material layer will not interact with the actual circuit areas. It should be appreciated that, for purposes of the present invention, the circuit pattern and the circuit areas may coincide and that the appropriate dummy fill pattern may be suitably designed to ensure that no unwanted intra- layer interactions occur.
  • a task 508 may be performed to isolate the dummy fill material (for the current material layer being processed) within the array to obtain an isolated dummy fill array that only contains regions identifying the current material layer. For example, with brief reference to FIG. 4, task 508 may manipulate the dummy fill array data such that only metal-1 regions 404 remains.
  • a task 510 may be performed to generate the final dummy fill pattern. Task 510 preferably subtracts the current circuit pattern data from the isolated dummy fill array obtained in task 508. The subtraction ensures that the final dummy fill pattern does not overlap areas on the first material layer associated with the current circuit pattern. In other words, the boundaries of the dummy fill pattern and the circuit pattern are nonintersecting.
  • a task 512 is performed to combine the data defining the actual circuit areas to the final dummy fill pattern.
  • Task 512 may be realized by performing a logical "OR" operation.
  • Task 512 suitably produces a mask pattern for the first material layer which includes circuit areas and dummy fill areas. This mask pattern may be suitably stored for subsequent patterning of the first material layer.
  • a query task 514 may be prompted.
  • Query task 514 determines whether mask patterns are to be generated for other material layers. If no other mask patterns need be generated, then process 500 ends. If, however, additional mask patterns need to be generated, then a task 516 is performed. Task 516 obtains the circuit pattern data associated with the next material layer (similar to task 506). Thereafter, process 500 is re-entered at task 508 to repeat the tasks necessary to generate the final mask pattern.
  • the dummy fill cell technique may be employed to reduce the amount of layer-to-layer interaction within a semiconductor device by intelligently arranging the dummy fill material on the different layers.
  • an additional aspect of the present invention may be utilized to further reduce the amount of layer-to-layer interaction by arranging the dummy fill material on a given layer in response to the circuit areas on one or more other layers. It should be noted that this aspect of the present invention may be utilized with or without the dummy fill cell as a foundation for each respective dummy fill pattern.
  • a number of layers that can potentially interact with each other are grouped together for analytical purposes and for the generation of preferred dummy fill patterns for each layer.
  • dummy fill on the metal-2 layer if located above a circuit line formed on the metal-1 layer or below a circuit line formed on the metal-3 layer, can cause undesired interaction between these layers.
  • a preferred dummy fill pattern for the metal-2 layer does not overlap circuit areas formed on at least the metal-1 and metal-3 layers.
  • the specific materials used for the various layers, the design of the dummy fill cell (if employed), and other process-based or circuit- based parameters, more or less layers may be considered.
  • FIG. 6 is a flow diagram of an exemplary mask production process 600 according to a preferred embodiment of the present invention.
  • the semiconductor device includes a metal-1 layer, a metal-2 layer, a metal-3 layer, a metal-4 layer, and a metal-5 layer.
  • the metal-1 layer is below the metal-2 layer, which is below the metal-3 layer, and so forth.
  • FIG. 7 depicts respective circuit patterns associated with circuit areas for the different metal layers (designated M-1 , M-2, M-3, M-4, and M-5).
  • the circuit patterns preferably represent oversized versions of the actual circuit data that defines the circuit areas.
  • process 600 may be performed to design a mask pattern for any multi-layer semiconductor device having more or less metal layers. Further, process 600 may additionally or alternatively contemplate an active layer, a polysilicon layer, or the like.
  • Process 600 is preferably performed to design the mask pattern for a specific material layer. As described above, process 600 also contemplates the layout of other material layers that may interact with the specific material layer.
  • the specified material layer being designed is the metal-3 layer and the interacting layers are presumed to be those layers immediately adjacent to the specified layer. Of course, depending upon the particular semiconductor device, an interacting material layer may be a nonadjacent layer.
  • Process 600 may begin with a task 602, which suitably obtains a first combined circuit pattern for the metal-2, metal-3, and metal-4 layers. As mentioned above, these three material layers are presumed to be susceptible to interlayer interaction, e.g., unwanted capacitances.
  • task 602 may access a suitable database containing previously designed circuit pattern data for the individual layers (e.g., as shown in FIG. 7).
  • task 602 may prompt a logical "OR" operation to combine the data for the three individual circuit patterns.
  • FIG. 8A depicts the first combined circuit pattern obtained by task 602.
  • a task 604 generates a first preliminary dummy fill pattern configured such that it does not overlap areas associated with the first combined circuit pattern.
  • the shaded portions of FIG. 8A represent the dummy fill areas.
  • the dummy fill areas may be associated with any given array of dummy fill segments, e.g., as described above in connection with the preferred dummy fill cell techniques.
  • a query task 606 may be performed to test whether the specified layer (the metal-3 layer in this example) can be included in any additional groupings of material layers that are susceptible to interlayer interaction. If additional interacting groups including the specified layer exist, then query task 606 preferably leads to a task 608.
  • Task 608 obtains the appropriate number of additional combined circuit patterns for additional groups of material layers including the specified layer. In the present example, task 608 may obtain a combined circuit pattern for the metal-1 , metal-2, and metal-3 layers (FIG. 8B) and a combined circuit pattern for the metal-3, metal-4, and metal-5 layers (FIG. 8C).
  • a task 610 suitably generates respective preliminary dummy fill patterns for each of the combined circuit patterns obtained in task 608 (task 610 is similar to task 604).
  • a task 612 is preferably performed.
  • a final dummy fill pattern for the specified material layer is created from the overlapping portions of the various preliminary dummy fill patterns.
  • task 612 may be associated with a logical "AND" operation performed for all of the preliminary dummy fill patterns.
  • FIG. 8D depicts the final dummy fill pattern for the present example.
  • the final dummy fill pattern may be alternately obtained in any suitable manner. For example, the circuit patterns for all layers grouped with the metal-3 layer can be combined together; the combined circuit pattern can then be subtracted from a full dummy fill pattern to obtain the final dummy fill pattern.
  • a task 614 may be performed to combine the final dummy fill pattern with the actual circuit data for the circuit areas on the specified material layer.
  • This task may be realized by a logical "OR" operation.
  • the final mask pattern associated with the metal-3 layer is shown in FIG. 8E.
  • the final mask contains the actual metal-3 circuit data located within an oversized "boundary” that separates the circuit data from the dummy fill.
  • the dummy fill has certain "cutout" portions that correspond to the circuit patterns of the metal-1 , metal-2, metal-4, and metal-5 layers as projected onto the metal-3 layer.
  • process 600 is utilized to determine the areas where dummy fill is to be applied, and an optimized dummy fill cell (as described above) is employed, then the final mask pattern will reduce the amount of layer-to-layer interaction present in the semiconductor device. For example, if only metal-1 and metal-2 are considered, then capacitive coupling may arise in the following manner: (1) metal-1 circuit areas to metal-2 circuit areas; (2) metal-1 circuit areas to metal-2 circuit areas via metal-1 dummy fill; or (3) metal-1 circuit areas to metal-2 circuit areas via metal-1 dummy fill and metal-2 dummy fill.
  • the use of an optimized dummy cell as described herein reduces (3), and the use of process 600 reduces (2).
  • dummy fill optimization may not be practical for all semiconductor devices and for all chemical mechanical polishing procedures.
  • the particular device and polishing recipe may dictate a minimum dummy fill density for one or more mate ⁇ al layers.
  • the dummy fill cell design and/or the dummy fill layout generated by process 600 may need to be modified to accommodate the specified minimum fill densities.
  • a number of practical considerations and design optimization schemes may be employed to increase the effectiveness of the above techniques while remaining within the given manufacturing process parameters. Such practical considerations and optimization schemes are beyond the scope of this description.
  • an improved technique for generating a dummy fill pattern for a semiconductor layer is provided.
  • the present invention provides a dummy fill technique that reduces the layer-to-layer interaction in a semiconductor circuit.
  • the preferred dummy fill technique considers the electrical performance of the semiconductor circuit in addition to the manufacturing requirements associated with chemical mechanical polishing processes utilized during the fabrication of the circuit.
  • the dummy fill pattern and corresponding mask pattern can be generated without a significant increase in computational load or manufacturing cost over prior art techniques.
  • the present invention has been described above with reference to preferred exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the preferred embodiment without departing from the scope of the present invention.
  • the specific material layers, the number of layers, and the circuit patterns can vary according to the particular semiconductor device.
  • the logical operations of combining, subtracting, or adding circuit patterns, dummy fill patterns, and the like may be implemented in any number of ways to produce the same result.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Un motif de remplissage fictif pour un composant à semi-conducteur multicouche est basé sur une cellule de remplissage fictif conçue de manière intelligente. Ledit motif de remplissage fictif est constitué d'un groupe de cellules de remplissage fictif. La cellule de remplissage fictif est configurée de sorte qu'elle réduise l'interaction intercouche indésirable, par exemple la capacité, entre des couches de matériaux différents dans un composant à semi-conducteur. La cellule de remplissage fictif comporte des régions associées à chacune des couches de matériaux, induisant le remplissage fictif. Par exemple, une région de la cellule de remplissage fictif peut être associée à une couche de métal 1 et une région séparée de la cellule peut être associée à une couche de métal 2. Les différentes régions sont configurées de sorte que la probabilité d'interaction intercouche soit réduite. Par ailleurs, le motif de remplissage fictif lui-même peut être conçu de manière intelligente en fonction des effets intercouches possibles. Le motif de remplissage fictif pour une première couche de matériau peut être conçue de manière appropriée de sorte que le remplissage fictif de la première couche de matériau ne se trouve pas au-dessus du motif du circuit pour la couche sous-jacente. De même, le remplissage fictif de la première couche de matériau peut être configurée de sorte qu'il ne se trouve pas au-dessous du motif du circuit pour la couche située au-dessus.
PCT/US1999/016794 1998-09-29 1999-07-23 Cellule de remplissage fictive pour la reduction de l'interaction intercouche WO2000019490A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16257998A 1998-09-29 1998-09-29
US09/162,579 1998-09-29

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WO2000019490A3 WO2000019490A3 (fr) 2002-01-10

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1310308C (zh) * 2001-10-24 2007-04-11 微米技术公司 对旋涂玻璃和有关自平坦化沉积生成填充图形
WO2009045613A1 (fr) * 2007-09-28 2009-04-09 Synopsys, Inc. Procédé et appareil pour effectuer un remplissage fictif par utilisation d'un ensemble de cellules de remplissage fictif
EP1336201B1 (fr) * 2000-11-23 2015-02-11 Infineon Technologies AG Systeme de circuit integre protege de l'analyse
DE102017117857A1 (de) * 2017-06-29 2019-01-03 Taiwan Semiconductor Manufacturing Co. Ltd. Integrierte Schaltkreis-Layouts mit Füllelementformen

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Publication number Priority date Publication date Assignee Title
US5278105A (en) * 1992-08-19 1994-01-11 Intel Corporation Semiconductor device with dummy features in active layers
US5459093A (en) * 1993-03-18 1995-10-17 Sony Corporation Method for forming dummy pattern in a semiconductor device
US5763955A (en) * 1996-07-01 1998-06-09 Vlsi Technology, Inc. Patterned filled layers for integrated circuit manufacturing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278105A (en) * 1992-08-19 1994-01-11 Intel Corporation Semiconductor device with dummy features in active layers
US5459093A (en) * 1993-03-18 1995-10-17 Sony Corporation Method for forming dummy pattern in a semiconductor device
US5763955A (en) * 1996-07-01 1998-06-09 Vlsi Technology, Inc. Patterned filled layers for integrated circuit manufacturing

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1336201B1 (fr) * 2000-11-23 2015-02-11 Infineon Technologies AG Systeme de circuit integre protege de l'analyse
CN1310308C (zh) * 2001-10-24 2007-04-11 微米技术公司 对旋涂玻璃和有关自平坦化沉积生成填充图形
WO2009045613A1 (fr) * 2007-09-28 2009-04-09 Synopsys, Inc. Procédé et appareil pour effectuer un remplissage fictif par utilisation d'un ensemble de cellules de remplissage fictif
US7681166B2 (en) 2007-09-28 2010-03-16 Synopsys, Inc. Method and apparatus for performing dummy-fill by using a set of dummy-fill cells
DE102017117857A1 (de) * 2017-06-29 2019-01-03 Taiwan Semiconductor Manufacturing Co. Ltd. Integrierte Schaltkreis-Layouts mit Füllelementformen
US11334703B2 (en) 2017-06-29 2022-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit layouts with fill feature shapes

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