、發明説明（ 具有破解保護的積體電路配置及製造該配置之方法 :^月係/歩及有基板的積體電路配置，該基板具有電路 疋件、以及_ ±· ^ # 坪命 一互連的接線板，並且也涉及製造一積 肢电路配置的方法。 4 、 攻2=電路中’特別是在智慧卡的使用，可能有潛在的 所^/積體電路的破解，所謂的"逆向工程,，，並使用 料二：、…來改變電路作業模式或執行該記憶體的資 =二::法可能導致不受歡迎的結果，特別是在安 Γ:。覆蓋晶片的物質，而且也是上層保護晶片接線 通常在此破解期間會被移除。接著顯露出來的 常是非安全有關的線路，可由所謂的旁路線繞 達w的層級和線路。現在只要花些許費用 可藉由’ΉΒ方法聚焦離子束„)執行這些步驟…旦到達 =與安全有關’因此也相當重要的線路’就可：在這 :ΓΛ非^彳™和脈衝（所謂的”時⑽㈣)），或 …些線路加上訊號以操縱資料(所、'強迫" (forcing))。 破L此二Γ目標曾經是要避免或者至少使積體電路的 ” ° 困難；一方面’達成這種目標的企圖，牽 涉到接線計劃中重要電路的隱藏架構， :由在相關接線板上覆蓋保護板的專屬應用裝置所 在使用保護板的情況下’該板稱為，，屏蔽"，今板 折的形狀或格子狀的線路’例如在保護板中成對存在，假 -4- 536799、 Explanation of the invention (Integrated circuit configuration with crack protection and method for manufacturing the configuration: ^ month system / 歩 and integrated circuit configuration with substrate, the substrate has circuit components, and _ ± · ^ # ping life one mutual Connected wiring board, and also involves a method of manufacturing an integrated circuit configuration. 4, attack 2 = circuit 'especially in the use of smart cards, there may be potential cracks in the integrated circuit, the so-called " Reverse engineering, and use materials 2 :, ... to change the circuit operation mode or execute the memory resources == 2 :: method may lead to undesired results, especially in the material that covers the wafer, and It is also that the upper-layer protection chip wiring is usually removed during this cracking. Then it is revealed that often non-safety-related lines can be bypassed to the level and line of w by the so-called bypass line. Now for a small fee, the method can be used Focusing the ion beam…) Perform these steps ... Once you reach = safety-relevant 'and therefore very important lines' is OK: here: ΓΛ 非 ^ 彳 ™ and pulses (so-called ”)), or ... some lines Coupled to manipulate data signal (the 'forced " (forcing)). The goal of breaking the two Γ was to avoid or at least make integrated circuits "° difficult; on the one hand, the attempt to achieve this goal involves the hidden architecture of important circuits in the wiring plan: it is covered by the relevant wiring board In the case of using the protection board where the exclusive application device of the protection board is used, 'the board is called, the shield', the shape of the folded board or the grid-like circuit ', for example, exists in pairs in the protection board, false -4- 536799
、發明説明（ 使某一部份發生中斷 残庫哭 一 ，板上將出現不同電壓，偵測 饫應杰就會啟動記憶體的消 無法作用。這此被稱m 或使其他電路區域 連接…= 動，，線路，同樣可以具體化為無 堤镬、然電壓的線路。在 受攻墼m、、 、匱況下，他們的作用只是在遭 增加複雜性或混淆攻擊者的視聽。 藉由上述被動線路可增加兮 杈組的安全性，在接線計劃 ^该被動線路也可由所謂的主動 ΛΑ ^ ; 土動綠路來取代。在使用主 、、’路的彳月況下’訊號會由驅動 ,μ ^上. 田^勁包路傳輸到屏蔽線路上， 此日才该訊號由評估電路加以破 解亚與例如參考訊號比較。 由於可能的訊號變化，在這愔 牡、it况下，屏蔽只能利用FIB方法 在四周環繞非常複雜的旁路線。 、 雖然傳統的邏輯模組積體電路 入 电吟主要疋以手動控制設計（ 用相I:汁)：式，衣造’但是人工處理或影響可能造成費 “南，特別疋在合成邏輯的情況，該方法是到目前為 止接受度最大的一種作法。 在這個方法中，物件的功能和關係以較高層級的程式任 言例如VHDL來加以公式化，並由_編輯程式轉譯、 Explanation of the invention (Make a part of the library break and cry for a while, different voltages will appear on the board, and the detection of Yingyingjie will start the memory erasure. This is called m or other circuit areas connected ... = Motion, lines can also be embodied as lines without banks and natural voltages. Under attack conditions m,, and, their role is only to increase complexity or confuse the audiovisual of the attacker. By The above-mentioned passive line can increase the safety of the branch group. In the wiring plan ^ the passive line can also be replaced by the so-called active ΛΑ ^; earth moving green road. In the case of using the main and road, the signal will be changed by Drive, μ ^. The field signal is transmitted to the shielded line. Only today is the signal to be cracked by the evaluation circuit and compared to the reference signal. Due to possible signal changes, in this case, it is shielded. Only the FIB method can be used to surround very complicated bypass lines. Although the traditional logic module integrated circuit is mainly used to control the design (using phase I: juice): type, clothing manufacturing, but manual processing or Shadow This may be the cause of Fei Nan, especially in the case of synthetic logic. This method is by far the most accepted method. In this method, the functions and relationships of objects are implemented by higher-level programmatic statements such as VHDL. Formulated and translated by editor
線計劃。由於屏蔽線的保護屬性，I 又蜀「王不自與貫際電路無關的 功能’且與他們的空間位置有關’但是這些不能夠在合成 方法中修正’假使是使用這個方法，不幸地只有在精後接 線計劃才可以人工加入保護才反，這需要增加額外的費用， 所以與建立積體電路時所需要的效率和時間優勢的要求相 互抵觸。 在巧情況下，只有以合成方法建立的積體電路特別容易 -5- 本纸張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 536799 五、發明説明（3 叉到攻擊，因為大部份接線都在比較 ::路:一。因此，可能的攻擊二直IS =、與安全有關的重要線路，例如使用針從尖令測定： 置進入，而不會碰到上層接線板上的線路。 士發明的目的是要提供一種積體電路配置和—種 ㈣配置的方法’該配置提供一種高度保護，以對抗二 外部攻擊的破解方法，而且具有低複雜度和&成本的㈣ ，特別適用以合成方法建立接線計劃的情況。 ‘ 根據本發明專利申請範圍帛i項和第6項之方法 該目的。 J -種晶片堆疊’其中破解將藉由互連來避免，—揭露於 00/673 19 A1 中。 本發明揭示一種積體電路配置，其中佔有最大部份的互 連可用於各個板子’藉由以互連填人可支援積體電路所希 望的功能_置無互連區域，㈣護該㈣電路。一方面 ’對於可能攻擊者所使用的逆向工程，這增加每片接線板 需要檢查的互連數量；另一方面’可能的攻擊者無法一開 始就確定接線板中的哪些互連是用於實際積體電路，而哪 些互連只是來保護電路的。因此優點為：在接線板上填入 及結合兩種互連配置，會在逆向工程中增加極大的複雜性 鴯 裝 線 根據本發明的積體電路配置，可包括具有主動電路元件 的基板，以及不使用主動電路元件的積體電硌配置例如倒 裝晶片，後者通常會再一次由有圖案的一側，倒轉及結合 -6 - 本紙狀度適财S g家標準(CNS) A4規格(210X297公董）Line plan. Due to the protective properties of the shielded wires, I also said that "Wang Buzi's functions that have nothing to do with the inter-circuits are related to their spatial location", but these cannot be modified in the synthesis method. "If this method is used, unfortunately only in Only after the precise wiring plan can the protection be added manually, this requires additional costs, so it conflicts with the requirements of efficiency and time advantage required when building integrated circuits. In coincidence, only the products built by synthetic methods The body circuit is especially easy. -5- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 536799. 5. Description of the invention (3 forks to attack, because most of the wiring are being compared :: 路: 1. Therefore, possible attacks are straight IS =, important lines related to security, such as using a needle to determine from the tip: without entering the upper wiring board. The purpose of the invention is to provide a Integrated circuit configuration and a method of configuration configuration This configuration provides a high degree of protection against cracking methods of external attacks, and has low complexity and & ㈣, especially suitable for the case of establishing a wiring plan by a synthetic method. 'The purpose according to the method of item 帛 i and item 6 of the scope of the patent application of the present invention. J-A kind of wafer stack' in which cracking will be avoided by interconnection,- Disclosed in 00/673 19 A1. The present invention discloses an integrated circuit configuration in which the largest part of the interconnection can be used for each board. 'By filling in the interconnect, people can support the desired function of the integrated circuit. Interconnection area to protect this circuit. On the one hand, 'for reverse engineering used by a possible attacker, this increases the number of interconnections that need to be checked per patch panel; on the other hand,' a possible attacker cannot determine the wiring at the beginning. Which interconnections in the board are used for the actual integrated circuit, and which interconnections are only used to protect the circuit. Therefore, the advantage is: filling and combining the two interconnection configurations on the wiring board will greatly increase the reverse engineering. Complex mounting line According to the integrated circuit configuration of the present invention, it may include a substrate having active circuit elements, and an integrated circuit configuration such as a flip chip without using active circuit elements. The latter will usually be reversed and combined from the patterned side again. -6-This paper is suitable for commercial use (CNS) A4 specification (210X297).
元A:主動包路兀件基板的結構側上。根據本發明，這此 凡件再_二々么士人士 、’。口在一起’以精確地製造電路配置。 八：：中將明白指itj ’根據本發明，電路元件這個詞也包 壯曰、α此’積體電路配置根據本發明也可以在上述倒 :曰片中使用’例如只包括互連，因此可以用於包含主 免路元件的晶片，為其提供有力的保護。 根據本發明製造配置的方4 ’經證明特別有利於使用合 、'方法所製造的積體電路。以合成方法在上層接線板中未 所覆蓋、因此顯露出來的重要互連，以及在較深層 可覆盍住的重要互連，根據本發明，藉由填入正位於互連 之上的閒置無互連區域，在合成方法結束後，當作積體電 路的保4。但是’本發明在合成方法之前或當時所想出的 應用’透過此說明也必須列入考慮。根據本發明的配置和 方法’較好藉由理想上依照合成方法的填人程式來加以實 現。除了速度的優點，藉由修改積體電路的接線計劃來建 立新的模組版本，同樣可以建立—全新的保護線接線計劃 。因此，用於逆向工程的破解，不只需要檢查某一模組版 本與下一版本的微幅差異，還必須以極高的成本來執行更 新。 在本積體電路配置中’不需要提供一個專屬板用於保護 互連，因為對應的互連位於完成的接線板中，不必花費額 外費用來建構金屬板。另一方面，假使積體電路在全自訂 設計中建立時，也可獲得這個經濟上的優點，如果對應的 保護互連填入或置入手動組合程式庫模組或互連的閒置區 本紙張尺度適用中國國家標準(CNS) Α4規格(210X 297公釐) 536799 A7 B7 五、發明説明（8 ) 參考符號清單 1 閒置無第一互連的區域 Γ 閒置無第一互連的封閉區 9 基板 10 第一金屬板 11 第二金屬板 12 第三金屬板 13 第四金屬板 20 第一互連（整體） 21 第一金屬板上的重要互連 22 弟'一金屬板上的重要互連 23 第三金屬板上的重要互連 30 作為保護之用的第二互連（整體） 31 第四金屬板的曲折形互連 32 第三金屬板的曲折形互連 33 與23平行擴展的互連 34 無連接的互連 ΤΙ- T4 電晶體 αα nsL Gl- G3 閘電極 S1- S3 源極區域 Dl- D3 >及極區域 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 x 297公釐）Element A: On the structural side of the active package circuit board. According to the present invention, all these things are again ___________, ’. Port together 'to precisely manufacture the circuit configuration. Eight: The lieutenant clearly refers to itj 'according to the present invention, the word circuit element also includes Zhuang, α this' integrated circuit configuration according to the present invention can also be used in the above-mentioned: said only includes interconnection, so Can be used for wafers containing main bypass components to provide strong protection. The method of manufacturing a configuration 4 'according to the present invention has proven to be particularly advantageous for integrated circuits manufactured using the combined method. Important interconnections that are not covered in the upper-layer wiring board and are thus exposed by a synthetic method, and important interconnections that can be trapped at a deeper level, according to the present invention, The interconnection area is used as a guarantee for the integrated circuit after the synthesis method is completed. However, "the application of the present invention before or at the time of the synthesis method" must also be taken into consideration through this description. The configuration and method according to the present invention are preferably implemented by a human fill-in program ideally according to a synthetic method. In addition to the advantages of speed, you can also create a new module version by modifying the wiring plan of the integrated circuit-a new protection wire wiring plan. Therefore, for reverse engineering cracking, it is not only necessary to check the slight difference between a module version and the next version, but also to perform the update at a very high cost. In this integrated circuit configuration, it is not necessary to provide a dedicated board for protecting the interconnections, as the corresponding interconnections are located in the finished wiring board, and no extra cost is required to construct the metal plate. On the other hand, if the integrated circuit is established in a fully custom design, this economic advantage can also be obtained. If the corresponding protection interconnect is filled or placed in the manual combined library module or the idle area of the interconnect, Paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) 536799 A7 B7 V. Description of invention (8) Reference symbol list 1 Idle area without first interconnect Γ Idle area without first interconnect 9 Substrate 10 First metal plate 11 Second metal plate 12 Third metal plate 13 Fourth metal plate 20 First interconnection (overall) 21 Important interconnection on the first metal plate 22 Important interconnection on the first metal plate 23 Important interconnection on the third metal plate 30 Second interconnection (integral) for protection 31 Zigzag interconnection of the fourth metal plate 32 Zigzag interconnection of the third metal plate 33 and 23 Even 34 unconnected interconnection Ti-T4 transistor αα nsL Gl- G3 gate electrode S1- S3 source area D1- D3 > and pole area-11-this paper size applies to China National Standard (CNS) A4 specification (210 x 297 mm)