WO2022161590A1 - Obscurcissement physique de matériel par couplage capacitif - Google Patents

Obscurcissement physique de matériel par couplage capacitif Download PDF

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Publication number
WO2022161590A1
WO2022161590A1 PCT/EP2021/051655 EP2021051655W WO2022161590A1 WO 2022161590 A1 WO2022161590 A1 WO 2022161590A1 EP 2021051655 W EP2021051655 W EP 2021051655W WO 2022161590 A1 WO2022161590 A1 WO 2022161590A1
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cell
additional
obfuscation
lines
obfuscated
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PCT/EP2021/051655
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English (en)
Inventor
Samuel Nascimento PAGLIARINI
Pablo Ilha VAZ
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Tallinn University Of Technology
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Priority to PCT/EP2021/051655 priority Critical patent/WO2022161590A1/fr
Publication of WO2022161590A1 publication Critical patent/WO2022161590A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
    • G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/16—Obfuscation or hiding, e.g. involving white box

Definitions

  • IP intellectual property
  • the present invention relates to a practical approach to change this landscape.
  • this invention introduces a novel obfuscation technique capable of hardening for an attacker to hypothesize about the functionality of the recovered structures from a layout.
  • U.S. patent US6924552B2 discloses a method of designing a multilayered integrated circuit. Said document describes the circuit comprised of at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer.
  • the main drawback of said method is that the inserted conductive lines do not alter the functionality of a circuit. An adversary may replicate the entire circuit even if he/she does not understand the reason behind the insertion of said lines. Said method does not present a key-based operation such as the one herein described.
  • U.S. patent US7288786B2 discloses that during the creation of wiring planes for logic modules, the regions which are left free of interconnects by synthesis methods in upper metal planes are filled to a maximum degree with further interconnects. These interconnects are meant to protect the integrated circuit and are embodied as sensor interconnects or else as connectionless interconnects only to confuse potential hackers. The drawback of such method is that the sensors are effective against probing attacks, no protection is offered against reverse engineering in a broad sense. An adversary may replicate the entire circuit, including the sensors, even if he/she does not understand the reason behind the insertion of said lines.
  • U.S. patent US5783846A discloses a method to protect an integrated digital circuit from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants in the substrate rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernible channel stops so that all cells falsely appear to have a common interconnection scheme.
  • the major drawback of said method is that it is not compatible with current IC fabrication practices, where metalized connections are the norm.
  • the fundamental concept of obfuscation techniques is to include elements that conduct a functional misdirection of the design characteristics, thus hardening for the attacker to hypothesize about or recover the design’s real functionality.
  • the technical problem to be solved with the present invention is to provide a method for obfuscation of ICs using standard fabrication practices/processes, which renders ICs non-functional when produced by unauthorized replication, even if the copier replicates the entire circuit.
  • Standard cells contain transistors, layer(s) of metallization for local routing, and vias/contacts for connections between distinct layers. Standard cells are classified as sequential or combinational. Examples of sequential cells are flip-flops and latches, while ANDs, ORs, XORs, NANDs, are examples of combinational cells.
  • sequential cells are flip-flops and latches
  • ANDs, ORs, XORs, NANDs are examples of combinational cells.
  • obfuscation is achieved by a capacitive coupling mechanism that changes the timing behavior of a specific cell.
  • a cell with a modified timing behavior is thus termed an obfuscated cell.
  • obfuscated cell In order to obfuscate the IP of an IC, only a fraction of its cells can be replaced for the obfuscated equivalents.
  • the capacitive coupling mechanism at the center of the present invention works as follows: standard cells contain transistors and some amount of local routing. According to present invention, no changes are made to the transistors (i.e., no device layers are modified). Instead, according to invention, additional metal lines are drawn, mostly parallel to the existing internal routing, thus promoting capacitive coupling between the newly formed parallel plates of the metallization. These parallel lines remain preferably within the boundaries of the cell for compatibility with current standard-cell based placement and routing. The new cell layout, now containing these additional lines, is termed an obfuscated cell.
  • capacitive coupling is perceived as a parasitic effect and is undesirable.
  • said capacitive coupling is used to create a communication channel that enables obfuscation.
  • the promoted parallel lines display a victim-aggressor behavior: the internal routing of the cell is the victim and the additional line(s) drawn around it are the aggressor(s).
  • the victim line will transition between logic high and logic low values. If the aggressor is driven with a voltage pulse that creates a transition in the opposite direction, the timing of the victim is slowed down. The opposite happens when the aggressor is transitioning in the same direction, i.e., the timing of the victim signal is accelerated. From this observation, according to the invention, a key-based obfuscation scheme is built.
  • Each obfuscated cell is given a new input termed key input K that controls the timing behavior of the obfuscated cell.
  • Each obfuscated cell is also given a small circuit that translates the binary input K into a voltage pulse.
  • the transitions align e.g., the pulse rising edge aligns with an also rising internal signal
  • the aforementioned acceleration takes place.
  • the falling edge of the pulse aligns with an internal signal that is rising a slowed down timing is achieved.
  • the pulsegen circuit is identical for all obfuscated cells as not to give hints of what is the intended functionality, which is entirely determined by the arrival time of the key input K.
  • the key input K drives the pulsegen circuit, which in turn drives the aggressor line with a specific voltage at a specific time, thus making the obfuscated cell either a faster or a slower version of the original cell.
  • the pulsegen circuit drives the aggressor line with a specific voltage at a specific time, thus making the obfuscated cell either a faster or a slower version of the original cell.
  • no physical connections are made between the new elements of the obfuscated cells and the transistors and wires that were part of the original cell layout.
  • a strategy is put in place for selecting cells that will alter the behavior of the IC when they are either accelerated or slowed down.
  • Cells that belong to long paths i.e., critical paths
  • cells that are present in short paths are good candidates for obfuscation since they may cause the circuit to violate hold timing if cells in that path compute rather too quickly. In either case, the outcome is that the outputs of the IC will differ from the expected and therefore obfuscation is achieved.
  • Each obfuscated cell takes a 1-bit key input K , while the aggregate key for unlocking the entire IC is n -bits long, where n is the number of cells selected for obfuscation.
  • the approach herein described requires no special fabrication structures or processes other than standard CMOS devices and can be fully adopted in IC design as it does not contradict current practices of the industry that rely on standardized cells; our obfuscated cell remains a standard cell.
  • the pulsegen circuit can be built with standard cells as well.
  • the approach for obfuscation does not target a specific region of an IC, but rather specific cells are selected as targets for obfuscation.
  • Cells are chosen based on the paths they are part of. Cells belonging to long paths and short paths are good candidates and there are plenty of those in every IC.
  • standard cells in modern ICs have one and at max two layers of metals (conductive layers) inside them, depending on the specifics of a given technology.
  • the entire IC typically has ⁇ 10 layers of metals.
  • preferred option metal lines are added on the same layer of the standard cell if there is headroom.
  • the lines are sized according to an algorithm. Taking into account the original layout of the cell being obfuscated, according to the invention, the occurrence of parallel running lines on the same layer is maximized. This is the preferred approach because it creates side walls between the lines, which are highly capacitive in nature. In addition, it is possible, that lines in different layers (i.e., on top of each other) are used to create capacitive coupling, but this effect is much less pronounced.
  • So-called flip-flop cells often take ⁇ 50% of the area of a digital circuit, so there are always good obfuscation targets to choose from.
  • Digital ICs usually make use of D-type flip-flops, either in its standard configuration or in a scan version.
  • additional lines are drawn in parallel to the clock wires that are part of the original flip-flop cell layout.
  • the clock signal determines the temporal behavior of a flip-flop.
  • the parallel lines can effectively accelerate or delay the clock arrival time, thus accelerating or delaying the entire flip-flop.
  • present invention provides a method for physical obfuscation of multilayered integrated circuit (IC) through capacitive coupling, comprising steps, where on the multilayered integrated circuit (IC) layout to be fabricated comprising on a substrate number of different layers, where at least one layer is metallic conductive layer comprising conductive lines for carrying electrical signals among components of the integrated circuit, said components comprising logic cells, at least one cell is selected for obfuscation.
  • steps where on the multilayered integrated circuit (IC) layout to be fabricated comprising on a substrate number of different layers, where at least one layer is metallic conductive layer comprising conductive lines for carrying electrical signals among components of the integrated circuit, said components comprising logic cells, at least one cell is selected for obfuscation.
  • additional parallel conductive lines are added to the integrated circuit (IC) layout, where said additional conductive lines are not connected to the cell selected for obfuscation, and said conductive lines are placed parallel with at least one conductive line connected to said cell to be obfuscated.
  • IC integrated circuit
  • Said additional conductive lines are configured to enable capacitive coupling between said additional conductive lines and said conductive lines (wires) connected to the selected cell.
  • said cells selected for obfuscation are so called flip-flop cells.
  • said additional parallel lines are placed parallel to the clock wires of obfuscated cell and are configured to accelerate or delay clock signal due to capacitive coupling with said additional lines.
  • a pulse generator circuit is annexed to said obfuscated cells and is responsible for creating a voltage pulse at a given time, controlled by the arrival of the input signal K .
  • the first aspect of the present invention relates to a method for physical obfuscation of multilayered integrated circuit (IC) through capacitive coupling, where on the multilayered integrated circuit (IC) layout to be fabricated comprising on a substrate number of different layers, where at least one layer is metallic conductive layer comprising conductive lines for carrying electrical signals among components of the integrated circuit, said components comprising logic cells, at least one cell is selected for obfuscation.
  • IC integrated circuit
  • additional parallel conductive lines are added to the integrated circuit (IC) layout into said metallic conductive layer comprising conductive lines, where said additional conductive lines are not connected to the cell selected for obfuscation, and said conductive lines are placed parallel with at least one conductive line connected to said cell to be obfuscated.
  • said additional conductive lines are configured to enable capacitive coupling between said additional conductive lines and said conductive lines (wires) connected to the selected cell.
  • At least one of said additional parallel conductive lines are connected to a pulse generator circuit.
  • said obfuscated cells are flip-flop cells.
  • said additional parallel lines are placed parallel to the clock wires of obfuscated cell and are configured to accelerate or delay clock signal due to capacitive coupling with said additional lines.
  • At least one additional parallel conductive line for each obfuscated cell is connected to an individual pulse generator circuit.
  • said additional lines added for obfuscation are placed to enable capacitive coupling with said flip-flop cell.
  • an additional inverter is added, where said additional lines added for obfuscation are placed to enable capacitive coupling with said flip-flop cell.
  • this added inverter in the signal input line deliberately changes the timing of signal in said line, in other words said added inverter prolongs the signal path and as a result said inverter violates the timing window of the circuit.
  • To compensate right key must be applied, which accelerates the input signal.
  • the second aspect of the present invention relates to an integrated circuit (IC) comprising physical obfuscation of cells according to a method of claim 1, said integrated circuit comprising on a substrate number of different layers, where at least one layer is metallic conductive layer comprising conductive lines for carrying electrical signals among components of the integrated circuit, said components comprising logic cells, where said metallic conductive layer in the layout near the obfuscated cell, comprises additional parallel conductive lines, where said additional conductive lines are not connected to the obfuscated cell, and said conductive lines are placed parallel with at least one conductive line connected to said obfuscated cell.
  • IC integrated circuit
  • At least one of said additional parallel conductive lines are connected to a pulse generator circuit.
  • said key generator circuit is configured to generate a pulse, when clock signal is transitioning.
  • At least one additional parallel conductive line for each obfuscated cell is connected to an individual pulse generator circuit.
  • said additional lines added for obfuscation are placed to enable capacitive coupling with said flip-flop cell.
  • an additional inverter is added, where said additional lines added for obfuscation are placed to enable capacitive coupling with said flip-flop cell.
  • the obfuscation method of invention makes use of standard IC fabrication processes and makes use of normally undesirable parasitic capacitive coupling for obfuscation selected cells in the IC.
  • the IC protected by said obfuscation method is rendered useless for the unauthorized copier even if the entire IC is copied one to one – without knowing when to apply the pulses to the obfuscated cells (via the key input K) of the original IC in order to make them function correctly, the entire copied IC is rendered useless.
  • the proposed approach introduces elements at the layout level that, by taking advantage of communication based on capacitive coupling (i.e., crosstalk), obfuscate the real behavior of the circuit and give it a key-based operation.
  • capacitive coupling i.e., crosstalk
  • Figure 1 depicts an example of so-called long path
  • Figure 2 depicts another example of a so-called long path where the launch flip-flop is obfuscated
  • Figure 3 depicts another example of a so-called long path where the capture flip-flop is obfuscated
  • Figure 4 depicts an example of so-called short path
  • Figure 5 depicts on the left a symbol of a D-type flip-flop, and on the right, a layout of a typical D-type flip-flop
  • Figure 6 depicts on the left a symbol an obfuscated D-type flip-flop, and on the right, on the right is depicted a first embodiment of a layout of a typical obfuscated D-type flip-flop
  • Figure 7 depicts on the left a symbol an obfuscated D-type flip-flop, and on the right, on the right is depicted a second embodiment of a layout of a typical o
  • Figure 1 depicts an example of so-called long path, where the path starts at the launch flip-flop (FF) on the left, goes through a series of inverters, and then reaches the capture flip-flop on the right.
  • the computation here takes place in exactly one full clock cycle, such that when the next clock edge is seen by the capture FF, the signal available on the input D is stable.
  • Figure 2 depicts a modified long path where obfuscation takes place at the launch FF.
  • This inverter can be part of the original design or added on purpose, the effect being that this path violates setup timing: it is not able to generate a stable input at the D pin of the capture FF. For this path to still respect setup timing, it requires more time for its computation to take place.
  • the alternative is to have an early arrival of the clock signal at the launch FF by setting the key input K with the right value at the right time. If an adversary sets the key input K as 0, no pulse is generated and this path will not respect timing. If an adversary sets the key input K as 1, the path may behave as expected depending on the timing of the pulse generation. If the rising edge of the pulse aligns with the rising edge of the signal and if the capacitive coupling effect is pronounced enough, this path will respect timing. If the pulse does not align with the clock in this specific manner, the path would not respect setup timing.
  • Figure 3 depicts a modified long path where obfuscation takes place at the capture FF.
  • This inverter can be part of the original design or added on purpose, the effect remains that this path violates setup timing: it is not able to generate a stable input at the D pin of the capture FF. For this path to respect setup timing, it requires more time for its computation to take place.
  • the alternative is to have a late arrival of the clock signal at the capture FF by setting the key input K with the right value at the right time. If an adversary sets the key input K as 0, no pulse is generated and this path will not respect timing. If an adversary sets the key input K as 1, the path may behave as expected depending on the timing of the pulse generation. If the falling edge of the pulse aligns with the rising edge of the clock signal and if the capacitive coupling effect is pronounced enough, this path will respect timing. If the pulse does not align with the clock in this specific manner, the path would not respect setup timing.
  • Figure 4 depicts an example of so-called short path, where the path starts at the launch flip-flop (FF) on the left, goes through a single inverter, and then reaches the capture flip-flop on the right.
  • This path respects hold timing while the computation here takes place in a very short time, much shorter than one clock cycle.
  • the launch FF would be obfuscated, any pulse that causes an early arrival time of the clock leads to a corrupted computation as the path would no longer respect hold timing.
  • an adversary is not able to simply catalog flip-flops as launch or arrival ones for deriving keys: in Figure 2 is shown a case where a launch FF has to be accelerated, while here we have a case of a launch FF that cannot be accelerated.
  • Figure 5 comprises on the left a symbol of a D-type flip-flop with inputs D (data), C (clock), and outputs Q and Qbar, and on the right, a layout of a typical D-type flip-flop with its 4 stages: clock driver, master latch, slave latch, output driver.
  • Poly lines are hachured, pins are dark rectangles, metal lines are white rectangles, and contacts to diffusion are crosses. Several details are omitted for clarity, including all diffusions. As it can be seen from the Figure 5, the lines in charge of clock distribution span across a long distance.
  • Figure 6 comprises on the left a symbol of an obfuscated D-type flip-flop with inputs D (data), C (clock), K (key), and outputs Q and Qbar, and on the right is depicted a layout of a typical D-type flip-flop as depicted in Figure 5.
  • stage On the left is the additional pulsegen circuit (stage), which is responsible for driving the aggressor metal line with a key-controlled value.
  • the added aggressor line does not intersect nor does it contain a contact to lower or upper layers (i.e., no crosses appear on top of the original layout).
  • the clock bar line is sandwiched between two aggressor lines for increasing the coupling effect.
  • Figure 7 comprises on the left a symbol of an obfuscated D-type flip-flop with inputs D (data), C (clock), K (key), and outputs Q and Qbar.
  • D data
  • C clock
  • K key
  • Q output
  • Qbar output
  • Figure 7 a layout of a typical D-type flip-flop as depicted in Figure 5.
  • the additional pulsegen circuit (stage) is on the left.
  • the aggressor line runs parallel to the clock line, but the effect of capacitive coupling is less pronounced.
  • pulsegen pulse generator circuit
  • the clock signal determines the temporal behavior of a flip-flop. This can effectively accelerate or delay the clock arrival time, thus accelerating or delaying the entire flip-flop.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un procédé d'obscurcissement physique d'un circuit intégré multicouche par couplage capacitif. Selon l'invention, dans la couche conductrice métallique dans la disposition à proximité de la cellule sélectionnée pour l'obscurcissement, des lignes conductrices parallèles supplémentaires sont ajoutées à la disposition de circuit intégré (IC) dans ladite couche conductrice métallique comprenant des lignes conductrices. Lesdites lignes conductrices supplémentaires ne sont pas connectées à la cellule sélectionnée pour l'obscurcissement, et lesdites lignes conductrices sont placées de façon parallèle à au moins une ligne conductrice connectée à ladite cellule devant être obscurcie. Lesdites lignes sont conçues pour permettre un couplage capacitif entre lesdites lignes conductrices supplémentaires et lesdites lignes conductrices connectées à la cellule sélectionnée.
PCT/EP2021/051655 2021-01-26 2021-01-26 Obscurcissement physique de matériel par couplage capacitif WO2022161590A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5783846A (en) 1995-09-22 1998-07-21 Hughes Electronics Corporation Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering
US6924552B2 (en) 2002-10-21 2005-08-02 Hrl Laboratories, Llc Multilayered integrated circuit with extraneous conductive traces
US7288786B2 (en) 2000-11-23 2007-10-30 Infineon Technologies A.G. Integrated circuit configuration with analysis protection and method for producing the configuration

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5783846A (en) 1995-09-22 1998-07-21 Hughes Electronics Corporation Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering
US7288786B2 (en) 2000-11-23 2007-10-30 Infineon Technologies A.G. Integrated circuit configuration with analysis protection and method for producing the configuration
US6924552B2 (en) 2002-10-21 2005-08-02 Hrl Laboratories, Llc Multilayered integrated circuit with extraneous conductive traces

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ANONYMOUS: "Wire Modelling, Cross-talk & Double-switching", 24 February 2018 (2018-02-24), pages 1 - 10, XP055845307, Retrieved from the Internet <URL:http://www.signoffsemi.com/wire-modelling-cross-talk/> [retrieved on 20210928] *
ARUNKUMAR VIJAYAKUMAR ET AL: "Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device- and Logic-Level Techniques", ARXIV.ORG, CORNELL UNIVERSITY LIBRARY, 201 OLIN LIBRARY CORNELL UNIVERSITY ITHACA, NY 14853, 2 October 2019 (2019-10-02), XP081502045, DOI: 10.1109/TIFS.2016.2601067 *
CHEN WEIYU ET AL: "Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs", PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE. ITC '97. WASHINGTON, DC, NOV. 1 - 6, 1997., 1 June 1997 (1997-06-01), US, pages 809 - 818, XP055845295, ISBN: 978-0-7803-4210-1, Retrieved from the Internet <URL:https://ece.northeastern.edu/courses/ece3890/2002fa/deepsmd/reference_3.pdf> *

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