CN102063584A - 芯片攻击保护 - Google Patents
芯片攻击保护 Download PDFInfo
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- CN102063584A CN102063584A CN2010105269660A CN201010526966A CN102063584A CN 102063584 A CN102063584 A CN 102063584A CN 2010105269660 A CN2010105269660 A CN 2010105269660A CN 201010526966 A CN201010526966 A CN 201010526966A CN 102063584 A CN102063584 A CN 102063584A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2208—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/86—Secure or tamper-resistant housings
- G06F21/87—Secure or tamper-resistant housings by means of encapsulation, e.g. for integrated circuits
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Abstract
Description
Claims (40)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IL173341 | 2006-01-24 | ||
IL173341A IL173341A0 (en) | 2006-01-24 | 2006-01-24 | Chip attack protection |
IL175902 | 2006-05-24 | ||
IL175902A IL175902A0 (en) | 2006-05-24 | 2006-05-24 | Chip attack protection |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200680053967XA Division CN101501840B (zh) | 2006-01-24 | 2006-12-11 | 芯片攻击保护 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102063584A true CN102063584A (zh) | 2011-05-18 |
CN102063584B CN102063584B (zh) | 2012-12-05 |
Family
ID=38309592
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2010105269660A Expired - Fee Related CN102063584B (zh) | 2006-01-24 | 2006-12-11 | 芯片攻击保护 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7966666B2 (zh) |
EP (2) | EP1977481B1 (zh) |
CN (1) | CN102063584B (zh) |
HK (2) | HK1129772A1 (zh) |
IL (1) | IL192916A (zh) |
WO (1) | WO2007086046A2 (zh) |
Cited By (4)
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CN105474390A (zh) * | 2013-07-02 | 2016-04-06 | 秦内蒂克有限公司 | 电子硬件组件 |
CN106960842A (zh) * | 2015-12-29 | 2017-07-18 | 智能Ic卡公司 | 用于保护集成电路器件的系统和方法 |
CN107850995A (zh) * | 2015-01-09 | 2018-03-27 | 斯坦福国际研究院 | 不可克隆的rfid芯片和方法 |
CN109659279A (zh) * | 2017-10-11 | 2019-04-19 | 意法半导体(鲁塞)公司 | 用于检测集成电路中的差分故障分析攻击和对衬底的减薄的方法以及相关集成电路 |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101299602B1 (ko) * | 2007-03-27 | 2013-08-26 | 삼성전자주식회사 | 리버스 엔지니어링을 보호하는 집적회로 |
EP2019425A1 (en) * | 2007-07-27 | 2009-01-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
DE102007051788A1 (de) | 2007-10-30 | 2009-05-14 | Giesecke & Devrient Gmbh | Halbleiterchip mit einer Schutzschicht und Verfahren zum Betrieb eines Halbleiterchip |
EP2300954B1 (en) | 2008-06-24 | 2014-12-03 | NDS Limited | Security within integrated circuits |
JP5482048B2 (ja) * | 2009-09-18 | 2014-04-23 | ソニー株式会社 | 集積回路および電子機器 |
US10678951B2 (en) * | 2011-10-24 | 2020-06-09 | Maxim Integrated Products, Inc. | Tamper detection countermeasures to deter physical attack on a security ASIC |
KR20140034332A (ko) * | 2012-08-14 | 2014-03-20 | 삼성전자주식회사 | 보안 장치 및 이를 구비하는 집적 회로 |
US9329147B1 (en) * | 2014-12-22 | 2016-05-03 | International Business Machines Corporation | Electronic data security apparatus |
FR3039926A1 (fr) * | 2015-08-04 | 2017-02-10 | Commissariat Energie Atomique | Procede d'assemblage de dispositifs electroniques |
EP3147830B1 (en) | 2015-09-23 | 2020-11-18 | Nxp B.V. | Protecting an integrated circuit |
FR3055471B1 (fr) * | 2016-08-31 | 2018-09-14 | Stmicroelectronics (Crolles 2) Sas | Puce protegee contre les attaques face arriere |
US9818871B1 (en) | 2016-10-20 | 2017-11-14 | Cisco Technology, Inc. | Defense layer against semiconductor device thinning |
US9754901B1 (en) | 2016-11-21 | 2017-09-05 | Cisco Technology, Inc. | Bulk thinning detector |
JP7216645B2 (ja) * | 2016-12-05 | 2023-02-01 | クリプトグラフィ リサーチ, インコーポレイテッド | 裏面セキュリティ・シールド |
US10547461B2 (en) | 2017-03-07 | 2020-01-28 | Nxp B.V. | Method and apparatus for binding stacked die using a physically unclonable function |
US10249579B2 (en) | 2017-04-25 | 2019-04-02 | Nuvoton Technology Corporation | Active shield for protecting a device from backside attacks |
FR3069703B1 (fr) | 2017-07-27 | 2020-01-24 | Stmicroelectronics (Crolles 2) Sas | Puce electronique |
FR3082659A1 (fr) | 2018-06-14 | 2019-12-20 | Stmicroelectronics (Research & Development) Limited | Puce electronique protegee |
US10770410B2 (en) * | 2018-08-03 | 2020-09-08 | Arm Limited | Circuit alteration detection in integrated circuits |
US10839109B2 (en) * | 2018-11-14 | 2020-11-17 | Massachusetts Institute Of Technology | Integrated circuit (IC) portholes and related techniques |
US11456291B2 (en) * | 2020-06-24 | 2022-09-27 | Qualcomm Incorporated | Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods |
EP3937055A1 (en) * | 2020-07-10 | 2022-01-12 | Nagravision SA | Integrated circuit device with protection against malicious attacks |
US11775696B2 (en) * | 2021-10-21 | 2023-10-03 | Hart Intercivic, Inc. | Systems, tamper-evident assemblies and methods to detect tampering and/or provide cryptographic evidence of tampering |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0494913A4 (en) * | 1989-10-03 | 1993-01-20 | University Of Technology, Sydney | Electro-active cradle circuits for the detection of access or penetration |
JP3440763B2 (ja) * | 1996-10-25 | 2003-08-25 | 富士ゼロックス株式会社 | 暗号化装置、復号装置、機密データ処理装置、及び情報処理装置 |
EP1149358B1 (de) * | 1999-01-29 | 2003-10-29 | Infineon Technologies AG | Kontaktlose chipkarte |
CN1188911C (zh) * | 1999-05-03 | 2005-02-09 | 因芬尼昂技术股份公司 | 保护多维结构的芯片堆的方法和装置 |
US6421013B1 (en) * | 1999-10-04 | 2002-07-16 | Amerasia International Technology, Inc. | Tamper-resistant wireless article including an antenna |
US7005733B2 (en) * | 1999-12-30 | 2006-02-28 | Koemmerling Oliver | Anti tamper encapsulation for an integrated circuit |
JP2003108958A (ja) * | 2001-09-28 | 2003-04-11 | Konica Corp | Icカード及びicカードの製造方法 |
US20040066296A1 (en) * | 2001-11-15 | 2004-04-08 | Atherton Peter S. | Tamper indicating radio frequency identification label with tracking capability |
DE10238835A1 (de) * | 2002-08-23 | 2004-03-11 | Infineon Technologies Ag | Halbleiterchip, Chipanordnung mit zumindest zwei Halbleiterchips und Verfahren zur Überprüfung der Ausrichtung zumindest zweier übereinander liegender Halbleiterchips in einer Chipanordnung |
AU2004269715A1 (en) * | 2003-08-29 | 2005-03-10 | Peter S. Atherton | A radio frequency identification tag with tamper detection capability |
FR2864667B1 (fr) * | 2003-12-29 | 2006-02-24 | Commissariat Energie Atomique | Protection d'une puce de circuit integre contenant des donnees confidentielles |
-
2006
- 2006-12-11 EP EP06821637.3A patent/EP1977481B1/en active Active
- 2006-12-11 US US12/087,942 patent/US7966666B2/en active Active
- 2006-12-11 EP EP13163271.3A patent/EP2615641B1/en not_active Not-in-force
- 2006-12-11 WO PCT/IL2006/001421 patent/WO2007086046A2/en active Application Filing
- 2006-12-11 CN CN2010105269660A patent/CN102063584B/zh not_active Expired - Fee Related
-
2008
- 2008-07-20 IL IL192916A patent/IL192916A/en not_active IP Right Cessation
-
2009
- 2009-10-15 HK HK09109565.7A patent/HK1129772A1/xx not_active IP Right Cessation
-
2011
- 2011-10-24 HK HK11111411.5A patent/HK1157508A1/xx not_active IP Right Cessation
Cited By (8)
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CN105474390A (zh) * | 2013-07-02 | 2016-04-06 | 秦内蒂克有限公司 | 电子硬件组件 |
CN105474390B (zh) * | 2013-07-02 | 2019-04-19 | 秦内蒂克有限公司 | 电子硬件组件 |
CN107850995A (zh) * | 2015-01-09 | 2018-03-27 | 斯坦福国际研究院 | 不可克隆的rfid芯片和方法 |
CN106960842A (zh) * | 2015-12-29 | 2017-07-18 | 智能Ic卡公司 | 用于保护集成电路器件的系统和方法 |
CN106960842B (zh) * | 2015-12-29 | 2020-09-22 | 智能Ic卡公司 | 用于保护集成电路器件的系统和方法 |
CN109659279A (zh) * | 2017-10-11 | 2019-04-19 | 意法半导体(鲁塞)公司 | 用于检测集成电路中的差分故障分析攻击和对衬底的减薄的方法以及相关集成电路 |
CN109659279B (zh) * | 2017-10-11 | 2023-09-08 | 意法半导体(鲁塞)公司 | 用于检测集成电路中的差分故障分析攻击和对衬底的减薄的方法以及相关集成电路 |
US11942440B2 (en) | 2017-10-11 | 2024-03-26 | Stmicroelectronics (Rousset) Sas | Method for detecting a differential fault analysis attack and a thinning of the substrate in an integrated circuit, and associated integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
IL192916A0 (en) | 2009-02-11 |
EP1977481A4 (en) | 2010-11-10 |
US7966666B2 (en) | 2011-06-21 |
EP2615641A2 (en) | 2013-07-17 |
US20090001821A1 (en) | 2009-01-01 |
EP2615641B1 (en) | 2015-07-01 |
HK1129772A1 (en) | 2009-12-04 |
WO2007086046A2 (en) | 2007-08-02 |
CN102063584B (zh) | 2012-12-05 |
IL192916A (en) | 2012-07-31 |
WO2007086046A3 (en) | 2009-04-16 |
EP2615641A3 (en) | 2014-06-04 |
EP1977481A2 (en) | 2008-10-08 |
HK1157508A1 (en) | 2012-06-29 |
EP1977481B1 (en) | 2013-08-21 |
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