JP4717011B2 - 機密データを含む集積回路チップの保護 - Google Patents
機密データを含む集積回路チップの保護 Download PDFInfo
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- JP4717011B2 JP4717011B2 JP2006546290A JP2006546290A JP4717011B2 JP 4717011 B2 JP4717011 B2 JP 4717011B2 JP 2006546290 A JP2006546290 A JP 2006546290A JP 2006546290 A JP2006546290 A JP 2006546290A JP 4717011 B2 JP4717011 B2 JP 4717011B2
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Description
という手段により、第一導電要素30の終端31及び37に接続されても良い。
10 基板
11 ビア
12,14,16 上部層
13,15,17 めっき板
20 基板
21 保護された回路
23 ワイヤボンド
26 めっき層
27 パッシベーション層
28,29 エポキシ層
30 第一導電要素
39 下位ジャンクション
40 第二導電要素
50 パッシベーション層
51,57 ビア
60 パッシベーション層
61,63,65,67,69 ビア
70 第一導電要素
80 パッシベーション層
100 基板
200 他の導電要素
300 集積回路
500 集積回路
A 前面
B 背面
FT1,FT2 トランジスタ回路
Claims (21)
- 安全に保護される必要がある情報データを含むまたは処理する集積回路チップ300であって、前記チップの第一面Aは前記集積回路に接続された少なくとも一つの第一導電要素30を有し、前記チップの他の面Bは他の導電要素200を有し、前記第一導電要素30と他の導電要素200とは誘導結合により結合されており、前記他の導電要素は前記第一導電要素と接触していない集積回路チップを有する電子装置。
- 前記チップの前記第一面Aは、前記第一導電要素に近接して配置された、及び/又は第一導電要素30に直列に接続された第二導電要素40をさらに有することを特徴とする請求項1に記載の装置。
- 前記第一導電要素30と前記第二導電要素40が、交互に混在した、巻きつくまたは相互に巻きつくパターンを有することを特徴とする請求項2に記載の装置。
- 前記第一導電要素は伝送電機子を有することを特徴とする請求項1から3のいずれか一項に記載の装置。
- 前記第一導電要素30、及び/又は前記第二導電要素40はインダクタンスを有することを特徴とする請求項1から4のいずれか一項に記載の装置。
- 前記他の導電要素200が接地板の導電率を有することを特徴とする請求項1から5のいずれか一項に記載の装置。
- 前記第一導電要素の電磁励起手段を有することを特徴とする請求項1から6のいずれか一項に記載の装置。
- 前記集積電子回路が、前記導電要素の少なくとも一つのインダクタンスを測定し、及び/又はインダクタンスの変化を探知する手段を有することを特徴とする請求項1から7のいずれか一項に記載の装置。
- 前記インダクタンス値の変化が探知されると、前記情報データを削除または記憶することを停止する手段を有することを特徴とする請求項8に記載の装置。
- 前記第一導電要素30、及び/又は前記第二導電要素40は、前記チップ100,500内部の集積電子回路Tに接続されている一方、前記他の導電要素200は前記集積電子回路Tに接続されていないことを特徴とする請求項1から9のいずれか一項に記載の装置。
- 前記チップ500は、前記第一導電要素30が前記集積電子回路T,100、及び/又は前記第二導電要素40に接続することを許容する少なくとも一つの金属または導電レベル52−62,58−68を含む上部コーティング層50,60,80を有することを特徴とする請求項1から10のいずれか一項に記載の装置。
- 前記第一導電要素30、及び/又は前記第二導電要素40は回路ループを形成することを特徴とする請求項1から11のいずれか一項に記載の装置。
- 前記他の導電要素200は接地または等電位面を形成することを特徴とする請求項1から12のいずれか一項に記載の装置。
- 前記第一導電要素30、及び/又は前記第二導電要素40は、少なくとも直線的な金属トラック32/42を有することを特徴とする請求項1から13のいずれか一項に記載の装置。
- 前記第一導電要素30、及び/又は前記第二導電要素40は、同心状に配置され、波形または多角形の螺旋を形成するようにまたは円形の螺旋を形成するように複数の相互接続された部分(32,33,34/42,43,44)を有することを特徴とする請求項1から14のいずれか一項に記載の装置。
- 前記第一及び/又は前記第二導電要素70は平行に配置され、少なくとも一つの曲折またはコイルを形成するような複数の相互接続された部分71,72,73,74を有することを特徴とする請求項1から15のいずれか一項に記載の装置。
- 前記その他の要素200は、平面またはめっき表面部分または導電性メッシュのネットワーク、特に円、四角形、六角形のメッシュのネットワーク、または格子を有することを特徴とする請求項1から16のいずれか一項に記載の装置。
- 前記導電要素30,40,70,200の各々は、前記チップの前記側面A,Bに平行な平板に位置していることを特徴とする請求項1から17のいずれか一項に記載の装置。
- 前記チップの前記導電要素30,40,70,200が封入材料で覆われていることを特徴とする請求項1から18のいずれか一項に記載の装置。
- 請求項1から19に記載の電子装置を少なくとも一つは有することを特徴とするチップカード。
- 請求項1から19に記載の電子装置を一つ以上有することを特徴とする暗号化またはデコード装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0351221A FR2864667B1 (fr) | 2003-12-29 | 2003-12-29 | Protection d'une puce de circuit integre contenant des donnees confidentielles |
FR0351221 | 2003-12-29 | ||
PCT/FR2004/050756 WO2005069210A1 (fr) | 2003-12-29 | 2004-12-23 | Protection d'une puce de circuit integre contenant des donnees confidentielles |
Publications (2)
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JP2007535022A JP2007535022A (ja) | 2007-11-29 |
JP4717011B2 true JP4717011B2 (ja) | 2011-07-06 |
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JP2006546290A Expired - Fee Related JP4717011B2 (ja) | 2003-12-29 | 2004-12-23 | 機密データを含む集積回路チップの保護 |
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US (1) | US8110894B2 (ja) |
EP (1) | EP1700256B1 (ja) |
JP (1) | JP4717011B2 (ja) |
AT (1) | ATE370464T1 (ja) |
DE (1) | DE602004008339T2 (ja) |
FR (1) | FR2864667B1 (ja) |
WO (1) | WO2005069210A1 (ja) |
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- 2004-12-23 AT AT04816603T patent/ATE370464T1/de not_active IP Right Cessation
- 2004-12-23 US US10/583,377 patent/US8110894B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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EP1700256A1 (fr) | 2006-09-13 |
WO2005069210A1 (fr) | 2005-07-28 |
FR2864667A1 (fr) | 2005-07-01 |
FR2864667B1 (fr) | 2006-02-24 |
EP1700256B1 (fr) | 2007-08-15 |
US20070121575A1 (en) | 2007-05-31 |
DE602004008339D1 (de) | 2007-09-27 |
JP2007535022A (ja) | 2007-11-29 |
DE602004008339T2 (de) | 2008-05-08 |
ATE370464T1 (de) | 2007-09-15 |
US8110894B2 (en) | 2012-02-07 |
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