US6835612B2 - Method for fabricating a MOSFET having a very small channel length - Google Patents

Method for fabricating a MOSFET having a very small channel length Download PDF

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US6835612B2
US6835612B2 US10/673,705 US67370503A US6835612B2 US 6835612 B2 US6835612 B2 US 6835612B2 US 67370503 A US67370503 A US 67370503A US 6835612 B2 US6835612 B2 US 6835612B2
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gate layer
gate
layer
width
channel length
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US20040157380A1 (en
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Annalisa Cappellani
Ludwig Dittmar
Dirk Schumann
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Polaris Innovations Ltd
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Infineon Technologies AG
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    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652Through-implantation
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • HELECTRICITY
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

Definitions

  • the present invention relates to a method for fabricating a MOSFET having a gate channel of a predetermined, very small channel length.
  • a high performance of the transistor presupposes, for example, a high operating current with a low power consumption and also only a low leakage current in the off state.
  • the gate resistance and parasitic effects such as the Miller capacitance are intended to be as small as possible.
  • T-gate transistors Various methods have been proposed for fabricating T-gate transistors. Thus, e.g. the fabrication of a T-gate in which a metal layer is subsequently deposited onto a preformed polysilicon gate is known. On account of positional errors between the layers, however, it is necessary to increase the distance between the source/drain contacts and the gate in order to ensure entirely satisfactory operation of the transistor even in the event of a misalignment. However, this entails an increased source/drain resistance.
  • a short-channel transistor is described e.g. by Ghani, Ahmed et al., IEDM 99, page 415. Furthermore, D. Hisamoto et al. (IEEE Transaction on Electronic Devices, Vol 44, 6, 97, page 951) describe a method for fabricating a self-aligned T-gate with a tungsten layer on an underlying first gate layer.
  • Kasai et al. (IEDM 94, pages 497-98) describe a method for fabricating a T-gate in which the gate layer stack comprises polysilicon, a diffusion barrier and a metal layer deposited one above the other.
  • the short-channel gate has to be structured with the aid of complicated lithographic methods, for instance with the aid of an electron beam.
  • a method for fabricating a MOSFET with a gate channel of a predetermined, very small channel length comprises the following steps:
  • the first gate layer comprising polysilicon
  • an intermediate layer preferably of tungsten nitride, to serve as a diffusion barrier, on the first gate layer
  • the second gate layer comprising tungsten
  • various etching steps having different degrees of isotropy are combined with one another in a suitable manner in order to obtain the desired T-shaped structure of the gate.
  • the gate layer stack is etched anisotropically, thereby patterning it.
  • the gate thus formed is still significantly wider than the predetermined channel length.
  • the second gate layer is masked in such a way that its width is greater than the predetermined channel length; i.e. the masking is effected in such a way that after the hereinafter first etching step, a layer stack is produced which comprises the first and second gate layers and has a width which is greater than the predetermined channel length.
  • the further processing of the gate layer stack in order to achieve the small gate length corresponding to the predetermined channel length is then effected by subsequent etching of the lower gate layer from the side.
  • a second etching step is carried out.
  • the second etching is carried out isotropically.
  • the second etching brings about a lateral constriction of the first gate layer, which is narrowed in a controlled manner down to the predetermined channel length.
  • the short-channel gate thus obtained is produced with the aid of simple process steps known per se, without complicated methods being employed.
  • a preferred embodiment provides for the width of the first gate layer to be controlled by the width of the second gate layer and by the duration of the controlled lateral undercutting of the first gate layer under the second gate layer.
  • the concentration of etchants and other parameters of the undercutting remain constant, so that only the time duration of this etching determines the lower gate length.
  • the predetermined width of the first gate layer is preferably equal to the predetermined channel length.
  • One development of the invention provides for the width of the first gate layer to be controlled during the undercutting with the aid of the concentration of an etchant.
  • the concentration can be set to a value which is constant during the etching, or else be altered in the course of the etching.
  • the predetermined width of the first gate layer is preferably equal to the predetermined channel length.
  • deviations of 10% in both directions also still lie within the scope of the invention.
  • the anisotropic etching of the second and of the first gate layer is continued until the dielectric is reached.
  • the sidewall produced during the isotropic etching becomes particularly uniform as a result.
  • the first, isotropic etching can also be ended within the lower gate layer and the second, isotropic etching can be begun there. In this case, the dielectric is not reached until during the second etching.
  • the first gate layer is isotropically laterally undercut selectively with respect to the second gate layer.
  • the upper dimensions of the gate line are preserved and can thus be contact-connected more easily.
  • the undercutting is preferably carried out with the aid of an isotropic plasma etching step.
  • an isotropic plasma etching step In this case, conventional dry etching chambers with inductive or other coupling-in are implied.
  • a hydrogen halide preferably serves as etching gas for the isotropic etching; hydrogen bromide, in particular, is advantageous owing to its good selectivity with respect to metals.
  • the width of the second gate layer to be between 120 and 300 nm and for the width of the first gate layer to between 30 and 150 nm.
  • Transistors having a channel length of 30 to 150 nm are thus preferably fabricated.
  • the gate dielectric preferably contains silicon dioxide.
  • the second gate layer preferably has a higher electrical conductivity than the first gate layer. As a result, the overall conductivity of the gate is increased.
  • the second gate layer preferably comprises tungsten as metal. It can be composed of tungsten.
  • One development of the invention provides for the introduction of source/drain implantations and the diffusion thereof under the predetermined width of the second gate layer as far as the edge of the first gate layer.
  • the wider, upper gate layer forms part of a mask which allows the implantations to be introduced into the wafer only at a certain distance from the lower gate layer through the dielectric.
  • the subsequent thermal distribution of the implantations is controlled in such a way that the dopants likewise cover, in addition to the width of a spacer, the difference between the widths of the second and first gate layers, i.e. the path to the predetermined small channel length.
  • the MOSFET according to the invention forms a part of a DRAM or of a logic circuit.
  • FIG. 1 is a diagrammatic side view illustrating a first process stage in the fabrication of T-gate transistors according to the invention
  • FIG. 2 illustrates a second process stage
  • FIG. 3 illustrates a third process stage.
  • FIG. 1 there is shown a sequence of a plurality of gate layers that are deposited on a silicon substrate 1 covered with a gate oxide 2 made, preferably, of silicon dioxide.
  • the gate layer stack thus produced substantially comprises a first gate layer 3 made of polysilicon and an overlying second gate layer 5 .
  • the second gate layer 5 serves for improving the conductivity of the gate in the case of very small dimensions and will therefore preferably be composed of a metal, in particular of tungsten.
  • the layer sequence required for the gate structure is patterned laterally in order to form the gate.
  • the layer sequence or its uppermost layer 5 is firstly masked. Since this masking is effected in such a way that the width of the second gate layer 5 is wider than the predetermined channel length at this method stage, it is possible to employ conventional lithographic techniques such as, for instance, the use of resist or hard masks.
  • the initial width of the gate layer stack is deliberately chosen to be wider than would correspond to the desired gate length and thus the channel length.
  • combining an anisotropic first etching with a subsequent anisotropic undercutting, which, in this order, leads to an undercutting of the first gate layer under the second gate layer results in a reduction of the gate length directly on the gate oxide.
  • a T-gate with a very short channel length can be fabricated with the aid of simple etching processes known per se.
  • the use of lasers or electron beams which are usually employed to produce very small structures is not necessary in the case of the method according to the invention. Rather, the second gate layer 5 can be masked in a customary manner with the aid of resist masks or hard masks.
  • the forming of the gate then begins with the anisotropic dry etching—directed in the direction perpendicular to the substrate surface—with the aid of a first etching gas, indicated by A 1 in FIG. 1 .
  • the etching is preferably continued until all of the gate layers have been patterned, but the underlying dielectric has still not been perforated.
  • the etching can also be ended at a stage in which the second gate layer 5 has been completely perforated, whereas the first gate layer 3 has only been partially perforated.
  • the first gate layer 3 is completely perforated as far as the dielectric 2 through the second etching step, described below.
  • a second etching gas A 2 is supplied isotropically to the substrate.
  • the term “isotropic” in this sense means that the degree of isotropy is high enough that the etching gas A 2 reaches and undercuts the sidewalls of the lower gate layer 3 .
  • the second etching must be effected selectively with respect to the dielectric 2 .
  • the dielectric need not necessarily be reached as early as in the course of the first etching; if the initial width of the gate structure, i.e. the width of the upper gate layer 5 , is large enough, it is also conceivable that, after the lower gate layer 3 has been reached, only the second etching uncovers the dielectric.
  • the etching gas A 2 can preferably be selected in such a way that the second etching is also effected selectively with respect to the second gate layer 5 lying above the first gate layer 3 (and, if appropriate, with respect to the intermediate layer lying between them).
  • T-shaped gate structures are produced whose readily conductive metallic upper part maintains its wider cross section formed after the first etching, while only the lower first gate layer 3 is narrowed.
  • the upper gate layer 5 can be contact-connected more easily.
  • the second etching is not selective with respect to the upper gate layer, although know T-shaped gate structures are produced, the same reduction of the initial gate length is nonetheless achieved in this case as well. Moreover, if the second gate layer 5 is deposited with a sufficient thickness, enough material of said layer also remains after the second etching in order to ensure a sufficient electrical conductivity of the gate and in order to reliably make contact with the gate.
  • a hydrogen halide preferably serves as etching gas A 2 for the second etching, carried out isotropically.
  • Hydrogen bromide (HBr) in particular, is highly suitable owing to its good selectivity with respect to silicon dioxide (as dielectric) and with respect to metals (as second gate layer).
  • FIGS. 1 and 2 gate layer stacks of adjacent capacitors are shown closely adjacent in exaggerated proportion in order to better illustrate the influence of different degrees of isotropy on the shaping by the etching gas A 2 .
  • FIG. 3 shows only a single fabricated T-shaped layer stack 3 , 4 , 5 , which is already covered laterally with spacers 7 .
  • the spacers serve for laterally insulating the gate channel with respect to the source/drain implantations S/D to be introduced.
  • the implantations S/D are implanted outside the spacers 7 through the dielectric 2 into regions 8 of the substrate.
  • the temperature and the duration of the action of heat are controlled in such a way that the ion profile 6 extends right under the upper gate layer 5 up to the lower gate layer 3 , i.e. into the region 6 a .
  • an additional ion diffusion—corresponding to the undercutting—of 50 nm on each side of the gate suffices to form a transistor with a channel length of 100 nm.
  • the source/drain implantations are brought to one another to preferably 30 to 150 nm (corresponding to the desired channel length). According to the invention, however, it is possible to fabricate MOSFETs with any desired, even shorter channel length.
  • Such a transistor can be produced with the aid of conventional lithography methods by the method according to the invention.
  • the present invention makes it possible to fabricate self-aligned multilayer gates in which exclusively conventional fabrication installations and process steps are employed.
  • the method is therefore simple and cost-effective, and the gate length of the transistors fabricated is particularly dimensionally accurate on account of the controlled undercutting.

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US10/673,705 2001-03-26 2003-09-26 Method for fabricating a MOSFET having a very small channel length Expired - Fee Related US6835612B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10114778A DE10114778A1 (de) 2001-03-26 2001-03-26 Verfahren zur Herstellung eines MOSFETs mit sehr kleiner Kanallänge
DE10114778.3 2001-03-26
DE10114778 2001-03-26
PCT/DE2002/000732 WO2002078058A2 (fr) 2001-03-26 2002-02-28 Procede pour la production d'un transistor mosfet a longueur de canal tres faible

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US6835612B2 true US6835612B2 (en) 2004-12-28

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EP (1) EP1374293B1 (fr)
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040097092A1 (en) * 2002-11-20 2004-05-20 Applied Materials, Inc. Method of plasma etching high-K dielectric materials with high selectivity to underlying layers
KR20150051720A (ko) * 2013-11-05 2015-05-13 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US20190103325A1 (en) * 2017-09-29 2019-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Footing Removal in Cut-Metal Process
US10879367B2 (en) * 2017-04-19 2020-12-29 Mitsubishi Electric Corporation Method for manufacturing semiconductor device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6656824B1 (en) * 2002-11-08 2003-12-02 International Business Machines Corporation Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch
JP2007157739A (ja) * 2005-11-30 2007-06-21 Fujitsu Ltd Cmos半導体素子とその製造方法
JP5579362B2 (ja) * 2007-10-19 2014-08-27 ピーエスフォー ルクスコ エスエイアールエル 縦型相変化メモリ装置の製造方法
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