US6115279A - System with meshed power and signal buses on cell array - Google Patents

System with meshed power and signal buses on cell array Download PDF

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Publication number
US6115279A
US6115279A US08/728,447 US72844796A US6115279A US 6115279 A US6115279 A US 6115279A US 72844796 A US72844796 A US 72844796A US 6115279 A US6115279 A US 6115279A
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Prior art keywords
voltage supply
lines
conductive layer
memory device
semiconductor memory
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US08/728,447
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English (en)
Inventor
Goro Kitsukawa
Takesada Akiba
Hiroshi Otori
William R. McKee
Jeffrey E. Koelling
Troy H. Herndon
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Hitachi Ltd
Texas Instruments Inc
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Hitachi Ltd
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Assigned to HITACHI LTD. reassignment HITACHI LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AKIBA, TAKESADA, KITSUKAWA, GORO, OTORI, HIROSHI
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HERNDON, TROY H., KOELLING, JEFFREY E., MCKEE, WILLIAM R.
Priority to US08/991,727 priority patent/US5953242A/en
Priority to US09/330,579 priority patent/US6069813A/en
Priority to US09/496,079 priority patent/US6288925B1/en
Publication of US6115279A publication Critical patent/US6115279A/en
Application granted granted Critical
Priority to US09/909,191 priority patent/US6396088B2/en
Priority to US10/120,872 priority patent/US6512257B2/en
Priority to US10/315,307 priority patent/US6831317B2/en
Priority to US10/728,682 priority patent/US6815742B2/en
Priority to US10/945,351 priority patent/US6967371B2/en
Priority to US11/158,379 priority patent/US7211842B2/en
Priority to US11/683,930 priority patent/US7323727B2/en
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Definitions

  • the invention relates generally to semiconductor circuit design and, more particularly, to a method and apparatus for interconnecting power and signal buses in an integrated circuit.
  • a meshed power bus system for the chip, as described in Yamada, A 64-Mb DRAM with Meshed Power Line, 26 IEEE Journal of Solid-State Circuits 11 (1991).
  • a meshed power bus system is readily implemented in integrated circuits like DRAMs because of their large arrays of memory cells and the presence of distributed sense amplifier drivers.
  • the meshed system supplies adequate power to the distributed sense amplifier drivers because the system has many power buses running in both horizontal and vertical directions across the arrays.
  • the Yamada meshed system may be implemented using a conventional complimentary metal oxide semiconductor (CMOS) technology, including first, second and third metal layers, each electrically isolated from each other, wherein the first metal layer represents the lowest metal layer, the third metal layer represents the upper-most metal layer, and the second metal layer lies between the first and third layers.
  • CMOS complimentary metal oxide semiconductor
  • the Yamada meshed system is constructed in the second and third metal layer and includes a positive supply voltage (VDD) mesh and a negative supply voltage (VSS) mesh, for the VDD power buses and the VSS power buses, respectively.
  • VDD positive supply voltage
  • VSS negative supply voltage
  • Conventional designs have these meshes running over the memory array and connecting at the sense amplifiers. Connections are made using through-holes, located in the area of the sense amplifier circuits. However, the presence of VDD and VSS power buses in the sense amplifiers is unnecessary, since these circuits do not require either VDD or VSS power buses, except for well bias.
  • the sense amplifiers due to their relatively small size and numerous associated signal and power buses, are adversely affected by the Yamada meshed system.
  • the Yamada meshed system overcrowds the sense amplifiers with additional power and signal buses.
  • the metal line width required for overlapping through-holes is larger than the minimum metal line width and therefore increases the width of the metal layers even further.
  • the metal layer over the sense amplifiers becomes determinative of the size of the sense amplifier circuits. Accordingly, their size reduction must be realized by tightening the metal width, inevitably resulting in increased resistance and slower operation.
  • the Noda scheme includes main word lines, constructed in the second metal line layer, and subword lines constructed in a poly silicon layer.
  • the Noda scheme describes two main word lines (one true, one bar) for every eight subword lines, and is thereby able to relax the main word line pitch to four times that of the subword line. However, this pitch would not support an improved meshed power and signal bus system.
  • the present invention accordingly, is a method and apparatus for providing a meshed power bus and signal bus system on an array-type integrated circuit that does not limit mesh through-hole connections to the area of the sense amplifiers, but provides for these connections at other locations on the array, thereby allowing for a relaxed metal width over the sense amplifiers, faster sense amplifier operation, and chip size reduction.
  • the through-holes for the mesh system are located in the cell array instead of, or in addition to, being located in the area of the sense amplifier circuits. This utilizes the available space for through-holes in the array, and allows for more efficient use of power and signal buses in the sense amplifiers.
  • the invention includes an array of DRAM memory cells, arranged as a plurality of subarrays and selected by main address decoders. Each subarray is surrounded by a plurality of sense amplifiers circuits, subdecoder circuits, and VDD, VSS and signal buses connecting to and running across the subarray.
  • the VDD buses run in both vertical and horizontal directions across the subarray, with all the vertical buses lying in the third metal layer and all the horizontal buses lying in the second metal layer, thereby creating a VDD mesh.
  • the buses in each layer are connected to each other using through-holes located in the memory cell subarray as well as on the sense amplifier area. Likewise, a VSS mesh and/or a signal mesh is created using through-holes located on the memory cell subarray. Once connected, the buses extend to the appropriate circuits, such as sense amplifier drive circuits, and the metal layer and through-hole requirement over the sense amplifiers is significantly reduced.
  • the invention also includes a hierarchical word line scheme.
  • the Noda hierarchical word line scheme should also be improved to provide a greater pitch of main word lines to subword lines.
  • an intersection area created between the sense amplifier and the subdecoder, includes subdecoder drivers as well as sense amplifier drivers. This combination provides high speed word line selection and high speed sense amplifier operation at the same time.
  • an improved layout technique for the sense amplifier circuits may be necessary to match the fine memory cell size.
  • This improved layout technique includes an alternating T-shaped gate region for a bit line equalization circuit and an H-shaped moat region with a metal-to-polysilicon-to-metal change structure for a latch circuit.
  • a technical advantage achieved with the invention is the ability to fully utilize the low resistance design of a meshed power system without having to increase the size of the peripheral circuits, for example, sense amplifiers, that are limited in size by their metal layers.
  • a further technical advantage achieved with the invention is that both signal and power buses may freely run in both horizontal and vertical directions.
  • a further technical advantage achieved with the invention is that the improved hierarchical word line structures are smaller and faster than conventional hierarchical word line structures.
  • FIG. 2 is a block diagram of two subarrays and surrounding sense amplifiers and subdecoders of the DRAM of FIG. 1.
  • FIG. 3 is a block diagram of one subarray, two sense amplifiers, and a subdecoder, as shown in FIG. 2, and a meshed power and signal system running across the subarray.
  • FIG. 4 is a schematic diagram of a meshed power and signal system over the subarray of FIG. 3.
  • FIG. 5a is a cross sectional view of a memory cell of the subarray of FIG. 3 with a through-hole connecting two metal layers used in the meshed power system of FIG. 4.
  • FIG. 5b is a detailed schematic of a memory cell of the subarray of FIG. 3.
  • FIGS. 6a-6c are layout diagrams of expanded sections of the meshed system of FIG. 4.
  • FIGS. 7a-b are schematic diagrams of circuits included in the intersection area, sense amplifier, subdecoder and memory array of FIG. 3.
  • FIG. 8 is a diagram of the subdecoder circuits of FIGS. 7.
  • FIG. 9a is a schematic diagram of a prior art subdecoder circuit showing the Noda hierarchical word line implementation.
  • FIG. 9b is a schematic diagram of one subdecoder circuit showing a hierarchical word line implementation.
  • FIG. 9c is a schematic diagram of a preferred subdecoder circuit showing a hierarchical word line implementation of the present invention.
  • FIG. 10a is a schematic diagram of the two sense amplifier circuits of FIG. 7a.
  • FIG. 10b is a layout diagram of the sense amplifier circuits of FIG. 10a.
  • FIG. 11a is a layout diagram of a circuit used in an equalizer section of a conventional sense amplifier.
  • FIG. 11b is a layout diagram of a circuit used in the equalizer section of the sense amplifier circuit of FIG. 7a, utilizing an alternate T-shaped gate region of the present invention.
  • FIG. 12a is a layout diagram of a circuit used in the latch section of the sense amplifier circuit of FIG. 7a, utilizing the H-shaped moat region of FIG. 10b.
  • FIG. 12b is a simplified diagram of the H-shaped moat region of FIG. 12a.
  • FIG. 13a is a metal layout diagram of a section of a conventional sense amplifier.
  • FIGS. 13b-c are metal layout diagrams of an improved section of the sense amplifier of FIG. 7a, implementing a noise decreasing method of the present invention.
  • FIG. 14a is a first cross sectional view of a sense amplifier using a triple well structure.
  • FIG. 14b is a second cross sectional view of the sense amplifier of FIG. 2, using a triple well structure.
  • FIG. 14c is a cross sectional view of the subdecoder of FIG. 2 using a triple well structure.
  • FIG. 15a is a block diagram showing four fuses used for the sense amplifiers of FIG. 2 and two additional sense amplifiers.
  • FIG. 15b is a schematic diagram showing four fuses used for the sense amplifiers of FIG. 2 and two additional sense amplifiers.
  • the reference numeral 10 refers to a memory device embodying features of the present invention.
  • the device 10 is fabricated using a conventional CMOS technology, including first, second and third metal layers and a polysilicon layer.
  • the device 10 also utilizes metal oxide semiconductor field effect transistors (MOSFETs), but other types of transistors may also be used, such as bipolar, and metal insulator semiconductors.
  • MOSFETs metal oxide semiconductor field effect transistors
  • the device 10 is a 256 Mbit dynamic random access memory (DRAM), it should be understood that the present invention is not limited to use with a 256 Mbit DRAM, but may be used in conjunction with other devices having arrays, including a programmable array logic, a 1 Gbit DRAM and other memory devices.
  • DRAM dynamic random access memory
  • the device 10 includes a set of array blocks of memory cells, such as an array block 12, a group of pads 14a-14f, and a group of main address decoders 16a-16l, wherein decoders 16b, 16e, 16h and 16k are row decoders and decoders 16a, 16c, 16d, 16f, 16g, 16i, 16j and 16l are column decoders.
  • the array block 12 is selected by signals from the address pads 14a-14d. It should be understood that while more address and signal pads exist, they may be represented by address pads 14a-14d, which are decoded by main address decoders 16a-16l.
  • the main address decoders 16a-16l represent a plurality of row and column decoders.
  • the row decoders generate signals including main-word signals MWB and subdecoder control signals DXB, and the column decoders generate signals such as column select signals YS. These signals are controlled by different address signals from the address pads 14a-14d, as discussed in greater detail below.
  • Array block 12 which is representative of the 16 Mbit array blocks, is further divided into 256 subarrays, two of which are shown in FIG. 2, and are respectively designated by reference numerals 18a and 18b.
  • Each subarray consists of 128K of memory cells (arranged as 512 rows by 256 columns).
  • Power is supplied to the device 10 through power pads 14e and 14f.
  • the pad 14e is the positive supply voltage (VDD) power pad and is connected to an external power supply (not shown).
  • the pad 14f is the negative supply voltage (VSS) power pad and is connected to an external ground (also not shown).
  • the memory cells of the subarray 18a are selected by signals from two groups of address subdecoders 20a and 20b.
  • the memory cells of the subarray 18b are selected by signals from two groups of address subdecoders 20c and 20d.
  • the memory cells of subarray 18a are read by two groups of sense amplifiers 22a and 22b.
  • the memory cells of subarray 18b are read by two groups of sense amplifiers 22b and 22c.
  • the sense amplifiers 22a-22c intersect with the subdecoders 20a-20d, at intersection areas 24a-24f. In this way, intersection areas 24a-24f are created by the extension of sense amplifier areas 22a-22c and subdecoder areas 20a-20d.
  • the pads 14e and 14f act as electrical ports to supply power to the entire device 10 through main VDD and VSS power buses 28 and 26, respectively.
  • the main VDD and VSS power buses 28 and 26 supply power to the device 10 through a plurality of buses, located in different metal layers.
  • the metal layers are layered onto a silicon substrate, in the order of: a first metal layer (M1), a second metal layer (M2), and a third metal layer (M3).
  • M1 first metal layer
  • M2 second metal layer
  • M3 third metal layer
  • Each of the metal layers M1, M2, M3 is electrically isolated from each other, but may be electrically interconnected at intersection points using through-holes.
  • Each metal layer M1, M2, M3 also has associated therewith a thickness such that the thickness for M3 is greater than the thickness for M2, which is greater than the thickness for M1.
  • a first VDD bus 30, comprising a conductor constructed in the third metal layer M3, extends in a vertical path across the subarray 18a.
  • a first VSS bus 32 also a conductor constructed in M3, extends in a vertical path across the memory subarray 18a, parallel with the bus 30.
  • a first signal bus 34 and a first column select YS bus 35 conductors constructed in M3, run vertically across the subarray 18a parallel with power buses 30 and 32.
  • a first subdecoder DXB bus 36 also a conductor constructed in M3, runs vertically across address subdecoder 20a, outside of the subarray 18a.
  • a second VDD bus 37a, a second VSS bus 37b and a second signal bus 37c, conductors constructed in M3, run vertically across the subdecoder 20a and the intersection areas 24a and 24b.
  • the second VDD bus 37a and the second VSS bus 37b have a width that is less than a width of the first VDD bus 30 and the first VSS bus 32, respectively.
  • a third VDD bus 38 and a third VSS bus 40, along with a third signal bus 42 and a second DXB bus 44, are also conductors similar to those described above, except that they are constructed in the second metal layer M2, and extend in parallel, horizontal paths across the memory subarray 18a.
  • the third VDD bus 38 electrically connects with the second VDD bus 37a within the subdecoder 20a at their intersection point 45 over the peripheral circuit area 20a and the first VDD bus 30 at their intersection point 46 within the memory subarray 18a.
  • the third VSS bus 40 electrically connects with the second VSS bus 37b at their intersection point 47 within the subdecoder 20a and the first VSS bus 32 at their intersection point 48 within the memory subarray 18a.
  • the third signal bus 42 electrically connects with the second signal bus 37c at their intersection point 49 within the subdecoder 20a and the first signal bus 34 at their intersection point 50 within the memory subarray 18a.
  • the second DXB bus 44 electrically connects with the first DXB bus 36 at their intersection point 52 in the subdecoder circuit 20a.
  • Each of the intersection points is achieved using through-holes, as discussed in greater detail with reference to FIGS. 5a-6c.
  • each bus Associated with each bus is a line width, it being understood that a bus with a larger surface area (width and thickness) provides a lower resistance current path.
  • the first VDD and VSS bus 30, 32 have a line width of 1.8 microns.
  • the second VDD and VSS bus 37a, 37b have a line width of 0.7 microns.
  • the third VDD and VSS bus 38, 40 have a line width of 1.8 microns.
  • the through-holes have associated therewith a diameter, it being understood that a through-hole with a larger surface area (diameter) provides a lower resistance current path.
  • the through-holes located above the memory subarray 18a have a diameter of 0.6 microns, while the through-holes located above the subdecoder circuit 20a have a diameter of 0.8 microns.
  • VDD and VSS power is supplied through the external pads 14e and 14f the main power buses 28 and 26, respectively, as previously described in FIG. 3.
  • the first VDD bus 30 is electrically connected to the main VDD power bus 28 thereby supplying VDD power to the first VDD bus, the second VDD bus 37a, and the third VDD bus 38.
  • the first VSS bus 32 is electrically connected to the main VSS power bus 26 thereby supplying VSS power to the first VSS bus, the second VSS bus 37b, and the third VSS bus 40.
  • a VDD mesh 54 is created by the VDD buses 30, 37a and 38 and a VSS mesh 56 is created by the VSS buses 32, 37b and 40.
  • each of the foregoing meshes have power buses running both vertically and horizontally across the subarray 18a, the subdecoder 20a and the intersection areas 24a-24b.
  • the VDD and VSS meshes 54 and 56 significantly reduce the total power bus resistance from the power pads 14e and 14f to the subdecoder 20a, the intersection areas 24a-24b and other circuits, even when the widths of the VDD and VSS buses 37a and 37b are narrow.
  • a first peripheral circuit drives electrical signals to the first signal bus 34 and the column decoder 16a (FIG. 1) drives electrical signals to the YS bus 35, which is used in sense amplifiers 22a and 22b.
  • main address decoder 16b drives electrical signals to the second DXB bus 44, in a conventional manner.
  • the first signal bus 34 electrically connects with the second signal bus 37c and the third signal bus 42 thereby creating a signal mesh 58 across the subarray 18a and the subdecoder 20a.
  • the first DXB bus 36 electrically connects with the second DXB bus 44 thereby creating a subdecoder mesh 60 across the subdecoder 20a.
  • the signal and subdecoder meshes 58 and 60 are able to connect the sense amplifiers 22a-22b, the subdecoder 20a, and the intersection areas 24a-24b in many different combinations.
  • the VDD, VSS, signal and subdecoder meshes 54, 56, 58 and 60 actually represent many vertical and horizontal lines for each mesh, thereby providing more buses for the surrounding circuits, and decreasing the resistance of each mesh.
  • the subarray 18a has multiple VDD buses 38a-38d running in M2 and multiple VDD buses 30a-30d running in M3, all tied to the main VDD bus 28 (FIG. 3), thereby decreasing the overall resistance of the VDD mesh 54.
  • the subarray 18a has multiple VSS buses 40a-40d running in M2 and multiple VSS buses 32a-32d running in M3, all tied to the main VSS bus 26 (FIG. 3), thereby decreasing the overall resistance of the VSS mesh 56.
  • buses run across the subarray 18a.
  • These other buses include multiple column factor (CF) buses 61a-61d running vertically in M3, for inputs to the column decoders 16a, 16c, 16d, 16f, 16g, 16i, 16j and 16l (FIG. 2), and multiple subdecoder buses (DXB1, DXB3, DXB5, DXB7) 44a-44d running horizontally in M2, for connection to the subdecoder circuits 20a and 20b (FIG. 2) and to the first DXB bus 36.
  • CF column factor
  • power buses 30a-30d, 32a-32d, 38a-38d, 40a-40d are located near an outer edge of the subarray 18a than the signal buses 61a-61d, 44a-44d.
  • resistance of the power buses is reduced, while the resistance for the signal buses, all grouped toward the interior edge of the subarray 18a, are relatively consistent with each other, thereby making signal propagation through the signal buses relatively consistent.
  • intersection point 48a denotes where the VSS bus 32b crosses the VSS bus 40b.
  • An electrical connection is made between the VSS bus 32b and the VSS bus 40b using a through-hole 62, located above a memory cell circuit 64.
  • the memory cell circuit 64 of the subarray 18a comprises a conventional, one capacitor and one transistor type DRAM cell.
  • a capacitor 65 is formed between a plate 67 and a storage node 68.
  • a transistor 69 is formed with the source and drain connected to the storage node 68 and a bit line (BL1) bus 70, respectively, and the gate connected to a first subword line (SW) bus 72a, having a width 74.
  • the cell structure of the preferred embodiment is a capacitor on bit line (COB) structure. This structure facilitates the sensitive nature of the BL1 bus 70 and enables operation without any detrimental effect by noise from the power and signal meshes 54, 56 and 58 located over the cell, due to the shielding affect of the plate 64.
  • COB capacitor on bit line
  • intersection point 48a appears to be located directly over the memory cell circuit 64, this is not required, and is only for the benefit of explanation. Furthermore, the through-hole 62 and VSS buses 32b and 40b are not necessary for memory cell 64 and not all of the power and signal buses will be connected to other buses.
  • the signal buses YS 35a-35d, CF 61a, MWB 86 and DXB1 44a run directly to their corresponding circuits, and therefore do not require a through-hole on the subarray 18a to change directions. Only the VSS buses 32b and 40b have a through-hole 62 to electrically connect them. With this arrangement, the width of each bus, 80, 82, 84, 88, 90 and 92, is optimized for speed and power resistance effect.
  • the sense amplifier 22a includes 128 sense amplifier circuits, such as sense amplifier circuits 98a and 98b. Both of the sense amplifier circuits 98a-98b are connected to a sense amplifier driver 100a, which is located in the intersection area 24a.
  • the sense amplifier circuit 98a is connected to a column of memory cells 102a, through the BL1 bus 70 (FIG. 5a) and a bit line (BL1B) bus 104a, which are both constructed in M1, and run vertically across the array 18a.
  • the intersection area 24a includes a plurality of circuits (excluding sense amplifier driver 100a and subdecoder drivers 110a-110d) which are referenced generally by the numeral 100b.
  • These circuits 100a-100b are designed to employ the advantages of the low resistance of the VDD, VSS and signal meshes 54, 56 and 58, as supplied by the buses 37a-37c.
  • the subdecoder driver 110a comprises an inverter, which converts the DXB7 bus 44d, to an inverted subdecoder (DX7) bus 114d.
  • the subdecoder drivers 110b-d convert the DXB1 44a, DXB3 44b and DXB5 44c to inverted subdecoder buses DX1 114a, DX3 114b and DX5 114c.
  • the subdecoder circuits 106a et seq employ a hierarchical word line structure. As discussed earlier, the subdecoder circuits formed in the subdecoder area 20a and 20b are used to select certain memory cells in the subarray 18a. This is accomplished by utilizing a plurality of subword lines, such as the line 72a, constructed in the polysilicon (FG) layer (FIG. 5a).
  • the MWB bus 86a drives four subdecoder circuits 106a-106d of subdecoder are 20a, which each drive a SW bus 72a-72d, extending into the subarray 18a.
  • the MWB bus 86a drives four additional subdecoder circuits 106e-106h of subdecoder area 20b, which each drive a SW bus 72e-72h, extending into the subarray 18a.
  • a conventional subdecoder circuit 116 and an alternative subdecoder circuit 118 implement a hierarchical word line structure.
  • the structures are hierarchical due to the placement of main word line buses, constructed in M2, over a subword line buses, constructed in FG.
  • the subdecoder circuits 116, 118 do not facilitate the meshed system of the present invention.
  • the conventional subdecoder circuit 116 as used in the Noda hierarchical word line structure scheme, consists of three n-type metal oxide semiconductor (NMOS) transistors and produces an SW output.
  • the subdecoder circuit 116 requires a non-inverted word line (MW) bus, which must also run across the array (not shown) along with a MWB bus. This effectively doubles the number of main word lines running in M2 across the array. As a result, two main word lines are used to drive eight subword lines, thereby creating a pitch of 4 subword lines to every main word line. This pitch, however, does not allow the extra metal space needed for the meshed system of the present invention.
  • MW non-inverted word line
  • the subdecoder circuit 118 consists of two NMOS transistors and two p-type metal oxide semiconductor (PMOS) transistors.
  • the subdecoder driver does not require a non-inverted word line bus (MW) as in FIG. 9a.
  • MW non-inverted word line bus
  • one main word line is used to drive eight subword lines, thereby creating a pitch of 8 subword lines to every main word line.
  • the subdecoder circuit consists of four transistors, it thereby consumes a lot of space, and to speed the circuit up, some of the transistors must be made very large.
  • the subdecoder circuit 106a of the preferred embodiment comprises the advantages of the above two subdecoder drivers.
  • the subdecoder circuit 106a uses the MWB bus 86a, the DXB7 bus 44d, and the DX7 bus 114d to produce the subword line SW bus 72a, thereby allowing the subdecoder circuit 106a to be constructed with only three transistors 120a-120c. Since the DX7 bus 114d runs only in the subdecoder 20a, and does not have to run horizontally across the array, the main word line pitch across the subarray 18a remains at eight subword lines for every main word line. As a result, there is sufficient metal space for the power, signal and subdecoder meshes 54, 56, 58 and 60, and the DXB bus 44 (FIG. 3) of the present invention.
  • An advantage of the subdecoder circuit 106a is that a subthreshold current in the row decoders and DXB drivers is primarily determined by NMOS transistors 120a, 120b. As a result, a low standby current is achieved during standby or precharge mode. This is because a gate with for the NMOS tranisistors 120a, 120b can be narrower than that of PMOS transistors, and NMOS transistor cutoff-transition characteristics are sharper than that of PMOS transistors.
  • the subdecoder circuit 106a provides extra metal space for the power, signal and subdecoder meshes 54, 56, 58 and 60, and the subdecoder circuit 106a improves in speed performance.
  • the speed of the subdecoder circuit 106a is directly proportional to the ability of the DX7 bus 114d to transition from low to high. Since the DX7 bus 114a is driven by the subdecoder driver 110a, and since the subdecoder driver is located in the non-crowded intersection area 24a, it can be made of sufficient size.
  • the DX7 bus 114a is constructed in M3, which has the lowest resistance of the three metal layers.
  • the equalizer section 124a includes three NMOS transistors 134a-134c for equalizing the BL1 bus 70 and the BL1B bus 104a during the standby or pre-charge modes.
  • the three transistors 134a-134c are controlled by an equalization bus 136.
  • the equalizer sections 124a and 124b are constructed in shapes of alternating "T's" as discussed in greater detail below with reference to FIG. 11a.
  • the latch sections 122a and 122b are constructed utilizing "H" shaped moat regions, as discussed in greater detail below with reference to FIGS. 12a-b.
  • a width 140 of the two gate regions is smaller than a conventional width 142 of two square gate regions 144a and 144b, as shown in FIG. 11b, and a small sense amplifier circuit 22a corresponds to the small memory cell circuit 64 (FIG. 5a).
  • the sense amplifier 22a also comprises an H-shaped moat 146.
  • the BL1 bus 70 constructed in M1, must cross the BL1B bus 104a, also constructed in M1, at the H-shaped moat 146 without electrically intersecting.
  • the BL1 bus 70 must drive a transistor gate 148a and the BL1B bus 104a must drive a transistor gate 148b.
  • the BL1B bus 104a is connected to the transistor gate 148b, constructed in FG, which runs under the metal layers.
  • the gate 148b not only serves to allow the BL1B bus 104a to cross the BL1 bus 70, but it is the gate for the transistor 130b.
  • the gate 148b is reconnected to a connecting bus 152, also constructed in M1, thereby electrically connecting the BL1B bus 104a to the connecting bus 152.
  • the BL2 bus 104b and the BL2B 104c bus also cross in the H-shaped moat 146.
  • these connections create an M1 to FG to M1 change and construct the two PMOS transistors 130a-130b. Not only does this change provide a size reduction, it does so without using an additional metal layer.
  • the H-shaped moat 146 solves another problem associated with the meshed system, that is, noise on the bit line buses 70 and 104a-104c.
  • Noise at the sense amplifiers 22a-22c is often caused by signal buses constructed in M3 overlapping the bit line buses 70 and 104a-c constructed in M1. Since the bit line buses 70 and 104a do a crossing pattern, any noise or capacitive coupling induced from signal buses constructed in M3, such as the CF bus or the YS bus, will be the same for both the BL1 bus 70 and the BL1B bus 104a, thereby effectively canceling the effect of noise. Likewise, any noise will be the same for the BL2 bus 104b and the BL2B bus 104c.
  • addition noise protection from signal buses constructed in M3 overlapping the bit line buses 70 and 104a-c constructed in M1 can be reduced through M2 shielding.
  • first and second buses 154a-154b constructed in M1 and running in a vertical direction and having a third bus 154c constructed in M3 which also running in a vertical direction
  • noise is aggravated.
  • Noise is induced from the third bus 154c to the first and second buses 154a and 154b, since they overlap and run in the same direction, allowing the noise to be strengthened by the large area of overlap.
  • This conventional design can be a problem, especially when the buses 154a, 154b are particularly sensitive to noise, such as the bit line buses 70 and 104a of the present invention. Furthermore, in the conventional design, a group of other buses 156a-156d constructed in M2 and running in a horizontal direction have little to no shielding effect, as shown.
  • the preferred embodiment reduces the noise between buses running in the same direction by improving the shielding effect of the M2 buses.
  • the BL1 bus 70 and the BL1B bus 104a are constructed in M1 and run in the vertical direction.
  • the CF bus 61a is constructed in M3 and runs in the vertical direction, just above the two bit line buses 70 and 104a. Located between the CF bus 61a and the bit line buses 70 and 104a are four buses 158a-158d constructed in M2 and running in the horizontal directions.
  • a second technique is used.
  • the bit line buses 70 and 104a are better shielded from the noise of the CF bus 61a by the quiet M2 buses 158a, 158d. Therefore, the quiet M2 buses 158a, 158d are drawn as large as possible, thereby maximizing their shielding affect.
  • the well structure of the sense amplifier can also be size determinative, especially in a situation like the preferred invention where power and signal meshes are utilized.
  • a triple well structure 160 comprising a p well (PW) 162a, a deep well (DW) 164a and a p-substrate (P-Sub) 166 is used for noise protection from a sense amplifier circuit 170 to a subarray 168a.
  • the triple well structure 160 comprises a p well (PW) 162b, a deep n-type well (DW) 164b and the P-Sub 166 for noise protection from a sense amplifier circuit 170 to a subarray 168b.
  • the wells 162a, 162b, 164a, 164b and substrate 166 may have various bias arrangements, one such arrangement provides:
  • biasing is well known in the art, and any descriptions of bias voltage are merely illustrative, and should not be limited to such in any manner.
  • the subarrays 168a and 168b are isolated from the noisy effects of the sense amplifiers 170 by two isolation n wells (NWs) 172a and 172b, respectively.
  • the NWs 172a, 172b create separation transistors for sharing one sense amplifier between memory cell arrays located on either side.
  • a negative bias voltage that is suitable for device isolation is supplied to the P-wells 162s and 162b, where the above described separation transistors and the memory cell transistors are both located.
  • the NWs 172a, 172b are biased to VPP 167b for electrical isolation.
  • the NW's 172a, 172b are located above the DWs 164a, 164b, respectively, and thereby bias the Dws to VPP.
  • the sense amplifier circuit 170 has an additional NW 174, which is biased to VDD 167d to provide faster operation of a p-type transistor 176.
  • NW 174 which is biased to VDD 167d to provide faster operation of a p-type transistor 176.
  • the advantage for DWs 164a, 164b being biased to VPP is that the subdecoders are CMOS circuits operating at the VPP voltage level (FIGS. 7a, 7b, 14c).
  • the VDD voltage level is suitable as a bias voltage for the NW 174, instead of the VPP voltage level.
  • the sense amplifier 170 also has two PWs 178a, 178b, biased to VBB 167c through the P-sub 166.
  • the PW 178a supports a transistor 180a and the PW 178b supports transistors 180b, 180c.
  • the preferred embodiment is able to shrink the well structure of the sense amplifier 24b, as compared to FIG. 14a.
  • the preferred embodiment utilizes a triple well structure 182 comprising a PW 184a, a DW 186a, and a P-Sub 188, for subarray 18a, and a PW 184b, a DW 186b, and the P-Sub 188, for subarray 18b.
  • the subarrays 18a-18b are thereby protected from the sense amplifier circuit 22b.
  • the triple well structure 182 also uses well-biasing similar to the illustrative biases described in Table 1. It is noted, however, that well biasing is well known in the art, and any descriptions of bias voltage are merely illustrative, and should not be limited to such in any manner.
  • the subarrays 18a-18b are isolated from the noisy effects of the sense amplifiers 24b by two isolation NWs 190a, 190b, respectively.
  • the isolation NWs 190a, 190b are biased to VPP 167b for isolation.
  • the isolation NWs 190a, 190b are located above the DWs 186a-186b, respectively, and thereby bias the DWs.
  • the preferred embodiment differs from the conventional system of FIG. 14a in that the isolation NW 190a also supports the transistor 130d, which corresponds with the transistor 176 of FIG. 14a. As a result, the transistor 130d will operate slower than the transistor 176 of FIG. 14a.
  • the speed of the transistor 130d is not critical to the overall timing of the sense amplifier circuit 90a. Therefore, although the PMOS transistor 130d is using a VPP biased well, there is no overall speed degradation.
  • a triple well structure 193 is implemented for the subdecoder 20a.
  • the P-Sub 188 and the DW 186a extend throughout the subarray 18a (FIG. 14b), across the subdecoder 20a, and into a subarray 196.
  • the PW 184a is separated from a PW 198 by an NW 200, which is biased to VPP 167b for isolation. By biasing the NW 200 at VPP 167b, the SW bus 72a can operate at VPP.
  • the sense amplifier 22a includes four fuses 202a-202d used for a column redundancy scheme.
  • the two fuses 202b and 202d are used to disable sense amplifier circuits 98a-98b, and the two fuses 202a and 202c are used to disable sense amplifier circuits 204a-204b.
  • Column redundancy is well known to those skilled in the art; however, conventional designs result in a dramatic area penalty in the sense amplifier design due to the fuse placement.
  • the fuses 202a-202d are lined in parallel with the bit line buses 70 and 104a, even for the fuses corresponding to sense amplifiers located in a different area. In this way, the vertical running CF bus 61a and the YS buses 35c-35d need to be offset for only one group of fuses, thereby providing the maximum space for the power and signal meshes 54, 56, 58 and 60.
US08/728,447 1995-11-09 1996-10-10 System with meshed power and signal buses on cell array Expired - Lifetime US6115279A (en)

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US08/728,447 US6115279A (en) 1995-11-09 1996-10-10 System with meshed power and signal buses on cell array
US08/991,727 US5953242A (en) 1995-11-09 1997-12-16 System with meshed power and signal buses on cell array
US09/330,579 US6069813A (en) 1995-11-09 1999-06-11 System with meshed power and signal buses on cell array
US09/496,079 US6288925B1 (en) 1995-11-09 2000-02-01 System with meshed power and signal buses on cell array
US09/909,191 US6396088B2 (en) 1995-11-09 2001-07-19 System with meshed power and signal buses on cell array
US10/120,872 US6512257B2 (en) 1995-11-09 2002-04-11 System with meshed power and signal buses on cell array
US10/315,307 US6831317B2 (en) 1995-11-09 2002-12-10 System with meshed power and signal buses on cell array
US10/728,682 US6815742B2 (en) 1995-11-09 2003-12-05 System with meshed power and signal buses on cell array
US10/945,351 US6967371B2 (en) 1995-11-09 2004-09-20 System with meshed power and signal buses on cell array
US11/158,379 US7211842B2 (en) 1995-11-09 2005-06-22 System with meshed power and signal buses on cell array
US11/683,930 US7323727B2 (en) 1995-11-09 2007-03-08 System with meshed power and signal buses on cell array

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US550295P 1995-11-09 1995-11-09
US08/728,447 US6115279A (en) 1995-11-09 1996-10-10 System with meshed power and signal buses on cell array

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US08/991,727 Division US5953242A (en) 1995-11-09 1997-12-16 System with meshed power and signal buses on cell array
US09/909,191 Continuation US6396088B2 (en) 1995-11-09 2001-07-19 System with meshed power and signal buses on cell array

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US08/991,727 Expired - Lifetime US5953242A (en) 1995-11-09 1997-12-16 System with meshed power and signal buses on cell array
US09/330,579 Expired - Lifetime US6069813A (en) 1995-11-09 1999-06-11 System with meshed power and signal buses on cell array
US09/496,079 Expired - Lifetime US6288925B1 (en) 1995-11-09 2000-02-01 System with meshed power and signal buses on cell array
US09/909,191 Expired - Lifetime US6396088B2 (en) 1995-11-09 2001-07-19 System with meshed power and signal buses on cell array

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US09/330,579 Expired - Lifetime US6069813A (en) 1995-11-09 1999-06-11 System with meshed power and signal buses on cell array
US09/496,079 Expired - Lifetime US6288925B1 (en) 1995-11-09 2000-02-01 System with meshed power and signal buses on cell array
US09/909,191 Expired - Lifetime US6396088B2 (en) 1995-11-09 2001-07-19 System with meshed power and signal buses on cell array

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JP2007052913A (ja) 2007-03-01
JPH09135006A (ja) 1997-05-20
KR100445952B1 (ko) 2004-11-10
US6288925B1 (en) 2001-09-11
SG63677A1 (en) 1999-03-30
US20020000583A1 (en) 2002-01-03
KR970029835A (ko) 1997-06-26
CN1155004C (zh) 2004-06-23
JP3869045B2 (ja) 2007-01-17
JP4550035B2 (ja) 2010-09-22
CN1152173A (zh) 1997-06-18
US6396088B2 (en) 2002-05-28
US5953242A (en) 1999-09-14
US6069813A (en) 2000-05-30

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