SG63677A1 - System with meshed power and signal buses on cell array - Google Patents

System with meshed power and signal buses on cell array

Info

Publication number
SG63677A1
SG63677A1 SG1996011039A SG1996011039A SG63677A1 SG 63677 A1 SG63677 A1 SG 63677A1 SG 1996011039 A SG1996011039 A SG 1996011039A SG 1996011039 A SG1996011039 A SG 1996011039A SG 63677 A1 SG63677 A1 SG 63677A1
Authority
SG
Singapore
Prior art keywords
cell array
signal buses
meshed power
meshed
power
Prior art date
Application number
SG1996011039A
Other languages
English (en)
Inventor
Goro Kitsukawa
Hiroshi Otori
Jeffrey E Koelling
Takesada Akiba
Troy H Herndon
William R Mckee
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of SG63677A1 publication Critical patent/SG63677A1/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065Differential amplifiers of latching type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18Bit line organisation; Bit line lay-out
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/14Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
SG1996011039A 1995-11-09 1996-11-06 System with meshed power and signal buses on cell array SG63677A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US550295P 1995-11-09 1995-11-09

Publications (1)

Publication Number Publication Date
SG63677A1 true SG63677A1 (en) 1999-03-30

Family

ID=21716204

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996011039A SG63677A1 (en) 1995-11-09 1996-11-06 System with meshed power and signal buses on cell array

Country Status (6)

Country Link
US (5) US6115279A (ja)
JP (2) JP3869045B2 (ja)
KR (1) KR100445952B1 (ja)
CN (1) CN1155004C (ja)
SG (1) SG63677A1 (ja)
TW (1) TW315468B (ja)

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US7180718B2 (en) * 2003-01-31 2007-02-20 X2Y Attenuators, Llc Shielded energy conditioner
US6924661B2 (en) * 2003-02-10 2005-08-02 International Business Machines Corporation Power switch circuit sizing technique
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JP2007194496A (ja) * 2006-01-20 2007-08-02 Toshiba Corp 半導体集積回路
EP1991996A1 (en) 2006-03-07 2008-11-19 X2Y Attenuators, L.L.C. Energy conditioner structures
JP4600835B2 (ja) * 2006-07-31 2010-12-22 エルピーダメモリ株式会社 半導体集積回路
KR100761854B1 (ko) * 2006-08-08 2007-09-28 삼성전자주식회사 비트라인 이퀄라이저 및 이를 구비하는 반도체 메모리장치, 그리고 비트라인 이퀄라이저의 제조 방법
US7752578B2 (en) * 2006-10-19 2010-07-06 Apache Design Solutions, Inc. Automatic voltage drop optimization
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JP5079342B2 (ja) 2007-01-22 2012-11-21 ルネサスエレクトロニクス株式会社 マルチプロセッサ装置
US8411482B2 (en) * 2008-08-20 2013-04-02 Intel Corporation Programmable read only memory
US7760578B2 (en) * 2008-10-20 2010-07-20 Lsi Logic Corporation Enhanced power distribution in an integrated circuit
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8525327B2 (en) 2011-10-03 2013-09-03 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
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JP2014528652A (ja) 2011-10-03 2014-10-27 インヴェンサス・コーポレイション パッケージの中心から端子グリッドをオフセットすることによるスタブ最小化
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
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US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
WO2014112472A1 (ja) * 2013-01-15 2014-07-24 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
US9117804B2 (en) * 2013-09-13 2015-08-25 United Microelectronics Corporation Interposer structure and manufacturing method thereof
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
JP6308831B2 (ja) * 2014-03-25 2018-04-11 ルネサスエレクトロニクス株式会社 半導体記憶装置
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
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Also Published As

Publication number Publication date
JPH09135006A (ja) 1997-05-20
US6288925B1 (en) 2001-09-11
TW315468B (en) 1997-09-11
US20020000583A1 (en) 2002-01-03
KR970029835A (ko) 1997-06-26
JP4550035B2 (ja) 2010-09-22
JP2007052913A (ja) 2007-03-01
KR100445952B1 (ko) 2004-11-10
US6396088B2 (en) 2002-05-28
CN1152173A (zh) 1997-06-18
US6069813A (en) 2000-05-30
US6115279A (en) 2000-09-05
JP3869045B2 (ja) 2007-01-17
CN1155004C (zh) 2004-06-23
US5953242A (en) 1999-09-14

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