US5558313A - Trench field effect transistor with reduced punch-through susceptibility and low RDSon - Google Patents

Trench field effect transistor with reduced punch-through susceptibility and low RDSon Download PDF

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Publication number
US5558313A
US5558313A US08/386,895 US38689595A US5558313A US 5558313 A US5558313 A US 5558313A US 38689595 A US38689595 A US 38689595A US 5558313 A US5558313 A US 5558313A
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Prior art keywords
layer
region
trench
transistor
body region
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Expired - Lifetime
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US08/386,895
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English (en)
Inventor
Fwu-Iuan Hshieh
Mike F. Chang
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Vishay Siliconix Inc
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Siliconix Inc
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Priority claimed from US07/918,954 external-priority patent/US5910669A/en
Priority claimed from US08/131,114 external-priority patent/US5479037A/en
Assigned to SILICONIX INCORPORATED reassignment SILICONIX INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, MIKE F., HSHIEH, FWU-IUAN
Priority to US08/386,895 priority Critical patent/US5558313A/en
Application filed by Siliconix Inc filed Critical Siliconix Inc
Priority to JP08524276A priority patent/JP3108439B2/ja
Priority to PCT/US1996/000941 priority patent/WO1996024953A1/fr
Priority to AU49650/96A priority patent/AU4965096A/en
Priority to CA002212765A priority patent/CA2212765A1/fr
Priority to EP96906189A priority patent/EP0808513A4/fr
Priority to US08/658,115 priority patent/US5981344A/en
Publication of US5558313A publication Critical patent/US5558313A/en
Application granted granted Critical
Assigned to COMERICA BANK, AS AGENT reassignment COMERICA BANK, AS AGENT SECURITY AGREEMENT Assignors: SILICONIX INCORPORATED, VISHAY DALE ELECTRONICS, INC., VISHAY INTERTECHNOLOGY, INC., VISHAY MEASUREMENTS GROUP, INC., VISHAY SPRAGUE, INC., SUCCESSOR IN INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC
Assigned to SILICONIX INCORPORATED, A DELAWARE CORPORATION, VISHAY DALE ELECTRONICS, INC., A DELAWARE CORPORATION, VISHAY GENERAL SEMICONDUCTOR, LLC, F/K/A GENERAL SEMICONDUCTOR, INC., A DELAWARE LIMITED LIABILITY COMPANY, VISHAY INTERTECHNOLOGY, INC., A DELAWARE CORPORATION, VISHAY MEASUREMENTS GROUP, INC., A DELAWARE CORPORATION, VISHAY SPRAGUE, INC., SUCCESSOR-IN-INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC, A DELAWARE CORPORATION, VISHAY VITRAMON, INCORPORATED, A DELAWARE CORPORATION, YOSEMITE INVESTMENT, INC., AN INDIANA CORPORATION reassignment SILICONIX INCORPORATED, A DELAWARE CORPORATION RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: COMERICA BANK, AS AGENT, A TEXAS BANKING ASSOCIATION (FORMERLY A MICHIGAN BANKING CORPORATION)
Assigned to JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT reassignment JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT SECURITY AGREEMENT Assignors: SILICONIX INCORPORATED, VISHAY DALE ELECTRONICS, INC., VISHAY INTERTECHNOLOGY, INC., VISHAY SPRAGUE, INC.
Anticipated expiration legal-status Critical
Assigned to VISHAY INTERTECHNOLOGY, INC., VISHAY SPRAGUE, INC., SPRAGUE ELECTRIC COMPANY, VISHAY TECHNO COMPONENTS, LLC, VISHAY VITRAMON, INC., VISHAY EFI, INC., DALE ELECTRONICS, INC., VISHAY DALE ELECTRONICS, INC., SILICONIX INCORPORATED reassignment VISHAY INTERTECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827Vertical transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Definitions

  • a positive potential is placed on gate 9.
  • the positive potential causes a channel region to form in the portion of the P body region 3A which forms part of the sidewall of the trench and causes an accumulation region to form in the portion of the N type epitaxial layer region 1A which forms a part of the sidewall of the trench. Electrons can then flow as indicated by the arrow from the N+ type source region 5, downward through the channel region of P body region 3A, downward through the accumulation region, downward through the remainder of the N type epitaxial region 1A, downward through the N+ type substrate 2, and to a drain electrode 7. If gate 9 does not have a positive potential, then no channel is formed and no electron flow from source to drain takes place. The transistor is therefore turned off.
  • FIG. 4 is a simplified cross-sectional diagram of a trench double diffused field effect transistor which does not incur the resistance penalty that the transistor of FIG. 3 does.
  • a lightly doped N- type epitaxial layer 201 is disposed on a more heavily doped N type epitaxial layer 202 which is in turn disposed on a more heavily doped N+ type substrate layer 203.
  • a P body region 204 is formed into the epitaxial layers 201 and 202 from upper surface 205 to form a relatively heavily doped epitaxial region 202A and a relatively light doped epitaxial region 201A.
  • N+ type source region 206 is formed into P body region 204 from upper surface 205.
  • the drain 207 is located on the underside of the substrate 203.
  • the structure of FIG. 4 does not incur the resistance penalty associated with the planar structure of FIG. 3 because electron flow proceeds through the N- type epitaxial region 201A in an accumulation region along the sidewall of the trench.
  • the resistance in an accumulation region is substantially independent of dopant concentration.
  • the gate/trench structure therefore forms a means for controllably forming the accumulation region. After the electrons have passed through the N- type epitaxial region 201A, the electrons pass through the relatively heavily doped N type epitaxial region 202A where the resistance is also low.
  • FIG. 7 is a diagram showing an approximate dopant profile along the line labeled B--B in FIG. 6.
  • the 3-9E15 dopant concentration is the dopant concentration of the relatively lightly doped N- type epitaxial region 201A of FIG. 6. Due to the heavily doped N+ type substrate 203 being in close proximity to gate 209A, a relatively high electric field develops between gate 209A and N+ substrate 203 as compared to the electric field developed between gate 209 and N type epitaxial region 202A of FIG. 4.
  • the net P type peak doping concentration in the channel region of P type body region 204 is 3-9E16.
  • Approximate thickness ranges for the embodiment of FIG. 6 are 0.5 microns for source region 206, 1.0-2.0 microns for P body region 204 at the trench sidewall, 1.0-2.0 microns from the bottom of the P body region at the sidewall to the top of N+ substrate layer 203.
  • the gate oxide may, for example, be 150-1000 angstroms thick.
  • the trench may be approximately 1.2-6.0 microns deep.
  • the bottom of the trench may be approximately 0.5-1.0 microns from the top of N+ type substrate layer 203.
  • Epitaxial layer 201 may be approximately 2.0-5.0 microns thick.
  • the short channel renders the transistor usable in low threshold voltage applications such as battery applications.
US08/386,895 1992-07-24 1995-02-10 Trench field effect transistor with reduced punch-through susceptibility and low RDSon Expired - Lifetime US5558313A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US08/386,895 US5558313A (en) 1992-07-24 1995-02-10 Trench field effect transistor with reduced punch-through susceptibility and low RDSon
JP08524276A JP3108439B2 (ja) 1995-02-10 1996-02-07 発生する確率の低減されたパンチスルーと、低いRDSonとを備えた溝型電界効果トランジスタ
PCT/US1996/000941 WO1996024953A1 (fr) 1995-02-10 1996-02-07 Transistor a effet de champ avec une tranchee, presentant une sensibilite diminuee au claquage et une resistance source-drain basse
AU49650/96A AU4965096A (en) 1995-02-10 1996-02-07 Trench field effect transistor with reduced punch-through susceptibility and low rdson
CA002212765A CA2212765A1 (fr) 1995-02-10 1996-02-07 Transistor a effet de champ avec une tranchee, presentant une sensibilite diminuee au claquage et une resistance source-drain basse
EP96906189A EP0808513A4 (fr) 1995-02-10 1996-02-07 Transistor a effet de champ avec une tranchee, presentant une sensibilite diminuee au claquage et une resistance source-drain basse
US08/658,115 US5981344A (en) 1992-07-24 1996-06-04 Trench field effect transistor with reduced punch-through susceptibility and low RDSon

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US07/918,954 US5910669A (en) 1992-07-24 1992-07-24 Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof
US92533692A 1992-08-04 1992-08-04
US08/131,114 US5479037A (en) 1992-08-04 1993-10-01 Low threshold voltage epitaxial DMOS technology
US08/386,895 US5558313A (en) 1992-07-24 1995-02-10 Trench field effect transistor with reduced punch-through susceptibility and low RDSon

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
US07/918,954 Continuation-In-Part US5910669A (en) 1992-07-24 1992-07-24 Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof
US08/131,114 Continuation-In-Part US5479037A (en) 1992-07-24 1993-10-01 Low threshold voltage epitaxial DMOS technology

Related Child Applications (1)

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US08/658,115 Division US5981344A (en) 1992-07-24 1996-06-04 Trench field effect transistor with reduced punch-through susceptibility and low RDSon

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US5558313A true US5558313A (en) 1996-09-24

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US08/386,895 Expired - Lifetime US5558313A (en) 1992-07-24 1995-02-10 Trench field effect transistor with reduced punch-through susceptibility and low RDSon
US08/658,115 Expired - Lifetime US5981344A (en) 1992-07-24 1996-06-04 Trench field effect transistor with reduced punch-through susceptibility and low RDSon

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US08/658,115 Expired - Lifetime US5981344A (en) 1992-07-24 1996-06-04 Trench field effect transistor with reduced punch-through susceptibility and low RDSon

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US (2) US5558313A (fr)
EP (1) EP0808513A4 (fr)
JP (1) JP3108439B2 (fr)
AU (1) AU4965096A (fr)
CA (1) CA2212765A1 (fr)
WO (1) WO1996024953A1 (fr)

Cited By (27)

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US5637898A (en) * 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
US5679966A (en) * 1995-10-05 1997-10-21 North Carolina State University Depleted base transistor with high forward voltage blocking capability
WO1997042663A1 (fr) * 1996-05-08 1997-11-13 Siliconix Incorporated Fabrication de transistors dmos a tranchee de haute densite utilisant des elements d'espacement des parois laterales
US5688725A (en) * 1994-12-30 1997-11-18 Siliconix Incorporated Method of making a trench mosfet with heavily doped delta layer to provide low on-resistance
WO1998004004A1 (fr) * 1996-07-19 1998-01-29 Siliconix Incorporated Transistor dmos pour tranchees a haute densite a implant de fond de tranchee
US5742076A (en) * 1996-06-05 1998-04-21 North Carolina State University Silicon carbide switching devices having near ideal breakdown voltage capability and ultralow on-state resistance
US5821583A (en) * 1996-03-06 1998-10-13 Siliconix Incorporated Trenched DMOS transistor with lightly doped tub
US5844273A (en) * 1994-12-09 1998-12-01 Fuji Electric Co. Vertical semiconductor device and method of manufacturing the same
US5877538A (en) * 1995-06-02 1999-03-02 Silixonix Incorporated Bidirectional trench gated power MOSFET with submerged body bus extending underneath gate trench
US6031265A (en) * 1997-10-16 2000-02-29 Magepower Semiconductor Corp. Enhancing DMOS device ruggedness by reducing transistor parasitic resistance and by inducing breakdown near gate runners and termination area
US6040212A (en) * 1996-08-16 2000-03-21 Fairchild Korea Semiconductor, Ltd. Methods of forming trench-gate semiconductor devices using sidewall implantation techniques to control threshold voltage
US6087215A (en) * 1996-12-27 2000-07-11 Hyundai Electronics Industries Co., Ltd. Method of fabricating a DRAM device
US6096608A (en) * 1997-06-30 2000-08-01 Siliconix Incorporated Bidirectional trench gated power mosfet with submerged body bus extending underneath gate trench
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US6168996B1 (en) * 1997-08-28 2001-01-02 Hitachi, Ltd. Method of fabricating semiconductor device
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