US5536952A - Heterojunction bipolar transistor - Google Patents

Heterojunction bipolar transistor Download PDF

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US5536952A
US5536952A US08/280,805 US28080594A US5536952A US 5536952 A US5536952 A US 5536952A US 28080594 A US28080594 A US 28080594A US 5536952 A US5536952 A US 5536952A
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layer
sic
transistor
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collector
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Shinichi Shikata
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Priority claimed from JP6610792A external-priority patent/JPH05275440A/ja
Priority claimed from JP06610892A external-priority patent/JP3339508B2/ja
Priority claimed from JP8726092A external-priority patent/JPH05291277A/ja
Priority claimed from JP8726892A external-priority patent/JPH05291278A/ja
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Priority to US08/280,805 priority Critical patent/US5536952A/en
Priority to US08/417,781 priority patent/US5624853A/en
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    • H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/931—Silicon carbide semiconductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/932—Boron nitride semiconductor

Definitions

  • the present invention relates to a semiconductor device having a high environmental resistance.
  • the carrier mobility of silicon is an obstacle against the development of elements.
  • a countermeasure against this problem is a method of precisely micropatterning elements, but the micropatterned element in turn poses another problem regarding allowable power characteristics including heat resistance.
  • GaAs having a high carrier mobility has been used in place of silicon for the above applications.
  • Similar problems are posed by high-speed digital circuits (e.g., a supercomputer). For this reason digital ICs using GaAs aS a semiconductor material have been developed and are often used in practice.
  • a material having a large band gap is preferably used in the above applications.
  • a heterojunction bipolar transistor is assumed as one of the devices which can replace conventional silicon bipolar semiconductor devices. Examples of the heterojunction bipolar transistor are disclosed in Japanese Patent Laid-Open No. 62-216364, 62-265762, 62-160760, and 62-159463. These examples are transistors each utilizing a heterojunction formed between silicon and silicon carbide.
  • silicon is used as a material, drastic solutions to the problems on a low breakdown voltage and a low resistance to environment cannot be provided. Since materials such as diamond and silicon carbide have large band gaps among the currently available materials, good performance can be expected in the above applications if these materials are used. Extensive studies have Seen made to develop a better semiconductor material using these materials in applications which cannot be handled by the silicon semiconductor, as described in Japanese Patent Laid-Open No. 64-55862 filed by the present applicant.
  • the first and second layers are made of silicon carbide layers having the same crystal structure to form a homojunction between the base and collector region, thereby further facilitating formation of a good semiconductor layer.
  • hexagonal silicon carbide can be used for the emitter region as a material having a larger band gap than that of cubic silicon carbide.
  • an SiC substrate is used as a substrate, and the collector, emitter, and base regions are sequentially formed on the SiC substrate, so that a substrate having a large area can be used to facilitate mass production of devices.
  • a layer (third layer) using diamond or BP x N 1-x serves as the uppermost layer in the emitter region.
  • the third layer may partially have a uniform crystal structure. This uniform crystal region can be used to arrange a device, thus providing an advantage in that diamond or BPN need not be formed on a large area.
  • the third layer may have a polycrystalline structure because a polycrystalline layer can be more easily formed.
  • these semiconductor layers can be properly formed on the substrate because these layers and the substrate are made of the same material.
  • either pnp or npn devices can be formed.
  • the bipolar transistor Since the bipolar transistor has a heterojunction made of a semiconductor having a large band gap, a large collector current can be obtained by a small base current in accordance with the potential barrier formed by this heterojunction.
  • the bipolar transistor has resistance to radiation and can be properly operated at very high temperatures. Since the band gap of the collector is large, the bipolar transistor has a high collector breakdown voltage. This allows formation of a good device as compared with a GaAs device.
  • a semiconductor device which can properly operate can be manufactured.
  • FIG. 1 is a sectional view showing the structure of the first embodiment
  • FIGS. 2A to 2D are sectional views for explaining the steps in manufacturing a transistor shown in FIG. 1;
  • FIGS. 3A and 3B are band diagrams of the transistor shown in FIG. 1;
  • FIG. 4 is a sectional view showing a transistor identical to that of FIG. 1 and having a self-aligned structure
  • FIGS. 5A to 5D are sectional views for explaining the steps in manufacturing the transistor shown in FIG. 4;
  • FIG. 6 is a sectional view showing the structure of the second embodiment
  • FIGS. 7A to 7D are sectional views for explaining the steps in manufacturing a transistor shown in FIG. 6;
  • FIGS. 8A and 8B are band diagrams of the transistor shown in FIG. 6;
  • FIG. 9 is a sectional view showing a transistor identical to that of FIG. 6 and having a self-aligned structure
  • FIGS. 10A to 10D are sectional views for explaining the steps in manufactnring the transistor shown in FIG. 6;
  • FIG. 11 is a sectional view showing the structure of the third embodiment.
  • FIGS. 12A to 12D are sectional views for explaining the step in manufacturing a transistor shown in FIG. 11;
  • FIGS. 13A and 13B are band diagrams of the transister shown in FIG. 11;
  • FIG. 14 is a sectional view showing a transistor identical to that of FIG. 11 and having a self-aligned structure
  • FIGS. 15A to 15D are sectional views for explaining the steps in manufacturing the transistor shown in FIG. 14;
  • FIG. 16 is a sectional view showing the structure of the fourth embodiment.
  • FIGS. 17A to 17D are sectional views for explaining the steps in manufacturing a transistor shown in FIG. 16;
  • FIGS. 18A and 18B are band diagrams of the transistor shown in FIG. 16;
  • FIG. 19 is a sectional view showing a transistor identical to that of FIG. 16 and having a self-aligned structure.
  • FIGS. 20A to 20D are sectional views for explaining the step in manufacturing the transistor shown in FIG. 19.
  • FIG. 1 shows the structure of a transistor according to an embodiment.
  • a p + -diamond layer 120, a p-diamond layer 130, an n + -SiC layer 140, a p-SiC layer 150, and a p + -SiC layer 160 are sequentially formed on a nondoped diamond substrate 110.
  • An emitter electrode 210, a base electrode 220, and a collector electrode 230 are electrically connected to the p + -diamond layer 120, the n + -SiC layer 140, and the p + -SiC layer 160, respectively.
  • SiC is defined herein to have a cubic crystal structure (3C-SiC or ⁇ -SiC).
  • p, p + , n, and n + represent p- and n-type semiconductor layers, and suffix "+" represent relatively high impurity concentrations, respectively.
  • This transistor is manufactured by the following steps.
  • the p + -diamond layer 120 and the p-type diamond layer 130 are sequentially formed on the diamond substrate 110 by a microwave CVD method.
  • the microwave had a frequency of 2.45 GHz and an output power of 400 W
  • a source gas was a gas mixture of CH 4 /H 2 at a ratio of 4: 100.
  • the growth conditions were a pressure of 500 Torr and a temperature of 600° to 900° C.
  • B 2 H 6 is mixed in the source gas to dope B (boron), and the content of B is changed to form the p + -diamond layer 120 and the p-diamond layer 130.
  • the n + -SiC layer 140, the p-SiC layer 150, and the p + -SiC layer 160 are sequentially formed by a low-pressure CVD method.
  • the source gas was a gas mixture of C 3 H 8 /SiHCl 2 at a mixing ratio of 1: 2. H 2 was used as a carrier gas.
  • the growth conditions were a pressure of 200 Pa and a temperature of 900° to 1,200° C.
  • PH 3 is mixed in the source gas to dope P (phosphorus).
  • B 2 H 6 is mixed in the source gas to dope B, thereby growing the p-SiC layer 150 and the p + -SiC layer 160 (FIG. 2A).
  • a mask is formed except for portions corresponding to the collector and base regions.
  • the p-SiC layer 150, the p + -SiC layer 160, and the n + -SiC layer 140 are etched by RIE (Reactive Ion Etching) (FIG. 2B).
  • RIE Reactive Ion Etching
  • a reaction gas is a gas mixture of CF 4 +O 2 (5%).
  • the p - -diamond layer 130 is etched by RIBE (Reactive Ion Beam Etching) using a gas mixture of Ar+N 2 O (20%) and a resist on the n + -SiC layer 140 as a mask (FIG. 2C).
  • the AlSi emitter electrode 210, the TaSi base electrode 220, and the Mo/Au collector electrode 230 are formed and wired (FIG. 2D). In these steps, a sample was formed, and its characteristics were measured. A current gain of 1,200 and a collector breakdown voltage of 20 V were obtained. A good operation was performed even at a temperature of 300° C.
  • the collector and base form a homojunction
  • the base and emitter form a heterojunction. Therefore, these layers can be formed with high precision.
  • This transistor is a pnp transistor having a heterojunction formed by p-type diamond and n-type SiC.
  • the p - -diamond layer 130 having a low carrier concentration is formed together with the heterojunction between the emitter and base.
  • the p - -SiC layer 150 having a low carrier concentration is formed between the collector and base.
  • This transistor is operated using holes as a majority carrier and is estimated to have a band diagram shown in FIG. 3A.
  • the band gap of the emitter region is about 5.5 eV
  • the band gap of each of the base and collector regions is about 2.2 eV
  • a band gap difference of about 3.3 eV is present between the emitter and base.
  • FIG. 3B is a band diagram showing a state wherein the transistor is DC-biased.
  • electrons are distributed in a Fermi-Dirac distribution at a portion higher than the energy level of the lower end of the conduction band of the base region (n + -SiC layer 140).
  • the Fermi-Dirac distribution of holes is obtained at a portion higher than energy levels E V1 and E V2 of the upper end of the valence band.
  • the holes have a higher energy in a downward direction.
  • a DC bias operation will be described with reference to FIG. 3B.
  • the transistor is forward-biased such that the emitter has a positive voltage and the base has a negative voltage.
  • the energy level of the base region is higher than that of the emitter region.
  • forward biasing is performed such that the collector has a negative voltage, the energy level of the collector region becomes high.
  • Electrons as a minority carrier are injected from the base, but only a small number of electrons having an energy higher than the potential carrier of the emitter region flow to the emitter.
  • the potential barrier of the valence band is lowered by the heterojunction, and the potential barrier is also lowered by the bias. For this reason, most of the holes flow in the collector region through the base region. Therefore, a large collector current flows with a small base current, thereby obtaining a large current amplification factor.
  • the device can be properly operated even at high temperatures although the band gap of SiC is slightly narrowed at such high temperatures. In addition, the device can be operated even at a high collector voltage. This device is superior to a state-of-the-art transistor by properly selecting parameters such as a film thickness.
  • the above-mentioned transistor may be manufactured to have a self-aligned structure, as known in a compound semiconductor (e.g., GaAs ).
  • a compound semiconductor e.g., GaAs
  • a compound semiconductor is used to form an HBT manufactured by self-alignment using an insulating film on a side wall, as described in Hayama et al., Fully Self-Aligned AlGaAs/GaAs HBT having AlGaAs Passivation Layer, the Institute of Electronics and Information, Technical Report ED-89-147 (1989), PP. 68-69.
  • This structure is applied to the above-mentioned transistor, as shown in FIG. 4.
  • FIGS. 5A to 5D show the steps in manufacturing the transistor shown in FIG. 4.
  • the transistor may have a structure in which a polyimide resin is used to form an insulating film, as described in Morizuka et al., "AlGaAs/GaAs HBT's Fabricated by a Self-Alignment Technology Using Polyimide For Electrode Separation” IEEE Electron Device Letters, EDL-9, 598 (1988), or an integrated structure, as described in HAN-TZONG YUAN, et al., "The Development of Heterojunction Integrated Injection Logic", IEEE TRANSACTION ON ELECTRON DEVICE, Vol. 36, No. 10., October. Another example of such a transistor is described in K.
  • the base electrode 220 is self-aligned by an SiO 2 protective film 170 formed on the side surfaces of the p-SiC layer 150 and the p + -SiC layer 160.
  • the emitter region is etched and the emitter electrode 210 is formed, using an SiO 2 protective film 180 on the base electrode 220.
  • a p + -diamond layer 120, a p-diamond layer 130, an n + -SiC layer 140, a p-SiC layer 150, and a p + -SiC layer 160 are sequentially formed on a nondoped diamond substrate 110 (FIG. 5A). Thereafter, the p - -SiC layer 150 and the p + -SiC layer 160 are eliminated using a mask formed except for a portion serving as a collector region, and a protective film 170 is formed (FIG. 5B).
  • a base electrode 220 and an SiO 2 protective film 180 are formed, and the p-diamond layer 130 and the n + -SiC layer 140 are etched using the base electrode 220 and the SiO 2 protective film 180 as masks (FIG. 5C).
  • An emitter electrode 210 and a collector electrode 230 are then formed (FIG. 5D).
  • the same etching conditions as in the above embodiment are used in this process, and the same mask material and insulating material as in the above references can be used.
  • Etching is performed using the protective films 170 and 180, and the like to form the electrodes. For this reason, the number of photomasks in the fabrication process can be small, and the photolithographic process including resist coating can be simplified. Error factors caused by mask alignment can be reduced, and a finer micropattern can be formed.
  • SiC is exemplified to have a cubic crystal structure.
  • SiC may have a hexagonal crystal structure (called 6H-SiC or ⁇ -Sic).
  • 6H-SiC has a band gap of 2.86 eV (band gap difference: 1.54 eV), and a higher voltage than that required for 3C-SiC is required, but heat resistance and collector breakdown voltage can be improved.
  • FIG. 6 shows the structure of a transistor according to the second embodiment.
  • a p + -SiC layer 160, a p-SiC layer 150, an n + -SiC layer 140, a p-diamond layer 130, and a p + -diamond layer 120 are sequentially formed on a nondoped SiC substrate 111.
  • a collector electrode 230, a base electrode 220, and an emitter electrode 210 are formed on and electrically connected to the p + -SiC layer 160, the n + -SiC layer 140, and the p + -diamond layer 120, respectively.
  • SiC is defined herein to have a cubic crystal structure (called 3C-SiC or ⁇ -SiC).
  • This transistor is manufactured by the following steps.
  • the p + -SiC layer 160, the p-SiC layer 150, and the n + -SiC layer 140 are sequentially formed on the SiC substrate 111 by a low-pressure CVD method.
  • a source gas was a gas mixture of C 3 H 8 /SiHCl 2 at a mixing ratio of 1: 2, H 2 was used as a carrier gas, and the growth conditions were a pressure of 200 Pa and a temperature of 900° to 1,200° C.
  • PH 3 is mixed in the source gas to dope P (phosphorus).
  • B 2 H 6 is mixed in the source gas to dope B (boron) to grow the p-SiC layer 150 and the p + -SiC layer 160.
  • the p-diamond layer 130 and the p + -diamond layer 120 are sequentially formed by a microwave CVD method.
  • the microwave had a frequency of 2.45 GHz and an output power of 400 W.
  • a source gas was a gas mixture of CH 4 /H 2 at a mixing ratio of 4: 100, and the growth conditions were a pressure of 500 Torr and a temperature of 600° to 900° C.
  • B 2 H 6 is mixed in the source gas to dope B, and the content of B is changed to grow the p + -diamond layer 120 and the p-diamond layer 130 (FIG. 7A).
  • the resultant structure is masked except for portions serving as the emitter and base regions, and the diamond layers 120 and 130 are etched by RIBE (Reactive Ion Beam Etching) using a gas mixture of Ar+N 2 O (20%) (FIG. 7B). Thereafter, the p-SiC layer 150 and the n + -SiC layer 140 are etched by RIE (Reactive Ion Etching) using a resist on the diamond layers 120 and 130 as a mask (FIG. 7C). At this time, the reaction gas is a gas mixture of CF 4 +O 2 (5%).
  • the AlSi emitter electrode 210, the TaSi base electrode 220, and the Mo/Au collector electrode 230 are formed and wired (FIG. 7D). A sample was formed by these steps, and the characteristics of the sample were measured. The sample had a current gain of 1,200 and a collector breakdown voltage of 20 V. The sample was properly operated even at a temperature of 300° C.
  • This transistor is a pnp transistor having a heterojunction formed by p-type diamond and n-type SiC.
  • the p-diamond layer 130 having a low carrier concentration is formed together with the heterojunction between the emitter and base.
  • the p-SiC layer 150 having a low carrier concentration is formed between the collector and base.
  • This transistor is operated using holes as a majority carrier and is estimated to have a band diagram shown in FIG. 8A.
  • the band gap of the emitter region is about 5.5 eV
  • the band gap of each of the base and collector regions is about 2.2 eV
  • a band gap difference of about 3.3 eV is present between the emitter and base.
  • FIG. 8B is a band diagram showing a state wherein the transistor is DC-biased.
  • electrons are distributed in a Fermi-Dirac distribution at a portion higher than the energy level of the lower end of the conduction band of the base region (n + -SiC layer 140).
  • the Fermi-Dirac distribution of holes is obtained at a portion higher than energy levels E V1 and E V2 of the upper end of the valence band.
  • the holes have a higher energy in a downward direction.
  • a DC biased operation will be described with reference to FIG. 8B.
  • the transistor is forward-biased such that the emitter has a positive voltage and the base has a negative voltage.
  • the energy level of the base region is higher than that of the emitter region.
  • forward biasing is performed such that the collector has a negative voltage, the energy level of the collector region becomes high.
  • Electrons as a minority carrier are injected from the base, but only a small number of electrons having an energy higher than the potential carrier of the emitter region flow to the emitter.
  • the potential barrier of the valence band is lowered by the heterojunction, and the potential barrier is also lowered by the bias. For this reason, most of the holes flow in the collector region through the base region.
  • a band gap difference between SiC and Si of the conventional structure is 1.1 eV, and a larger current amplification factor than that of the conventional structure can be obtained.
  • the device can be properly operated even at high temperatures although the band gap of SiC is slightly narrowed at such high temperatures. In addition, the device can be operated even at a high collector voltage. This device is superior to a state-of-the-art transistor by properly selecting parameters such as a film thickness.
  • SiC having a high heat conductivity and a low dielectric constant is used as the material for the substrate, good heat dissipation properties can be obtained. In addition, the stray capacitance of a wiring layer can be reduced. These advantages are enhanced when the device is used with a high power at a high frequency. In addition, since the SiC layers 160,150, and 140 are made of the same material, they can be properly formed. A homojunction between the base and collector is also an advantage of this transistor.
  • the p-diamond layer 130 and the p + -diamond layer 120 are formed as the uppermost layers, these layers are finally formed in the fabrication process. For this reason, in the formation of these layers, a diamond layer having a size (1 to 10 ⁇ .sup. ⁇ ) corresponding to the emitter size, can be selectively grown. For this reason, the diamond layer need not be formed to have a large size, and the manufacturing problems can be reduced.
  • the diamond layers 130 and 120 are preferably formed by monocrystalline diamond, but may be formed by polycrystalline diamond. In the latter case, although the current injection efficiency and the current amplification factor are reduced, fabrication can be properly performed.
  • a polycrystalline diamond layer having a relatively uniform orientation, i.e., 95% or more of the (110) planes was formed as a sample layer, following the same procedures as in the above embodiment.
  • a transistor having a current gain of 250 was obtained with this diamond layer.
  • FIG. 9 shows the self-aligned structure of the transistor in FIG. 6.
  • a base electrode 220 is self-aligned by an SiOn. protective film 170 formed on the side wall of the diamond layers 130 and 120.
  • an SiO 2 protective film 180 on the base electrode 220 is used to etch the collector region and form the collector electrode 230.
  • FIGS. 10A to 10D show the steps in manufacturing this transistor. These steps are performed under the same etching conditions as in the previous embodiment, and any other structure is the same as that in FIG. 4.
  • the p + -SiC layer 160, the p-SiC layer 150, and the n + -SiC layer 140 are sequentially formed on the SiC substrate 111 following the same procedures as in FIG. 7A (FIG. 10A).
  • the resultant structure is masked except for a portion serving as an emitter region, and the p-diamond layer 130 and the p + -diamond layer 120 are formed by the selective growth described above, thereby forming the protective film 170 (FIG. 10B).
  • the base electrode 220 and the SiO 2 protective film 180 are formed, and the n + -SiC layer 140, the p-SiC layer 150, and the p + -SiC layer 160 are etched using the base electrode 220 and the SiO 2 protective film 180 as masks (FIG. 10C).
  • the emitter electrode 210 and the collector electrode 230 are formed (FIG. 10D).
  • the epitaxial growth is facilitated and the product yield can be increased as compared with a case wherein epitaxial growth is performed on the entire surface.
  • a transistor having a diamond layer having a size of 2 ⁇ m.sup. ⁇ had a very high current amplification factor, i.e., a current gain of 900.
  • the protective films 170 and 180 and the like are used as etching masks to form the electrodes, the number of masks in the fabrication process can be reduced, and the photolithographic process such as resist coating can be simplified. Error factors caused by mask alignment can be reduced, and a finer micropattern can be formed.
  • SiC is exemplified to have a cubic crystal structure.
  • SiC may have a hexagonal crystal structure (called 6H-SiC or ⁇ -Sic).
  • 6H-SiC has a band gap of 2.86 eV (band gap difference: 1.54 eV), and a higher voltage than that required for 3C-SiC is required, but heat resistance and collector breakdown can be improved.
  • FIG. 11 shows the structure of a transistor according to the third embodiment.
  • an p + -SiC layer 160, a p-SiC layer 150, an n + -SiC layer 140, a p-BP x N 1-x layer 132, and a p + -BP x N 1-x layer 122 are sequentially formed on a nondoped SiC substrate 111.
  • a collector electrode 230, a base electrode 220, and an emitter electrode 210 are formed on and electrically connected to the p + -SiC layer 160, the n + -SiC layer 140, and the p + -BP x N 1-x layer 122, respectively.
  • "x" in BP x N 1-x is set to 0.1 so that the lattice constant of BP x N 1-x becomes equal to that of SiC. Since these lattice constants are equal to each other, a fabrication advantage (i.e. , the layers 132 and 122 can be properly formed) can be obtained as compared with the fabrication of the transistor shown in FIG. 6.
  • SiC is defined herein to have a cubic crystal structure (3C-SiC or ⁇ -SiC).
  • This transistor is manufactured by the following steps.
  • the p + -SiC layer 160, the p-SiC layer 150, and the n + -SiC layer 140 are sequentially formed on the SiC substrate 111 by a low-pressure CVD method.
  • a source gas was a gas mixture of C 3 H 8 /SiHCl 2 at a mixing ratio of 1: 2, H 2 was used as a carrier gas, and the growth conditions were a pressure of 200 Pa and a temperature of 900° to 1,200° C.
  • PH 3 is mixed in the source gas to dope P (phosphorus).
  • B 2 H 6 is mixed in the source gas to dope B (boron) to grow the p-SiC layer 150 and the p + -SiC layer 160.
  • the p-BP x N 1-x layer 132 and the p + -BP x N 1-x layer 122 are sequentially formed by a thermal CVD method.
  • a source gas was a gas mixture of B 2 H 6 (e.g., 5%), PH 3 (e.g., 5%), NH 3 , and H 2 .
  • the layers were grown at a temperature of 800° to 1,100° C.
  • Zn is used as a p-type dopant
  • Zn (CH 3 ) 3 is mixed in the source gas
  • the content of Zn(CH 3 ) 3 is changed to grow the p + -BP x N 1-x layer 122 and the p-BP x N 1-x layer 132 (FIG. 12A).
  • Si is used as a p-type dopant
  • SiH 4 is mixed in the source gas.
  • the resultant structure is masked except for portions serving as the emitter and base regions, and the BP x N 1-x layers 122 and 132 are etched by RIBE (Reactive Ion Beam Etching) using a gas mixture of Ar+N 2 O (20%) (FIG. 12B). Thereafter, the p-SiC layer 150 and the n + -SiC layer 140 are etched by RIE (Reactive Ion Etching) using a reslist on the BP x N 1-x layers 122 and 132 as a mask (FIG. 12C). At thls time, the reaction gas is a gas mixture of CF 4 +O 2 (5%).
  • the AlSi emitter electrode 210, the TaSi base electrode 220, and the Mo/Au collector electrode 230 are formed and wlred (Flg. 12D).
  • This transistor is a pnp transistor having a heterojunction formed by p-type BP x N 1-x and n-type SiC.
  • the same advantage as in FIG. 6 is obtained except that the emitter consists of BP x N 1-x .
  • the p-BP x N 1-x layer 132 having a low carrier concentration is formed together with the heterojunction between the emitter and base.
  • the p-SiC layer 150 having a low carrier concentration is formed between the collector and base.
  • This transistor is operated using holes as a majority carrier and is estimated to have a band diagram shown in FIG. 13A.
  • the band gap of the emitter region is about 3.0 eV
  • the band gap of each of the base and collector regions is about 2.2 eV
  • a band gap difference of about 0.8 eV is present between the emitter and base.
  • FIG. 13B is a band diagram showing a state wherein the transistor is DC-biased.
  • electrons are distributed in a Fermi-Dirac distribution at a portion higher than the energy level of the lower end of the conduction band of the base region (n + -SiC layer 140).
  • the Fermi-Dirac distribution of holes is obtained at a portion higher than energy levels E V1 and E V2 of the upper end of the valence band.
  • the holes have a higher energy in a downward direction.
  • a DC bias operation will be described with reference to FIG. 13B.
  • the transistor is forward-biased such that the emitter has a positive voltage and the base has a negative voltage.
  • the energy level of the base region is higher than that of the emitter region.
  • forward biasing is performed such that the collector has a negative voltage, the energy level of the collector region becomes high.
  • Electrons as a minority carrier are injected from the base, but only a small number of electrons having an energy higher than the potential carrier of the emitter region flow to the emitter.
  • the potential barrier of the valence band is lowered by the heterojunction, and the potential barrier is also lowered by the bias. For this reason, most of the holes flow in the collector region through the base region. Therefore, a large collector current flows with a small base current, thereby obtaining a large current gain.
  • the transistor of this embodiment can be properly operated even at high temperatures although the band gaps are slightly narrowed at such high temperatures.
  • the device can be operated even at a high collector voltage.
  • This transistor of this embodiment is superior to a state-of-the-art transistor by properly selecting parameters such as a film thickness.
  • SiC having a high heat conductivity and a low dielectric constant is used as the material for the substrate, good heat dissipation properties can be obtained.
  • FIG. 14 shows the self-aligned structure of the transistor described above.
  • the base electrode 220 is self-aligned by an SiO 2 protective film 170 formed on the side wall of the BP x N 1-x layers i32 and 122.
  • an SiO 2 protective film 180 on the base electrode 220 is used to etch the collector region and form the collector electrode 230.
  • FIGS. 15A to 15D show the steps in manufacturing this transistor. The etching conditions are the same as those in the previous embodiment, and any other arrangement is the same as in FIG. 4.
  • the p + -SiC layer 160, the p-SiC layer 150, and the n + -SiC layer 140 are sequentially formed on the SiC substrate 111 following the same procedures as in FIG. 12A (FIG. 15A).
  • the resultant structure is masked except for a portion serving as an emitter region, and the p-BP x N 1-x layer 132 and the p + -BP x N 1-x layer 122 are formed by the selective growth described above, thereby forming the protective film 170 (FIG. 15B).
  • the base electrode 220 and the SiO 2 protective film 180 are formed, and the n + -SiC layer 140, the p-SiC layer 150, and the p + -SiC layer 160 are etched using the base electrode 220 and the SiO 2 protective film 180 as masks (FIG. 15C).
  • the emitter electrode 210 and the collector electrode 230 are formed (FIG. 15D). Epitaxial growth is facilitated and the product yield can be increased as compared with a case wherein epitaxial growth is performed on the entire surface.
  • the protective films 170 and 180 and the like are used as etching masks to form the electrodes, the number of masks in the fabrication process can be reduced, and the photolithographic process such as resist coating can be simplified. Error factors caused by mask alignment can be reduced, and a finer micropattern can be formed.
  • SiC is exemplified to have a cubic crystal structure.
  • SiC may have a hexagonal crystal structure (called 6H-SiC or ⁇ -Sic).
  • 6H-SiC has a band gap of 2.86 eV, and a higher voltage than that required for 3C-SiC is required, but heat resistance and collector breakdown can be improved.
  • a pnp transistor is exemplified, but the type of dopant is changed to obtain an npn transistor.
  • the value of x in BP x N 1-x is changed to change the band gap.
  • FIG. 16 shows the structure of a transistor formed on a cubic SiC (called 3C-SiC or ⁇ -SiC) substrate.
  • a p + -SiC layer 160 having a cubic crystal structure a p-SiC layer 150 having a cubic crystal structure, an n + -SiC layer 140 having a cubic crystal structure, a p-SiC layer 131 having a hexagonal crystal structure (called 6H-SiC or ⁇ -SiC), and a p + -SiC layer 121 having a hexagonal crystal structure are sequentially formed on a nondoped SiC substrate 111.
  • a collector electrode 230, a base electrode 220, and an emitter electrode 210 are formed on and electrically connected to the p + -SiC layer 160, the n + -SiC layer 140, and the p + -SiC layer 121, respectively.
  • cubic SiC is represented as 3CSiC
  • hexagonal SiC is represented by 6HSiC.
  • This transistor is manufactured by the following steps.
  • the p + -3CSiC layer 160, the p-3CSiC layer 150, and the n + -3CSiC layer 140 are sequentially formed on the 3CSiC substrate 111 by a low-pressure CVD method.
  • a source gas was a gas mixture of C 3 H 8 /SiHCl 2 at a mixing ratio of 1: 2, H 2 was used as a carrier gas, and the growth conditions were a pressure of 200 Pa and a temperature of 900° to 1,200° C.
  • PH 3 is mixed in the source gas to dope P (phosphorus).
  • B 2 H 6 is mixed in the source gas to dope B (boron) to grow the p-3CSiC layer 150 and the p + -3CSiC layer 160.
  • the p-6HSiC layer 131 and the p + -6HSiC layer 121 are sequentially formed by a thermal CVD method.
  • the p-6HSiC layer 131 and the p + -6HSiC layer 121 are formed in the same manner as in the p + -3CSiC layer 160 and the p-3CSiC layer 150 (FIG. 17A).
  • the resultant structure is masked except for portions serving as the emitter and base regions, and the 6HSiC layers 121 and 131 are etched byRIBE (Reactive Ion Beam Etching) using a gas mixture of Ar+N 2 O (20%) (FIG. 17B). Thereafter, the p-3CSiC layer 150 and the n + -3CSiC layer 140 are etched by RIE (Reactive Ion Etching) using a resist on the 6HSiC layers 121 and 131 as a mask (FIG. 17C). At this time, the reaction gas is a gas mixture of CF 4 +O 2 (5%).
  • the AlSi emitter electrode 210, the TaSi base electrode 220, and the Mo/Au collector electrode 230 are formed and wired (FIG. 17D).
  • This transistor is a pnp transistor having a heterojunction formed by p-type 6HSiC and n-type 3CSiC.
  • the p-6HSiC layer 131 having a low carrier concentration is formed together with the heterojunction between the emitter and base.
  • the p - -3CSiC layer 150 having a low carrier concentration is formed between the collector and base.
  • This transistor is operated using holes as a majority carrier and is estimated to have a band diagram shown in FIG. 18A.
  • the band gap of the emitter region is about 2.88 eV
  • the band gap of each of the base and collector regions is about 2.2 eV
  • a band gap difference of about 0.66 eV is present between the emitter and base.
  • FIG. 18B is a band diagram showing a state wherein the transistor is DC-biased.
  • electrons are distributed in a Fermi-Dirac distribution at a portion higher than the energy level of the lower end of the conduction band of the base region (n + -3CSiC layer 140 ).
  • the Fermi-Dirac distribution of holes is obtained at a portion higher than energy levels E V1 and E V2 of the upper end of the valence band.
  • the holes have a higher energy in a downward direction.
  • a DC biased operation will be described with reference to FIG. 18B.
  • the transistor is forward-biased such that the emitter has a positive voltage and the base has a negative voltage.
  • the energy level of the base region is higher than that of the emitter region.
  • forward biasing is performed such that the collector has a negative voltage, the energy level of the collector region becomes high.
  • Electrons as a minority carrier are injected from the base, but only a small number of electrons having an energy higher than the potential carrier of the emitter region flow to the emitter.
  • the potential barrier of the valence band is lowered by the heterojunction, and the potential barrier is also lowered by the bias. For this reason, most of the holes flow in the collector region through the base region.
  • the transistor of this embodiment can be properly operated even at high temperatures although the band gaps are slightly narrowed at such high temperatures.
  • the device can be operated even at a high collector voltage.
  • This transistor of this embodiment is superior to a state-of-the-art transistor by properly selecting parameters such as a film thickness.
  • 3CSiC having a high heat conductivity and a low dielectric constant is used as the material for the substrate, good heat dissipation properties can be obtained.
  • this transistor has a heterojunction using a single material as SiC. For this reason, as compared with other heterojunction transistors, extra materials are not required, and the fabrication process can be facilitated.
  • an npn transistor can be manufactured in addition to the pnp transistor, and the composition of the dopant can be controlled. Therefore, transistors having different impurity profiles can be formed. Transistors having various characteristics can be provided in a variety of applications.
  • FIG. 19 shows the self-aligned structure of the transistor in FIG. 16.
  • the base electrode 220 is self-aligned by an SiO 2 protective film 170 formed on the side wall of the 6HSiC layers 131 and 121.
  • an SiO 2 protective film 180 on the base electrode 220 is used to etch the collector region and form the collector electrode 230.
  • FIGS. 20A to 20D show the steps in manufacturing this transistor. These steps are performed under the same etching conditions as in the previous embodiment, and any other structure is the same as that in FIG. 4.
  • the p + -3CSiC layer 160, the p-3CSiC layer 150, and the n + -3CSiC layer 140 are sequentially formed on the 3CSiC substrate 111 following the same procedures as in FIG. 17A (FIG. 20A).
  • the resultant structure is masked except for a portion serving as an emitter region, and the p-6HSiC layer 131 and the p + -6HSiC layer 121 are formed by the selective growth described above, thereby forming the protective film 170 (FIG. 20B).
  • the base electrode 220 and the SiO 2 protective film 180 are formed, and the n + -3CSiC layer 140, the p-3CSiC layer 150, and the p + -3CSiC layer 160 are etched using the base electrode 220 and the SiO 2 protective film 180 as masks (FIG. 20C).
  • the emitter electrode 210 and the collector electrode 230 are formed (FIG. 20D). Since the protective films 170 and 180 and the like are used as etching masks to form the electrodes, the number of masks in the fabrication process can be reduced, and the photolithographic process such as resist coating can be simplified. Error factors caused by mask alignment can be reduced, and a finer micropattern can be formed.
  • the SiC substrate is exemplified to have a cubic crystal structure.
  • the SiC substrate may have a hexagonal crystal structure.
  • the emitter region (6HSiC layers 121 and 131), the base region (3CSiC layer 140), and the collector region (3CSiC layers 150 and 160) are formed in the order named.
  • the emitter region serves as a lower layer to facilitate wiring in an ECL (Emitter Coupled Logic).

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5624853A (en) * 1992-03-24 1997-04-29 Sumitomo Electric Industries, Ltd. Method for forming heterojunction bipolar transistors
US5847414A (en) * 1995-10-30 1998-12-08 Abb Research Limited Semiconductor device having a hetero-junction between SiC and a Group 3B-nitride
US5859447A (en) * 1997-05-09 1999-01-12 Yang; Edward S. Heterojunction bipolar transistor having heterostructure ballasting emitter
US5986287A (en) * 1995-09-08 1999-11-16 Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E. V. Semiconductor structure for a transistor
US20030234400A1 (en) * 2001-05-28 2003-12-25 Takashi Udagawa Semiconductor device, semiconductor layer and production method thereof
CN106784125A (zh) * 2016-12-08 2017-05-31 西安电子科技大学 Ga2O3/SiC异质结光电PNP晶体管及其制备方法
WO2018103645A1 (zh) * 2016-12-08 2018-06-14 西安电子科技大学 Ga2O3/SiC异质结NPN/PNP光电晶体管的制备方法
CN109244179A (zh) * 2018-08-10 2019-01-18 西安电子科技大学 基于金刚石/SiC异质结构的光电NPN晶体管及其制备方法
CN113140620A (zh) * 2021-04-13 2021-07-20 西安电子科技大学 宽禁带半导体BPN/GaN异质结材料及外延生长方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4440072C1 (de) * 1994-11-10 1996-02-22 Inst Halbleiterphysik Gmbh Verfahren zur Herstellung einer vergrabenen monokristallinen Siliziumcarbidschicht
US5939738A (en) * 1995-10-25 1999-08-17 Texas Instruments Incorporated Low base-resistance bipolar transistor
SE9801881D0 (sv) * 1998-05-28 1998-05-28 Asea Brown Boveri A switching device
SE9804135L (sv) 1998-11-30 2000-05-31 Abb Ab Fotokonduktiv omkopplare
JP2000277622A (ja) * 1999-01-18 2000-10-06 Sony Corp 半導体装置およびその製造方法
SE9901410D0 (sv) * 1999-04-21 1999-04-21 Abb Research Ltd Abipolar transistor
US6573565B2 (en) * 1999-07-28 2003-06-03 International Business Machines Corporation Method and structure for providing improved thermal conduction for silicon semiconductor devices
DE10005405A1 (de) * 2000-02-04 2001-08-09 Inst Halbleiterphysik Gmbh Schichtstapel für pnp-Heterobipolar-Transistor
DE10104776A1 (de) * 2001-02-02 2002-08-22 Infineon Technologies Ag Bipolartransistor und Verfahren zu dessen Herstellung
US7132701B1 (en) * 2001-07-27 2006-11-07 Fairchild Semiconductor Corporation Contact method for thin silicon carbide epitaxial layer and semiconductor devices formed by those methods

Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4097888A (en) * 1975-10-15 1978-06-27 Signetics Corporation High density collector-up structure
EP0125943A1 (de) * 1983-04-14 1984-11-21 Allied Corporation Bipolarer Transistor mit Heteroübergang Indiumphosphid-Borphosphid
JPS62159463A (ja) * 1986-01-08 1987-07-15 Fujitsu Ltd 半導体装置の製造方法
JPS62160760A (ja) * 1986-01-10 1987-07-16 Fujitsu Ltd 半導体装置の製造方法
JPS62216364A (ja) * 1986-03-18 1987-09-22 Fujitsu Ltd ヘテロ接合バイポ−ラトランジスタ
JPS62265762A (ja) * 1986-05-14 1987-11-18 Fujitsu Ltd 半導体装置
EP0282054A1 (de) * 1987-03-12 1988-09-14 Sumitomo Electric Industries Limited Dünnschicht-Einkristall-Diamantsubstrat
JPS6455862A (en) * 1987-08-26 1989-03-02 Sumitomo Electric Industries Heterojunction transistor and manufacture thereof
JPH01143261A (ja) * 1987-11-27 1989-06-05 Nec Corp 半導体装置
EP0379359A2 (de) * 1989-01-20 1990-07-25 Sumitomo Electric Industries, Ltd. Kompositmaterial
US4945394A (en) * 1987-10-26 1990-07-31 North Carolina State University Bipolar junction transistor on silicon carbide
US5006914A (en) * 1988-12-02 1991-04-09 Advanced Technology Materials, Inc. Single crystal semiconductor substrate articles and semiconductor devices comprising same
JPH0397275A (ja) * 1989-09-09 1991-04-23 Katsunobu Maeda 炭化硅素の青色発光ダイオード素子
US5043773A (en) * 1990-06-04 1991-08-27 Advanced Technology Materials, Inc. Wafer base for silicon carbide semiconductor devices, incorporating alloy substrates
US5117267A (en) * 1989-09-27 1992-05-26 Sumitomo Electric Industries, Ltd. Semiconductor heterojunction structure
US5144398A (en) * 1989-03-29 1992-09-01 Canon Kabushiki Kaisha Semiconductor device and photoelectric conversion apparatus using the same
US5164810A (en) * 1989-12-06 1992-11-17 General Motors Corporation Cubic boron nitride bipolar transistor
US5179070A (en) * 1988-04-30 1993-01-12 Sumitomo Electric Industries, Ltd. Semiconductor substrate having a superconducting thin film with a buffer layer in between
JPH0529331A (ja) * 1991-07-19 1993-02-05 Rohm Co Ltd ヘテロ接合バイポーラトランジスタ
US5247192A (en) * 1991-09-30 1993-09-21 Rohm Co., Ltd. Heterojunction bipolar transistor

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4985742A (en) * 1989-07-07 1991-01-15 University Of Colorado Foundation, Inc. High temperature semiconductor devices having at least one gallium nitride layer
JP2730271B2 (ja) * 1990-03-07 1998-03-25 住友電気工業株式会社 半導体装置
US5266819A (en) * 1991-05-13 1993-11-30 Rockwell International Corporation Self-aligned gallium arsenide/aluminum gallium arsenide collector-up heterojunction bipolar transistors capable of microwave applications and method
US5378921A (en) * 1991-10-21 1995-01-03 Rohm Co., Ltd. Heterojunction multicollector transistor
EP0562272A3 (en) * 1992-03-23 1994-05-25 Texas Instruments Inc Microwave heterojunction bipolar transistors with emitters designed for high power applications and method for fabricating same
EP0562549B1 (de) * 1992-03-24 1998-07-01 Sumitomo Electric Industries, Ltd. Heteroübergang-Bipolartransistor mit Siliziumkarbid
US5326992A (en) * 1992-07-29 1994-07-05 The United States Of America As Represented By The Secretary Of The Navy Silicon carbide and SiCAlN heterojunction bipolar transistor structures
US5272096A (en) * 1992-09-29 1993-12-21 Motorola, Inc. Method for making a bipolar transistor having a silicon carbide layer
US5285089A (en) * 1992-12-02 1994-02-08 Kobe Steel U.S.A., Inc. Diamond and silicon carbide heterojunction bipolar transistor
US5442199A (en) * 1993-05-14 1995-08-15 Kobe Steel Usa, Inc. Diamond hetero-junction rectifying element

Patent Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4097888A (en) * 1975-10-15 1978-06-27 Signetics Corporation High density collector-up structure
EP0125943A1 (de) * 1983-04-14 1984-11-21 Allied Corporation Bipolarer Transistor mit Heteroübergang Indiumphosphid-Borphosphid
JPS62159463A (ja) * 1986-01-08 1987-07-15 Fujitsu Ltd 半導体装置の製造方法
JPS62160760A (ja) * 1986-01-10 1987-07-16 Fujitsu Ltd 半導体装置の製造方法
JPS62216364A (ja) * 1986-03-18 1987-09-22 Fujitsu Ltd ヘテロ接合バイポ−ラトランジスタ
JPS62265762A (ja) * 1986-05-14 1987-11-18 Fujitsu Ltd 半導体装置
EP0282054A1 (de) * 1987-03-12 1988-09-14 Sumitomo Electric Industries Limited Dünnschicht-Einkristall-Diamantsubstrat
JPS6455862A (en) * 1987-08-26 1989-03-02 Sumitomo Electric Industries Heterojunction transistor and manufacture thereof
US4945394A (en) * 1987-10-26 1990-07-31 North Carolina State University Bipolar junction transistor on silicon carbide
JPH01143261A (ja) * 1987-11-27 1989-06-05 Nec Corp 半導体装置
US5179070A (en) * 1988-04-30 1993-01-12 Sumitomo Electric Industries, Ltd. Semiconductor substrate having a superconducting thin film with a buffer layer in between
US5006914A (en) * 1988-12-02 1991-04-09 Advanced Technology Materials, Inc. Single crystal semiconductor substrate articles and semiconductor devices comprising same
EP0379359A2 (de) * 1989-01-20 1990-07-25 Sumitomo Electric Industries, Ltd. Kompositmaterial
US5144398A (en) * 1989-03-29 1992-09-01 Canon Kabushiki Kaisha Semiconductor device and photoelectric conversion apparatus using the same
JPH0397275A (ja) * 1989-09-09 1991-04-23 Katsunobu Maeda 炭化硅素の青色発光ダイオード素子
US5117267A (en) * 1989-09-27 1992-05-26 Sumitomo Electric Industries, Ltd. Semiconductor heterojunction structure
US5164810A (en) * 1989-12-06 1992-11-17 General Motors Corporation Cubic boron nitride bipolar transistor
US5043773A (en) * 1990-06-04 1991-08-27 Advanced Technology Materials, Inc. Wafer base for silicon carbide semiconductor devices, incorporating alloy substrates
JPH0529331A (ja) * 1991-07-19 1993-02-05 Rohm Co Ltd ヘテロ接合バイポーラトランジスタ
US5247192A (en) * 1991-09-30 1993-09-21 Rohm Co., Ltd. Heterojunction bipolar transistor

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
Han Tzong Yuan et al, The Development of Heterojunction Integrated Injection Logic, IEEE Transactions on Electron Devices, vol. 36, No. 10, Oct. 1989, pp. 2083 2092. *
Han-Tzong Yuan et al, "The Development of Heterojunction Integrated Injection Logic," IEEE Transactions on Electron Devices, vol. 36, No. 10, Oct. 1989, pp. 2083-2092.
Hayama et al, "Fully Self-Aligned AlGaAs/GaAs HBT With AlGaGAs Passivation Layer," the Institute of Electronics and Information, Technical Report ED-89-147 (1989), pp. 68-69.
Hayama et al, Fully Self Aligned AlGaAs/GaAs HBT With AlGaGAs Passivation Layer, the Institute of Electronics and Information, Technical Report ED 89 147 (1989), pp. 68 69. *
K. Nagata et al, "Self-aligned AlGaAs/GaAs HBT With Low Emitter Resistance Utilizing InGaAs Cap Layer," IEEE Trans. Electron Devices, vol. ED-35, 1988, pp. 2-7.
K. Nagata et al, Self aligned AlGaAs/GaAs HBT With Low Emitter Resistance Utilizing InGaAs Cap Layer, IEEE Trans. Electron Devices, vol. ED 35, 1988, pp. 2 7. *
Morizuka et al, "AlGaAs/GaAs HBT's Fabricated by a Self-Alignment Technology Using Polyimide for Electrode Separation," IEEE Electron Device Letters, EDL-9, 598 (1988), pp. 268-270.
Morizuka et al, AlGaAs/GaAs HBT s Fabricated by a Self Alignment Technology Using Polyimide for Electrode Separation, IEEE Electron Device Letters, EDL 9, 598 (1988), pp. 268 270. *

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5624853A (en) * 1992-03-24 1997-04-29 Sumitomo Electric Industries, Ltd. Method for forming heterojunction bipolar transistors
US5986287A (en) * 1995-09-08 1999-11-16 Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E. V. Semiconductor structure for a transistor
US5847414A (en) * 1995-10-30 1998-12-08 Abb Research Limited Semiconductor device having a hetero-junction between SiC and a Group 3B-nitride
US5859447A (en) * 1997-05-09 1999-01-12 Yang; Edward S. Heterojunction bipolar transistor having heterostructure ballasting emitter
US7315050B2 (en) 2001-05-28 2008-01-01 Showa Denko K.K. Semiconductor device, semiconductor layer and production method thereof
US20070259510A1 (en) * 2001-05-28 2007-11-08 Showa A Denko K.K. Semiconductor device, semiconductor layer and production method thereof
US20030234400A1 (en) * 2001-05-28 2003-12-25 Takashi Udagawa Semiconductor device, semiconductor layer and production method thereof
US7622398B2 (en) 2001-05-28 2009-11-24 Showa Denko K.K. Semiconductor device, semiconductor layer and production method thereof
CN106784125A (zh) * 2016-12-08 2017-05-31 西安电子科技大学 Ga2O3/SiC异质结光电PNP晶体管及其制备方法
WO2018103645A1 (zh) * 2016-12-08 2018-06-14 西安电子科技大学 Ga2O3/SiC异质结NPN/PNP光电晶体管的制备方法
CN109244179A (zh) * 2018-08-10 2019-01-18 西安电子科技大学 基于金刚石/SiC异质结构的光电NPN晶体管及其制备方法
CN113140620A (zh) * 2021-04-13 2021-07-20 西安电子科技大学 宽禁带半导体BPN/GaN异质结材料及外延生长方法
CN113140620B (zh) * 2021-04-13 2022-12-02 西安电子科技大学 宽禁带半导体BPN/GaN异质结材料及外延生长方法

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