US20160240722A1 - System for improving solar cell manufacturing yield - Google Patents

System for improving solar cell manufacturing yield Download PDF

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US20160240722A1
US20160240722A1 US14/830,589 US201514830589A US2016240722A1 US 20160240722 A1 US20160240722 A1 US 20160240722A1 US 201514830589 A US201514830589 A US 201514830589A US 2016240722 A1 US2016240722 A1 US 2016240722A1
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microenvironment
processing station
layer
photovoltaic cell
substrate
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Jiunn Benjamin Heng
Chunguang Xiao
Dongzhi Yan
Jiansheng Zhou
Zhiquan Huang
Zheng Xu
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Silevo China Co Ltd
Silevo LLC
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Silevo China Co Ltd
Silevo LLC
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Assigned to SILEVO CHINA CO., LTD. reassignment SILEVO CHINA CO., LTD. CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 036561 FRAME: 0153. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Assignors: XIAO, CHUNGUANG, YAN, DONGZHI, ZHOU, JIANSHENG
Priority to CN201521007527.3U priority Critical patent/CN205752206U/zh
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Assigned to Sierra Solar Power (Hangzhou) Co., Ltd. reassignment Sierra Solar Power (Hangzhou) Co., Ltd. CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 036703 FRAME: 0037. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE ASSIGNMENT. Assignors: XIAO, CHUNGUANG, ZHOU, JIANSHENG, YAN, DONGZHI
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    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
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    • H02S50/00—Monitoring or testing of PV systems, e.g. load balancing or fault identification
    • H02S50/10—Testing of PV devices, e.g. of PV modules or single PV cells
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Definitions

  • This is generally related to the manufacture of photovoltaic cells. More specifically, this disclosure is related to a system for improving the yield of photovoltaic cell manufacture.
  • a photovoltaic cell converts light into electricity using the photovoltaic effect.
  • a typical single p-n junction structure includes a p-type doped layer and an n-type doped layer.
  • Photovoltaic cells with a single p-n junction can be homojunction photovoltaic cells or heterojunction photovoltaic cells. If both the p-doped and n-doped layers are made of similar materials (materials with equal bandgaps), the photovoltaic cell is called a homojunction photovoltaic cell.
  • a heterojunction photovoltaic cell includes at least two layers of materials of different bandgaps.
  • a p-i-n/n-i-p structure includes a p-type doped layer, an n-type doped layer, and an intrinsic (undoped) semiconductor layer (the i-layer) sandwiched between the p-layer and the n-layer.
  • a multi junction structure includes multiple single-junction structures of different bandgaps stacked on top of one another.
  • a photovoltaic cell In a photovoltaic cell, light is absorbed near the p-n junction generating carriers. The carriers diffuse into the p-n junction and are separated by the built-in electric field, thus producing an electrical current across the device and external circuitry.
  • An important metric in determining a photovoltaic cell's quality is its energy-conversion efficiency, which is defined as the ratio between power converted (from absorbed light to electrical energy) and power collected when the photovoltaic cell is connected to an electrical circuit.
  • FIG. 1 presents a diagram illustrating an exemplary SHJ photovoltaic cell (prior art).
  • SHJ photovoltaic cell 100 includes front grid electrode 102 , heavily doped amorphous-silicon (a-Si) emitter layer 104 , intrinsic a-Si layer 106 , crystalline-Si substrate 108 , and back grid electrode 110 .
  • Arrows in FIG. 1 indicate incident sunlight.
  • a-Si layer 106 can be used to reduce the surface recombination velocity by creating a barrier for minority carriers.
  • the a-Si layer 106 also passivates the surface of crystalline-Si layer 108 by repairing the existing Si dangling bonds.
  • the thickness of heavily doped a-Si emitter layer 104 can be much thinner compared to that of a homojunction photovoltaic cell.
  • SHJ photovoltaic cells can provide a higher efficiency with higher open-circuit voltage (V oc ) and larger short-circuit current (J sc ).
  • tunneling-based heterojunction devices can provide excellent open-circuit voltage (V oc ) from the combination of the field effect and surface passivation.
  • QTB quantum-tunneling barrier
  • the film quality of such ultra-thin QTB layers is very sensitive to environmental factors. Gaseous contaminants and moisture in the atmosphere can often cause degradation of the QTB layers and the corresponding junction structures, which leads to reduction of photovoltaic cell performance.
  • Conventional cleanroom technologies have been widely deployed in integrated circuit (IC) fabrication. However, the fabrication of photovoltaic cells can be different from conventional IC fabrication.
  • the throughput of photovoltaic cell manufacturing facilities in terms of the number of wafer processed, can often be much higher than that of IC manufacturing facilities.
  • the footprint of a high-throughput photovoltaic cell manufacturing facilities can also be significantly larger than that of an IC manufacturing facility.
  • the cost of implementing cleanroom capabilities throughout the entire photovoltaic cell fabrication facility can be prohibitively high.
  • a system for fabricating photovoltaic structures.
  • the system can include a photovoltaic cell enclosure that can connect a first processing station and a second processing station while providing a microenvironment for photovoltaic cells.
  • the microenvironment can be separated from a surrounding environment.
  • a microenvironment controller can control density of at least one chemical that could contaminate or react with an oxide layer on a photovoltaic cell, thereby protecting the photovoltaic cell between processes.
  • the system can include a monitor to monitor at least one microenvironment characteristic.
  • the characteristic can be a humidity parameter, a chemical density parameter, a particulate density parameter, or any combination thereof.
  • the microenvironment controller can include a particulate removal apparatus, a humidity controller apparatus, a chemical removal apparatus, or any combination thereof.
  • the microenvironment controller can maintain a relative humidity below 20%.
  • the microenvironment controller can remove, by 70% or more, NO x , NH 3 , SO x , H 2 S, volatile organic compound, or any combination thereof
  • the first processing station can be a wet processing station or a chemical vapor deposition tool.
  • the second processing station can be a chemical vapor deposition tool or a physical vapor deposition tool.
  • the system can also include a performance monitor apparatus to measure performance of a photovoltaic structure after the wafer of the photovoltaic structure is processed by the second processing station.
  • the wafer enclosure can be a room, a tunnel, or a container.
  • the microenvironment can be filled with at least one gas that does not react with the photovoltaic cell.
  • FIG. 1 shows an exemplary SHJ photovoltaic cell (prior art).
  • FIG. 2 shows an exemplary double-sided tunneling junction photovoltaic cell.
  • FIG. 3 shows an exemplary photovoltaic cell fabrication facility, according to an embodiment of the present invention.
  • FIG. 4 shows an exemplary photovoltaic cell fabrication facility, according to an embodiment of the present invention.
  • FIG. 5 shows an exemplary process of fabricating a photovoltaic cell, according to an embodiment of the present invention.
  • FIG. 6 shows the operation of an exemplary photovoltaic cell production line, according to an embodiment of the present invention.
  • FIG. 7 shows an exemplary process of fabricating a photovoltaic cell, according to an embodiment of the present invention.
  • FIG. 8 shows an exemplary facility for fabricating a photovoltaic cell, according to an embodiment of the present invention.
  • FIG. 9 shows an exemplary process of fabricating a photovoltaic cell, according to an embodiment of the present invention.
  • Embodiments of the present invention provide a system and method for improving the manufacturing yield of high-efficiency photovoltaic cells.
  • the microenvironment of locations where unfinished wafers are stored between processes can be carefully controlled to minimize degradation to the intermediate layers on the wafers.
  • One benefit, among others, of the present invention is that it provides a controlled microenvironment, which can be configured to be portable, to accommodate wafers between processes, thereby protecting vulnerable wafer surfaces from potential contamination and/or degradation.
  • the provision of such a microenvironment can support a large manufacturing throughput without requiring the entire facility or surrounding environment to be turned into a cleanroom or cleanroom-like environment, which can bring significant cost savings.
  • a portable microenvironment can be transported and assembled in such a way to accommodate a particular layout of a facility, thereby allowing for customizing the location where various process stations are deployed.
  • the portability of a microenvironment is also advantageous because as many of such microenvironments can be deployed overtime to accommodate a growing scale of production. In contract, a fixed cleanroom-like environment cannot accommodate an increase in the scale of production.
  • microenvironment described herein is a portion of the entire facility and surrounding environment, which may be regulated by a regular heating, ventilating and air conditioning (HVAC) system.
  • HVAC heating, ventilating and air conditioning
  • a conventional cleanroom typically has an entire facility under control and the surrounding environment is subject to a particular standard.
  • the microenvironment described herein can be portable. In other words, the microenvironment can be an enclosed space that can be moved from one place to another.
  • water-based air purifiers and gas phase chemical filters can be used to remove gaseous contaminants, such as SO x , H 2 S, NO x , NH 3 , volatile organic compounds (VOCs), etc., and other particulates from the microenvironment.
  • the air purification system can include a three-stage purification process: (1) mist wash to remove particulates and gross pollutants in the air, (2) dehumidification, and (3) chemical filtering to remove harmful chemicals in gas form.
  • the microenvironment can be implemented as an airtight nitrogen-filled cabinet, a room, or a tunnel between processing stations.
  • photovoltaic cell can refer to any photovoltaic structure capable of converting light energy to electrical energy.
  • Solar cells are one type of photovoltaic cells that are typically used to covert sunlight to electrical energy.
  • photovoltaic cell can refer to a completed cell, or an intermediary product that is not yet a finished product, such as a wafer.
  • FIG. 2 presents a diagram illustrating an exemplary double-sided tunneling junction photovoltaic cell.
  • Double-sided tunneling junction photovoltaic cell 200 can include base layer 202 , quantum tunneling barrier (QTB) layers 204 and 206 covering both surfaces of base layer 202 and passivating the surface-defect states, front-side doped a-Si layer forming front emitter 208 , backside doped a-Si layer forming a BSF layer 210 , front transparent conducting oxide (TCO) layer 212 , back TCO layer 214 , front metal grid 216 , and back metal grid 218 .
  • QTB quantum tunneling barrier
  • the main advantage of the tunneling junction is that the ultra-thin tunneling oxide layer deposited on either or both sides of the base layer enables a very low interface defect density (D it ), which can be less than 1 ⁇ 10 11 cm 2 , without significantly increasing the series resistance associated with tunneling through such an oxide layer. As a result, a high efficiency photovoltaic cell with open-circuit voltage (V oc ) that is larger than 715 mV can be achieved. Details, including fabrication methods, about double-sided tunneling junction photovoltaic cell 200 can be found in U.S. Pat. No. 8,686,283 (Attorney Docket No.
  • the emitter layer on the backside and a front surface field (FSF) layer on the front side of the photovoltaic cell can achieve a back junction photovoltaic cell with improved performance.
  • FSF front surface field
  • Placing the heavily p-type doped emitter (assuming that the base layer is n-type doped) on the backside of the photovoltaic cell can minimize current loss due to short wavelength absorption near the front surface of the photovoltaic cell.
  • the p-type doped emitter when placed on the backside, can be relatively thick to eliminate emitter depletion effects without compromising on current loss due to short wavelength absorption. As a result of the majority of carrier depletion being reduced, the cell's open-circuit voltage and fill factor is expected to improve.
  • the back junction structure also provides more flexibility to tune the p-type doped emitter's work function to better match the work function of the back TCO material, or allows the usage of a better optimized backside TCO material without being limited by its transmission properties.
  • the back junction is mostly impacted by long-wavelength, low-energy absorption, it is less affected by high-energy, excessive carrier recombination at the junction. Details, including fabrication methods, about a back junction photovoltaic cell with tunnel oxide can be found in U.S.
  • the c-Si wafer When manufacturing crystalline silicon (c-Si) based photovoltaic cells, the c-Si wafer typically undergoes a wet process first, which can include surface cleaning and texturizing.
  • the ultra-thin QTB layers that passivate the surfaces of the c-Si substrate can be formed via a dry oxidation process inside a furnace, plasma enhanced chemical deposition (PECVD) deposition, chemical oxidation, steam oxidation, or low pressure radical oxidation (LPRO), among others.
  • PECVD plasma enhanced chemical deposition
  • LPRO low pressure radical oxidation
  • a mono-atomic layer of SiO 2 or SiO can be formed by a furnace-based dry oxidation process or PECVD process on the surface of a c-Si wafer.
  • the crystalline silicon wafer can undergo a hot water bath, as part of the wet process, to form a thin layer of silicon oxide on both surfaces of the wafer.
  • a hot water bath can be conducted in de-ionized water with a temperature ranging from 60° C. to 90° C. The duration of the bath can be determined based on the desired thickness of the tunneling oxide layer.
  • a thin layer (approximately 10 angstroms thick) of intrinsic semiconductor (which can be amorphous) may also be deposited or formed on the c-Si wafer or the tunneling oxide layers to act as QTB layers.
  • Such a thin layer of oxide and/or intrinsic semiconductor is very fragile and its integrity can be damaged by contaminants or moisture in the environment.
  • c-Si wafers after each processing step can be kept in a wafer-holding area to dry off and/or to wait for subsequent processing, such as dry oxidation, chemical vapor deposition (CVD), or physical vapor deposition (PVD).
  • a wafer-holding area is conventionally an open space within the photovoltaic cell fabrication facility.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • the waiting time may vary for c-Si wafers emerging from the same wet process. It has been observed that the differences in waiting time (meaning that the wafers have been exposed to the contaminants in the environment for different time periods) before the CVD process can result in performance differences of the fabricated photovoltaic cells, while some photovoltaic cells fail to meet the efficiency requirement. In other words, the yield of the photovoltaic cell production line can be compromised. Hence, as the wafers are kept in the wafer-holding area for longer periods of time, the efficiency of the final products can be worsened. This problem could be more prominent when larger wafers (such as 6-inch wafers instead of 5-inch wafers) are used for photovoltaic cell fabrication.
  • Such performance degradation is partially caused by the various contaminants in the atmosphere attacking various layers exposed to the environment between difference processes, such as the surface of cleaned c-Si wafer, the thin QTB layer, or the emitter/surface field layer, causing degradation in passivation or junction quality.
  • most large-scale photovoltaic cell fabrication facilities lack sufficient environmental control due to their size. It is not practical to build a sufficiently large cleanroom to house a large-scale photovoltaic cell production line.
  • embodiments of the present invention provide a method and system that facilitate controlled microenvironments between processing stations such that silicon wafers can remain in the controlled microenvironments while waiting for the next process.
  • the controlled microenvironment can be substantially segregated, either by physical boundaries or by flows of a purge gas, from the larger environment of the fabrication facility. Particulates, moisture, and gaseous contaminants can be removed from the controlled microenvironment to prevent environmental damage to the photovoltaic cell junctions.
  • the controlled microenvironment can be implemented as an airtight, nitrogen-filled cabinet, a separate room whose temperature, humidity, chemical content, and particle content are closely monitored and controlled, or an airtight nitrogen-filled tunnel.
  • a specially designed room located within the photovoltaic cell fabrication facility can be used for holding the wafers while they are waiting for the next process.
  • the dry room may house the CVD tool and provide sufficient space for holding wafers waiting for the CVD process or between difference CVD processes. Wafers emerging from the previous process, such as a wet process that cleans and etches the c-Si wafers, can be immediately placed into the dry room with minimum exposure to the larger environment.
  • HEPA filters which provide cleanliness between class 1000 and class 10,000
  • water-based air purifiers, dehumidifiers, and chemical filters are installed in the dry room to remove gaseous contaminants, such as NO x , NH 3 , SO x , H 2 S, VOCs, etc.
  • the system can include a three-stage purification mechanism, which includes a mist-based washing module to remove particulates and pollutants, a dehumidifier, and a chemical filtering module.
  • the chemical removal efficiency of the chemical filters is maintained at above 70%, preferably at above 80%, and more preferably at above 95%.
  • Temperature and humidity are carefully controlled to desired levels within the dry room to prevent damage to the passivation layers caused by excessive moisture.
  • the temperature of the dry room is kept between 15 and 27° C., preferably at 23° C., and the absolute humidity is kept below 5 g/kg, preferably between 1.3 and 4.0 g/kg.
  • the relative humidity is maintained below 20%, preferably at 13 ⁇ 5%.
  • other smaller, physically enclosed wafer-holding apparatus or wafer enclosures such as airtight, enclosed carts and cabinets, can be placed within the dry room to further reduce possible contamination to the photovoltaic cell junctions/passivation layers.
  • these wafer enclosures can be filled with at least one type of gas that does not react with the surface of the photovoltaic structure (e.g., thin silicon oxide layer or intrinsic crystalline or amorphous silicon layer), such as purified nitrogen gas (N 2 ), to ensure greater environmental control.
  • the purified N 2 can have a purity of at least 99.9%, preferably around 99.95%.
  • the cleanliness within the carts/cabinets is kept at class 100.
  • the amount of O 2 is kept below 300 parts per million (ppm), and the amount of moisture or water vapor is kept at below 1000 ppm, preferably below 100 ppm.
  • the pressure within the carts/cabinet can be kept between 700 and 800 Torr. In one embodiment, the pressure can be at 760-770 Torr, so that the air flow can be reduced when the wafers are transported in and out of the carts/cabinet.
  • the carts and cabinets can be made of chemical-resistance materials, such as polyvinyl chloride (PVC) and/or stainless steel. In addition to keeping these carts or cabinets in the dry room, it is also possible to place them in the larger, generic environment. For example, one can place such carts or cabinets next to the wet station.
  • wafers can be immediately loaded into the enclosed carts or cabinets to ensure that exposure to the larger, surrounding environment is kept to a minimum. Subsequently, the carts or cabinets can be transported to the next processing station to allow wafers to be loaded directly into the next processing station from the enclosed, controlled environment.
  • the wafers waiting for further processing can also be placed in a tunnel that connects two processing stations.
  • the tunnel can be airtight, and may be equipped with a conveyor belt and entry/exit load lock chambers. Wafers finishing the first process (such as a wet process) can be loaded into the tunnel, often by robotic arms, through the entry load lock chamber, and are transported by the conveyor belt to the next processing station.
  • the exit of the tunnel may be the load lock chamber of the deposition or processing tool.
  • wafers can enter the next-stage tool directly from the tunnel without any exposure to the larger environment.
  • the tunnel is filled with purified N 2 that has a purity of at least 99.9%, preferably around 99.95%. Other environmental control factors in the tunnel are similar to the ones used in the cart/cabinet.
  • FIG. 3 shows an exemplary photovoltaic cell fabrication facility, according to an embodiment of the present invention.
  • photovoltaic cell fabrication facility 300 includes various processing stations for fabricating a photovoltaic cells, such as wet station 302 and dry station 304 .
  • Photovoltaic cell fabrication facility 300 can also include one or more wafer-holding areas where the wafers are temporarily stored while waiting for the next process, such as wafer-holding area 306 .
  • Photovoltaic cell fabrication facility 300 can include any industrial-sized room or building for fabrication of photovoltaic cells. In some embodiments, photovoltaic cell fabrication facility 300 can be well over 10,000 sq. ft.
  • Wet station 302 can be used to perform any process that involves a solution, including but not limited to: surface cleaning, surface texturization, wet etching, and steam oxidation.
  • Dry station 304 can include one or more tools that can be used to perform any process that does not involve a solution, including but not limited to: an oxidation tool (such as a furnace-based dry oxidation tool, a CVD tool, or an LPRO tool), one or more emitter/surface-field-layer tools (such as a plasma-enhanced chemical vapor deposition (PECVD) tool), a transparent conductive oxide (TCO) layer tool (such as an electron-beam evaporation tool or a sputtering tool), a dry-etching tool, etc.
  • an oxidation tool such as a furnace-based dry oxidation tool, a CVD tool, or an LPRO tool
  • one or more emitter/surface-field-layer tools such as a plasma-enhanced chemical vapor deposition (PECVD) tool
  • TCO transparent conductive oxide
  • dry station 304 is used for forming the tunneling layer, the photovoltaic cell emitter layer, the surface field layer, and the TCO layers,
  • Wafer-holding area 306 can be used to temporarily store silicon wafers that have been processed at wet station 302 and are queuing to be processed in dry station 304 .
  • silicon wafers with an ultra-thin oxide layer on one or both sides of the wafers may be placed in wafer-holding area 306 to wait for subsequent CVD processes to deposit the emitter layer and surface field layer.
  • silicon wafers can be placed in cassettes, such as cassette 308 . Multiple cassettes may be placed side-by-side or stacked on top of each other. Note that FIG. 3 shows that the silicon wafers are placed vertically in the cassettes.
  • the cassettes may be placed in such a way that silicon wafers are substantially horizontally oriented.
  • the wafer-holding areas can typically be in the larger environment of the fabrication facility, which can include various contaminants, such as moisture, particulates, and chemical vapors.
  • Some smaller-scale photovoltaic cell facility may place the production line in a cleanroom.
  • most cleanroom standards do not limit the amount of non-particulate contamination within the cleanroom, and HEPA/ULPA filters are ineffective in removing non-particulate contaminants.
  • certain airborne contaminants such as SO x , NO x , NH 3 , water vapor, ozone, VOCs, etc.
  • included in the cleanroom air can come in contact with the ultra-thin oxide/intrinsic semiconductor layer on one or both sides of the silicon wafers and may damage such an ultra-thin oxide/intrinsic semiconductor layer, thus degrading the passivation.
  • the final products may exhibit lower efficiency.
  • the microenvironment within or surrounding wafer-holding area 306 is controlled to prevent contamination to the intermediate layers on the photovoltaic cells.
  • wafer-holding area 306 and dry station 304 both reside in a dry room 310 , which has its own microenvironment that is segregated from the larger, surrounding environment of fabrication facility 300 .
  • Dry room 310 can include a number of environment-control modules, including but not limited to: particulate filtering module 312 , temperature and humidity control module 314 , and non-particulate filtering module 316 .
  • Particulate filtering module 312 can remove particles from dry room 310 .
  • particulate filtering module 312 can include a HEPA filter or an ULPA filter, and a mist-wash module.
  • dry room 310 can be kept as a class 1000 or a class 10,000 cleanroom with positive pressure maintained in the room.
  • Non-particulate filtering module 314 can remove gas phase contaminants, such as SO x , NO x , H 2 S, NH 3 , ozone, VOCs, etc., from dry room 310 .
  • Temperature and humidity control module 314 can control the temperature and humidity within dry room 310 to a desired level.
  • the temperature of the room can be maintained between 15-27° C., preferably at 23° C.
  • the relative humidity can be maintained below 20%, preferably at 13 ⁇ 5%.
  • the absolute humidity can be maintained below 5 g/Kg, preferably at 1.3-4.0 g/Kg.
  • Non-particulate filtering module 316 may include various types chemical filters.
  • the chemical removal efficiency is maintained at above 70% (meaning that over 70% of the targeted chemicals can be removed), preferably at above 80%, and more preferably at above 95%.
  • wafer-holding area 306 can be an open area located in dry room 310 .
  • wafer-holding area 306 can include airtight, enclosed carts and/or cabinets, which can be wheeled or otherwise transported from wet station 302 to dry station 304 .
  • the controlled microenvironment can be made portable and allowed to move within facility 300 .
  • the carts or cabinets can be made with chemical-resistant materials, such as PVC or stainless steel.
  • the enclosed carts or cabinets can be filled with purified N 2 with a purity of at least 99.9%, preferably around 99.95%.
  • the pressure of nitrogen within the carts/cabinets can be maintained at 700-800 Torr, preferably at 760-770 Torr.
  • the level of particulate within the carts/cabinets can be kept at class 100 or better.
  • Other environmental factors, such as oxygen level, temperature, and humidity, can also be controlled within the carts/cabinets.
  • the oxygen level can be maintained at below 300 ppm.
  • the temperature can be maintained between 15-27° C., preferably at 25° C.
  • the moisture (H 2 O vapor) level can be maintained below 1000 ppm, preferably below 100 ppm.
  • wet station 302 can be connected to wafer-holding area 306 via an air-tight, optionally nitrogen-filled tunnel 303 , which can be controlled with a similar set of parameters as an airtight cart or cabinet.
  • FIG. 4 shows an exemplary photovoltaic cell fabrication facility, in accordance with an embodiment of the present invention.
  • photovoltaic cell fabrication facility 400 can include a number of processing tools, such as wet station 402 , CVD tool 404 , CVD tool 406 , and PVD tool 408 .
  • Wet station 402 can include various baths or rinses that can be used for surface cleaning, surface texturization, passivation, and oxidation. Multiple silicon wafers can be placed in a cassette that is placed in the bath or under the rinse for batch processing.
  • CVD tool 404 can be used for material deposition on a first side of the silicon wafers (for example, for forming a tunneling layer and/or subsequently depositing the emitter layer).
  • CVD tool 406 can be used for material deposition on a second side of the silicon wafers (for example, for forming a second tunneling layer and/or subsequently depositing the surface field layer).
  • PVD station 408 can be used for the deposition of a TCO layer on one or both sides of the wafers.
  • each processing tool can include an enclosed load/unload area where silicon wafers (in cassettes or other types of carriers) are loaded into or unloaded from the processing tool.
  • These load/unload areas are also known as buffers between the processing tool and the larger environment of fabrication facility 400 .
  • wet station 402 can include a load/unload buffer 412
  • CVD tool 404 includes a load/unload buffer 414 .
  • load/unload buffers may include physically enclosed space, such as an airtight chamber or cabinet.
  • the load/unload buffers can be built with chemical-resistant materials, such as PVC or stainless steel.
  • the buffers (such as a chamber or a cabinet) can be filled with purified N 2 with a purity of at least 99.9%, preferably around 99.95%.
  • the pressure of nitrogen within the chamber/cabinet can be maintained at 700-800 Torr, preferably at 760-770 Torr.
  • the level of particulate within the chamber/cabinet can be kept at class 100 or better.
  • Other environmental factors, such as oxygen level, temperature, and humidity, can be controlled within the chamber/cabinet.
  • the oxygen level can be maintained below 300 ppm.
  • the temperature can be maintained between 15-27° C., preferably at 25° C.
  • the moisture (H 2 O vapor) level can be maintained below 1000 ppm, preferably below 100 ppm.
  • the load/unload buffers can be moved between the process stations, hence allowing the wafers to stay protected during such transportation.
  • a tunnel can be placed between the load/unload buffers of the different tools.
  • a tunnel 422 is placed between buffer 412 of wet station 402 and buffer 414 of CVD tool 404 .
  • wafers that have been processed by wet station 402 can be transported to CVD tool 404 via tunnel 422 , and are not exposed to the larger environment of fabrication facility 400 during transportation.
  • wafers can also be kept within tunnel 422 while waiting for the CVD process.
  • the microenvironment within the tunnel is similar to the ones in the load/unload buffers.
  • the tunnels are built with chemical-resistant materials, such as PVC or stainless steel.
  • the tunnels can be filled with purified N 2 with a purity of at least 99.9%, preferably around 99.95%.
  • the pressure of nitrogen within the tunnels can be maintained at 700-800 Torr, preferably at 760-770 Torr.
  • the level of particulate within the tunnels can be kept at class 100 or better.
  • Other environmental factors, such as oxygen level, temperature, and humidity, can be controlled within the tunnels.
  • the oxygen level can be maintained at below 300 ppm.
  • the temperature can be maintained between 15-27° C., preferably at 25° C.
  • the moisture (H 2 O vapor) level can be maintained at below 1000 ppm, preferably below 100 ppm. It is also to use a combination of portable wafer enclosures and tunnels.
  • portable wafer enclosures such as air tight carts or cabinets can be used to transport wafers from wet station 402 and CVD tool 404 , and one or more tunnels can be used between CVD tools 404 and 406 .
  • photovoltaic cell fabrication facility 400 includes two CVD tools for back-to-back deposition of both sides of the wafers. Because standard CVD tools already have load lock chambers, it is possible to build a tunnel that connects the load lock chambers of the two CVD tools such that wafers finishing processing at CVD tool 404 are transported to CVD tool 406 via tunnel 424 without being exposed to the larger environment. Additional N 2 -filled buffers can also be built around each CVD tool, in case a CVD tool is temporarily offline.
  • FIG. 5 shows an exemplary process of fabricating a photovoltaic cell, according to an embodiment of the present invention.
  • SG-Si substrate 500 is prepared.
  • the thickness of SG-Si substrate 500 can range between 80 and 500 ⁇ m. In one embodiment, the thickness of SG-Si substrate 500 can be between 90 and 120 ⁇ m.
  • the resistivity of SG-Si substrate 500 is typically in, but not limited to, the range between 1 ⁇ cm and 10 ⁇ cm. In one embodiment, SG-Si substrate 500 has a resistivity between 1 ⁇ cm and 2 ⁇ cm.
  • the preparation operation can include saw damage etching that removes approximately 10 ⁇ m of silicon and surface texturing.
  • the surface texture can have various patterns, including but not limited to: hexagonal-pyramid, inverted pyramid, cylinder, cone, ring, and other irregular shapes.
  • the surface texturing operation results in a random pyramid textured surface. Afterwards, SG-Si substrate 500 goes through extensive surface cleaning. Note that in FIG. 5 the texture pattern is not drawn to the actual scale and is enlarged to illustrate the texture. Actual texture pattern would be much smaller compared with the surface dimensions. Note that operation 5 A may include one or more wet process, such as texturization and rinse.
  • a thin layer of high-quality (with D it less than 1 ⁇ 10 11 /cm 2 ) dielectric material is formed or deposited on the front and back surfaces of SG-Si substrate 500 to form front and back passivation/tunneling layers 502 and 504 , respectively.
  • D it less than 1 ⁇ 10 11 /cm 2 dielectric material
  • Various types of dielectric materials can be used to form the passivation/tunneling layers, including, but not limited to: silicon oxide (SiO x ), hydrogenated SiO x , silicon nitride (SiN x ), hydrogenated SiN x , aluminum oxide (AlO x ), silicon oxynitride (SiON), and hydrogenated SiON.
  • various oxidation and/or deposition techniques can be used to form the passivation/tunneling layers, including, but not limited to: thermal oxidation, atomic layer deposition, wet or steam oxidation, low-pressure radical oxidation, plasma-enhanced chemical-vapor deposition (PECVD), LPRO, etc.
  • the thickness of passivation/tunneling layers 502 and 504 can be between 1 and 50 angstroms. In one embodiment, the thickness of passivation/tunneling layers 502 and 504 is between 1 and 15 angstroms. Note that the well-controlled thickness of the passivation/tunneling layers ensures good tunneling and passivation effects.
  • the unfinished wafer is placed into an ultra-clean microenvironment that is substantially segregated from the surrounding environment of the photovoltaic cell fabrication facility.
  • the environmental factors such as particulate count, temperature, humidity, pressure, etc., can be controlled in the microenvironment.
  • gaseous contaminants such as SO x , NO x , NH 3 , H 2 S, ozone, VOCs, can be substantially removed from the microenvironment to ensure the integrity of passivation/tunneling layers.
  • the unfinished photovoltaic cells are kept in the ultra-clean, controlled microenvironment until the next operation. Note that if operation 5 B is a dry process, the wafer can be placed in the ultra-clean microenvironment subsequent to operation 5 A.
  • a layer of hydrogenated, graded-doping a-Si having a doping type opposite to that of substrate 500 can be deposited on the surface of back passivation/tunneling layer 504 to form an emitter layer 506 .
  • emitter layer 506 is positioned on the backside of the photovoltaic cell facing away from the incident sunlight. Note that, if c-Si substrate 500 is n-type doped, then emitter layer 506 is p-type doped, and vice versa.
  • emitter layer 506 can be p-type doped using boron as dopant and can be formed using a CVD technique, such as PECVD.
  • SG-Si substrate 500 , back passivation/tunneling layer 504 , and emitter layer 506 form the hetero-tunneling back junction.
  • the thickness of emitter layer 506 can be between 1 and 20 nm. Note that an optimally doped (with doping concentration varying between 1 ⁇ 10 15 /cm 3 and 5 ⁇ 10 20 /cm 3 ) and sufficiently thick (at least between 3 nm and 20 nm) emitter layer can ensure a good ohmic contact and a large built-in potential.
  • the region within emitter layer 506 that is adjacent to back passivation/tunneling layer 504 can have a lower doping concentration, and the region that is away from back passivation/tunneling layer 504 can have a higher doping concentration.
  • the lower doping concentration can reduce defect density at the interface between back passivation/tunneling layer 504 and emitter layer 506 , and the higher concentration on the other side can prevent emitter layer depletion.
  • the work function of emitter layer 506 can be tuned to better match that of a subsequently deposited back transparent conductive oxide (TCO) layer to enable larger V oc and a higher fill factor.
  • TCO transparent conductive oxide
  • emitter layer 506 In addition to a-Si, it is also possible to use other material, including but not limited to: one or more wide-bandgap semiconductor materials and polycrystalline Si, to form emitter layer 506 . Subsequent to operation 5 C, the unfinished photovoltaic cell is placed into an ultra-clean microenvironment to wait for the next operation.
  • a layer of hydrogenated, graded-doping a-Si having a doping type same as that of substrate 500 can be deposited on the surface of front passivation/tunneling layers 502 to form front surface field (FSF) layer 508 .
  • FSF front surface field
  • c-Si substrate 500 is n-type doped
  • FSF layer 508 is also n-type doped, and vise versa.
  • FSF layer 508 is n-type doped using phosphorous as dopant.
  • FSF layer 508 can be formed using a CVD technique, such as PECVD.
  • C-Si substrate 500 , front passivation/tunneling layer 502 , and FSF layer 508 form the front surface tunneling junction that effectively passivates the front surface.
  • the thickness of FSF layer 508 can be between 1 and 30 nm.
  • the doping concentration of FSF layer 508 can vary from 1 ⁇ 10 15 /cm 3 to 5 ⁇ 10 20 /cm 3 .
  • the unfinished photovoltaic cell is optionally placed into an ultra-clean microenvironment to wait for the next operation.
  • the photovoltaic cell although not yet finished, is less sensitive to environmental factors. Therefore, placing and keeping the unfinished photovoltaic cells in the ultra-clean microenvironment can be optional after operation 5 D.
  • a layer of TCO material can be deposited on the surface of emitter layer 506 to form a back-side conductive anti-reflection layer 510 , which ensures a good ohmic contact.
  • TCO include, but are not limited to: indium-titanium-oxide (ITiO), indium oxide (In 2 O 3 ), indium-tungsten-oxide (IWO), indium-tin-oxide (ITO), indium-zinc-oxide (IZO), tin-oxide (SnO x ), aluminum doped zinc-oxide (ZnO:Al or AZO), Zn—In—O (ZIO), gallium doped zinc-oxide (ZnO:Ga), and other large bandgap transparent conducting oxide materials.
  • the work function of back-side TCO layer 510 can be tuned to better match that of emitter layer 506 .
  • a sputtering technique is used to form back-side TCO layer 510 .
  • front-side TCO layer 512 which can have a similar material composition as back-side TCO layer 510 , is formed on the surface of FSF layer 508 .
  • Front-side TCO layer 512 forms a good anti-reflection coating to allow maximum transmission of sunlight into the photovoltaic cell. Note that operation 5 E and 5 F can occur with the same PVD process, or can occur with two separate sputtering processes, using the same or different TCO materials.
  • front-side electrode 514 and back-side electrode 516 are formed on the surfaces of TCO layers 512 and 510 , respectively.
  • front-side electrode 514 and back-side electrode 516 include metal grids, wherein the metal can include Cu, Ag, Al, Au, or any conductive material.
  • the conductive grid can be formed using various techniques, including, but not limited to: electroplating, screen printing of a metal paste, inkjet or aerosol printing of a conductive ink, and evaporation.
  • front-side electrode 514 and/or back-side electrode 516 can include Cu grid formed using various techniques, including, but not limited to: electroless plating, electro plating, sputtering, and evaporation.
  • the existence of the back-side TCO layer and the fact that the back-side electrode includes a metal gird make it possible for the fabricated photovoltaic cell to operate in a bi-facial manner, i.e., to receive light from both the front and the back side.
  • FIG. 5 is based on a back-heterojunction device structure
  • embodiments of the present invention can be applied to various, different device structures, such as photovoltaic cells whose emitter is on the front side, or photovoltaic cells whose electrodes of both polarities are on the back side (i.e., with an interdigitated backside contacts, IBC).
  • IBC interdigitated backside contacts
  • FIG. 5 shows that the fabrication of photovoltaic cell follows the order of “center to surface”. In other words, the fabrication starts from the central base layer, and other layers are deposited one by one on both sides of base layer.
  • the advantage of such an arrangement is that the junctions on both sides can be formed sequentially without any intermediate steps in between. Once the junctions are formed, the photovoltaic cell becomes more robust and is less likely to degrade due to environment factors, thus making subsequent fabrication operations simpler.
  • the advantage of such an arrangement is that the wafer only needs to be flipped one time. However, strict control of the microenvironments where the photovoltaic cell is transported and held between fabrication operations is needed for most of the operations, because the junctions are not completed until near the end.
  • FIG. 6 shows the operation of an exemplary photovoltaic cell production line, according to one embodiment of the present invention.
  • a number of photovoltaic cell wafers can be first loaded into a cassette (operation 602 ).
  • the photovoltaic cell wafers include 6 inch by 6 inch square silicon wafers or 6 inch by 6 inch pseudo square (such as squares with rounded corners) silicon wafers.
  • the cassette can undergo one or more wet processes (operation 604 ).
  • the cassette may be dipped into one or more baths or go through one or more rinses.
  • the cassette (along with wafers within) is placed into a load/unload buffer (operation 606 ).
  • the load/unload buffer can include a chamber or a cabinet that is airtight and filled with purified N 2 .
  • the microenvironment within the load/unload buffer can be controlled to ensure that the wafers do not come into contact with various contaminants, including but not limited to: dust particles, harmful chemical vapors, aerosols, moisture, VOCs, etc., that may exist in the larger environment of the fabrication facility.
  • the cassette can be kept in the load/unload buffer until it is time for the next process, at which point the cassette is transported from the load/unload buffer from the wet station to the load/unload buffer of the next processing station, which can be an oxidation tool or CVD tool (operation 608 ).
  • the cassette can be transported via an enclosed tunnel connecting the two load/unload buffers.
  • the cassette can be transported via a N 2 -filled cart.
  • wafers are loaded from the cassette into the processing tool (operation 610 ).
  • the processing tool can be located in a room separated from the rest of the fabrication facility.
  • the microenvironment within this separated room can be controlled to remove various contaminants, including but not limited to: dust particles, harmful chemical vapors, aerosols, moisture, VOCs, etc., that may exist in the larger environment of the fabrication facility.
  • various contaminants including but not limited to: dust particles, harmful chemical vapors, aerosols, moisture, VOCs, etc.
  • the wafers can undergo a material formation or deposition process, such as an oxidation or CVD process (operation 612 ). After the deposition process, if the junctions or the layer structure are not yet completed, the wafers are loaded into another buffer to wait for the next process (operation 614 ).
  • Operations 608 - 614 may repeat until all layers, including the emitter layer, the field surface layer, and the front and back TCO layers are formed (operation 616 ).
  • the photovoltaic cells are then ready for metallization (operation 618 ). Note that the combination of the tunneling junction structure and the carefully controlled wafer loading/transport microenvironments within the photovoltaic cell fabrication facility ensures that the large-scale photovoltaic cell production line can manufacture photovoltaic cells with an efficiency of at least 20% at a high yield.
  • FIG. 7 shows such an exemplary method, according to one embodiment of the present invention.
  • SG-Si wafer 700 is prepared, similar to operation 5 A.
  • This preparation operation can include saw damage etching that removes approximately 10 ⁇ m of silicon and surface texturing.
  • the surface texturing operation results in a random pyramid textured surface.
  • SG-Si wafer 700 goes through extensive surface cleaning.
  • the texture pattern is not drawn to the actual scale and is enlarged to illustrate the texture. Actual texture pattern would be much smaller compared with the surface dimensions.
  • operation 7 A may include one or more wet processes.
  • thin tunneling oxide layers 702 and 704 can be formed on the front and back surfaces of SG-Si substrate 700 , respectively.
  • oxide layers 702 and 704 are formed by immerging wafer 700 in heated de-ionized water.
  • the temperature of the de-ionized water can be from 60° C. to 90° C.
  • the duration of the hot water bath can be selected such that the tunneling oxide layers 702 and 704 are between 1 and 50 angstroms.
  • the thickness of tunneling oxide layers 702 and 704 is between 1 and 15 angstroms.
  • wafer 700 is retained in a controlled microenvironment that can protect the surfaces of wafer 700 from potential contamination and/or reaction with the chemicals in the air.
  • the environmental factors such as particulate count, temperature, humidity, pressure, etc., can be controlled in the microenvironment.
  • Gaseous contaminants such as SO x , NO x , NH 3 , H 2 S, ozone, VOCs, can be substantially removed from the microenvironment to ensure the integrity of tunneling layers.
  • the microenvironment can be a room, cart, cabinet, or a tunnel. Other types of wafer enclosures are also possible.
  • doped a-Si emitter layer 706 having a doping type opposite to that of substrate 700 can be deposited on the surface of back passivation/tunneling layer 704 .
  • c-Si wafer 700 is n-type doped
  • emitter layer 706 is p-type doped.
  • Emitter layer 706 can formed by adding boron in a CVD deposition process.
  • SG-Si substrate 700 , back passivation/tunneling layer 704 , and emitter layer 706 form the hetero-tunneling back junction.
  • the thickness of emitter layer 706 can be between 1 and 20 nm.
  • An optimally doped (with doping concentration varying between 1 ⁇ 10 15 /cm 3 and 5 ⁇ 10 20 /cm 3 ) and sufficiently thick (at least between 3 nm and 20 nm) emitter layer can ensure a good ohmic contact and a large built-in potential.
  • the region within emitter layer 706 that is adjacent to back passivation/tunneling layer 704 can have a lower doping concentration, and the region that is further away from back passivation/tunneling layer 704 can have a higher doping concentration.
  • the lower doping concentration can reduce defect density at the interface between back passivation/tunneling layer 704 and emitter layer 706 , and the higher concentration on the other side can prevent emitter layer depletion.
  • a layer of intrinsic a-Si can be deposited between passivation/tunneling layer 704 and emitter layer 706 (e.g., by turning of the boron doping during the beginning of the CVD process).
  • tunneling oxide layer 704 which can be very thing (e.g., on the order of 10 angstroms). Before the CVD process, this thin oxide layer can be vulnerable due to potential contamination and reaction with chemicals and moisture in the air. Storing and/or transporting the wafer in the microenvironment can protect the wafer from such contamination.
  • tunneling oxide layer 702 can be in contact with the wafer carrier, which can cause contamination to oxide layer 702 .
  • front tunneling oxide layer 702 can optionally be removed by an additional wet etching step to expose c-Si surface 707 . Because tunneling oxide layer 702 is less critical on the junction between the base layer and subsequently deposited front surface field layer, removal of tunneling oxide layer 702 might not significantly impair the photovoltaic cell performance.
  • tunneling oxide layer 702 is now used as a sacrificial layer and removed to expose a “fresh” layer of c-Si on wafer 700 , the subsequently grown junction can be substantially free of defectives. After tunneling oxide layer 702 is removed, wafer 700 can be stored and/or transported in the microenvironment to protect the exposed c-Si surface 707 .
  • a layer of doped a-Si having a doping type same as that of substrate 700 can be deposited on exposed crystalline silicon surface 707 to form front surface field (FSF) layer 708 .
  • FSF front surface field
  • c-Si substrate 700 is n-type doped
  • FSF layer 708 is also n-type doped using phosphorous as dopant.
  • FSF layer 708 can be formed using a CVD technique.
  • C-Si substrate 700 and FSF layer 708 form the front surface junction.
  • the thickness of FSF layer 708 can be between 1 and 30 nm.
  • the doping concentration of FSF layer 708 can vary from 1 ⁇ 10 15 /cm 3 to 5 ⁇ 10 20 /cm 3 .
  • a-Si In addition to a-Si, it is also possible to use other material, including but not limited to: wide-bandgap semiconductor materials and polycrystalline Si, to form FSF layer 708 .
  • a layer of intrinsic a-Si can be deposited between c-Si surface 707 and FSF layer 708 to improve passivation.
  • the unfinished photovoltaic cell can be optionally placed and/or transported in an ultra-clean microenvironment while waiting for the next operation. After the junctions (both the front and the back junctions) are formed, the photovoltaic cell, although not yet finished, is less sensitive to environmental factors. Therefore, placing the unfinished photovoltaic cells in the ultra-clean microenvironment can be optional after operation 7 E.
  • a layer of TCO material can be deposited on both sides of wafer 700 , forming front-side and back-side conductive anti-reflection layers 712 and 710 , respectively.
  • the TCO material used in this step can be similar to that used in operation 5 E.
  • one or two separate PVD steps, such as sputtering, can be used to form TCO layers 510 and 512 .
  • front-side and back-side electrodes 714 and 716 can be formed on the surfaces of TCO layers 712 and 710 , respectively.
  • the techniques used for forming these electrodes can be similar to that used in operation 5 G.
  • FIG. 8 shows an exemplary photovoltaic cell fabrication facility 800 configured to perform the operations shown in FIG. 7 , according to one embodiment of the present invention.
  • photovoltaic cell fabrication facility 800 includes wet processing station 802 , CVD tool 804 , wet processing station 806 , CVD tool 808 , and PVD tool 810 . Respectively attached to these processing stations are buffers 812 , 814 , 816 , 818 , and 820 .
  • a wafer is first wet-processed in wet station 802 , where operations 7 A and 7 B are performed. During this wet processing, the wafer is cleaned and texturized. In addition, the wafer is oxidized on both sides in a hot bath to form the tunneling oxide layers.
  • the wafer is optionally placed in buffer 812 , where it is dried.
  • the wafer is then placed in a microenvironment, which in this example can be cabinet 822 .
  • the microenvironment inside cabinet 822 is controlled (e.g, filled with nitrogen and/or with chemical/humidity control).
  • Cabinet 822 can protect the thin oxide layers from potential contamination.
  • cabinet 822 and buffer 812 can be the same mechanism. That is, buffer 812 can be a cabinet that can be attached to and detached from wet processing station 802 . The same configuration can also be applied to buffers 814 , 816 , and 818 .
  • the wafer is then sent to CVD tool 804 via buffer 814 , and undergoes a first CVD process to have its back-side emitter layer formed, as described in operation 7 C.
  • the wafer is optionally placed in another microenvironment 824 , which can also be a cabinet. Transporting the wafer in cabinet 824 can be optional because at this moment the wafer's emitter layer is already formed, and the oxide layer on the opposite side serves as a sacrificial layer and will be subsequently removed.
  • the wafer is then moved to wet processing station 806 , which hosts a wet etching process to remove the oxide layer on the side where the front surface field layer is to be deposited.
  • wet processing station 806 hosts a wet etching process to remove the oxide layer on the side where the front surface field layer is to be deposited.
  • the wafer has an exposed surface (c-Si surface) and is moved into cabinet 826 via buffer 816 .
  • cabinet 826 also provides a controlled microenvironment to protect the exposed c-Si surface of the wafer.
  • the wafer is transported to CVD tool 808 via buffer 818 .
  • CVD tool 808 can be used to deposit the FSF layer, as described in operation 7 E.
  • the wafer is removed from CVD tool 808 and optionally placed in microenvironment 828 , which in this case can be a tunnel.
  • the wafer is then transported to PVD tool 810 via buffer 820 to form the front-side and back-side TCO layers, as described in operation 7 F.
  • one or more of the processing stations may be directly connected via a tunnel such as microenvironment 828 and without the need for buffers 818 and 820 .
  • the processing speed and throughput of two or more processing stations may be such that a buffer is not needed and a stations are communicatively coupled via a tunnel that forms a controlled microenvironment.
  • FIG. 9 shows the operation of an exemplary photovoltaic cell production line corresponding to FIGS. 7 and 8 , according to one embodiment of the present invention.
  • a number of photovoltaic cell wafers can be first loaded into a cassette (operation 902 ).
  • the cassette can undergo one or more wet processes, where the wafers are cleaned, texturized, and oxidized (operation 904 ).
  • the cassette may be submerged in one or more baths and go through one or more rinses.
  • the cassette (along with wafers within) is placed into a load/unload buffer (operation 906 ).
  • the load/unload buffer can include a chamber or a cabinet that is airtight and filled with purified N 2 .
  • the microenvironment within the load/unload buffer can be controlled to ensure that the wafers do not come into contact with various contaminants, including but not limited to: dust particles, harmful chemical vapors, aerosols, moisture, VOCs, etc., that may exist in the surrounding environment of the fabrication facility.
  • the cassette can be kept in the load/unload buffer until it is time for the next process, at which point the cassette is transported from the load/unload buffer from the wet station to the load/unload buffer of the first CVD tool (operation 908 ).
  • the cassette can be transported via an enclosed tunnel connecting the two load/unload buffers.
  • the cassette can be transported via a N 2 -filled cart.
  • wafers are loaded from the cassette into the first CVD tool (operation 910 ).
  • the back-side emitter layer is formed in the first CVD process (operation 912 ).
  • the wafer is placed in the buffer of the first CVD tool (operation 914 ) and transported to the second wet processing station (operation 916 ).
  • the second wet processing station then performs a wet etching step on the wafer to remove the oxide layer on the front side where the FSF layer will be deposited (operation 920 ). As a result, a layer of c-Si is exposed on the front-side surface of the wafer.
  • the cassette of wafers are placed into another buffer (operation 924 ) and transported to the second CVD tool in a controlled microenvironment (operation 926 ).
  • This microenvironment can protect the exposed c-Si surface from potential contamination.
  • the second CVD then deposits the FSF layer on the wafer (operation 928 ).
  • the cassette of wafers are transported to the PVD tool, optionally in a controlled microenvironment (operation 930 ).
  • the PVD tool can deposit both the front-side and back-side TCO layers, after which the wafers undergo a metallization process to form the electrodes (operation 932 ).
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