US20140084378A1 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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US20140084378A1
US20140084378A1 US14/033,842 US201314033842A US2014084378A1 US 20140084378 A1 US20140084378 A1 US 20140084378A1 US 201314033842 A US201314033842 A US 201314033842A US 2014084378 A1 US2014084378 A1 US 2014084378A1
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region
type
terminal
drain
source
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Hirofumi Harada
Masayuki Hashitani
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Ablic Inc
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Seiko Instruments Inc
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Publication of US20140084378A1 publication Critical patent/US20140084378A1/en
Assigned to SII SEMICONDUCTOR CORPORATION reassignment SII SEMICONDUCTOR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SEIKO INSTRUMENTS INC.
Priority to US15/247,144 priority Critical patent/US10014294B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883—Combination of depletion and enhancement field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • the present invention relates to an analog semiconductor integrated circuit device which is required to have a high output voltage accuracy.
  • a constant voltage circuit which outputs a constant voltage irrespective of the power supply voltage can be realized in a simplified manner at a low cost by, as illustrated in FIGS. 2A and 2B , connecting in series an enhancement type N-channel MOS field effect transistor (hereinafter referred to as NMOS) and a depression type N-channel MOS field effect transistor.
  • NMOS enhancement type N-channel MOS field effect transistor
  • depression type N-channel MOS field effect transistor a depression type N-channel MOS field effect transistor
  • a source terminal and a body terminal which is connected to a P-type well region are connected to a ground terminal at the lowest potential in the constant voltage circuit, while a gate terminal and a drain terminal are connected to a source terminal of a depression type NMOS 102 .
  • a drain terminal is connected to a power supply voltage terminal at the highest potential in the constant voltage circuit, while a gate terminal is connected to the source terminal of the NMOS 102 .
  • the NMOS 101 When such connection is made, first, the NMOS 101 operates in saturation because the potential of the gate terminal and the potential of the drain terminal are the same. With regard to the NMOS 102 , when a voltage of a certain level or higher is applied to the drain terminal, the NMOS 102 operates in saturation. Because currents which pass through the respective NMOSs are the same, the following simple relational expression which expresses a state in which the saturation currents are balanced with each other is obtained:
  • Kne ( Vg 1 ⁇ -Vtne ) 2 Knd ( Vg 2 ⁇ Vtnd ) 2 (a)
  • Kne, Vg1, and Vtne are the transconductance, the gate potential, and the threshold voltage of the NMOS 101 , respectively, and Knd, Vg2, and Vtnd are the transconductance, the gate potential, and the threshold voltage of the NMOS 102 , respectively.
  • an output value Vout of the constant voltage circuit is as follows:
  • Vout ( Knd/Kne ) 1/2 ⁇ Vtnd ⁇ +Vtne (b)
  • Vout can be adjusted by the element characteristics of the respective NMOSs.
  • Vtnd and Knd are the threshold voltage and the transconductance determined under the back bias effect caused by the voltage Vout since the potential of the body terminal of the NMOS 102 is lower than the potential of the source terminal. To prevent the change in characteristics due to the back bias effect the body terminal will be connected to the source terminal.
  • FIG. 4 a method of manufacturing the above-mentioned conventional semiconductor integrated circuit device is schematically described with reference to FIG. 4 .
  • the same terminology is used as in FIGS. 2A and 2B .
  • a P-type semiconductor substrate or an N-type semiconductor substrate is prepared.
  • P-type impurities of boron (B) or BF 2 are injected by ion implantation into desired regions in which the NMOSs are to be formed, thermal diffusion is performed to form the P-well regions (Step a).
  • the amount of the injected impurities and the conditions of the thermal diffusion are selected so that the impurity concentration in the P-well regions lies between 1 ⁇ 10 16 cm ⁇ 3 and 1 ⁇ 10 17 cm ⁇ 3 and the depth of the P-well regions is several micrometers.
  • Step b in order to electrically isolate the elements from each other, LOCOS or the like is used to form an element isolation region.
  • P-type impurities of boron (B) or BF 2 are injected by ion implantation into the region in which the enhancement type NMOS is to be formed (Step c).
  • N-type impurities of phosphorus (P) or arsenic (As) are injected by ion implantation into the region in which the depression type NMOS is to be formed (Step d).
  • Step e a gate oxide film of the enhancement type NMOS and the depression type NMOS is formed by thermal oxidation.
  • Step f in order to form gate electrodes of the enhancement type NMOS and the depression type NMOS, a poly-Si film is deposited and impurities at a high concentration are injected so as to attain 1 ⁇ 10 19 cm ⁇ 3 or higher by ion implantation or thermal diffusion, and patterning is carried out (Step f).
  • N-type high concentration impurities for forming the source/drain have a concentration 1 ⁇ 10 19 cm ⁇ 3 or higher and are arranged at a predetermined distance from the end of the gate electrode.
  • N-type low concentration impurity regions of 5 ⁇ 10 16 cm ⁇ 3 to 5 ⁇ 10 17 cm ⁇ 3 are formed from the N-type high concentration impurity regions to the ends of the gate electrode, respectively.
  • the N-type low concentration impurity regions operate to alleviate the electric field when a high voltage is applied (Step g).
  • an insulating film which is an oxide film is deposited on the entire surface.
  • metal wiring is formed by sputtering and patterning a metal film (Step h).
  • FIGS. 3A and 3B Another exemplary conventional constant voltage circuit is described with reference to FIGS. 3A and 3B .
  • the same NMOS element as illustrated in FIGS. 2A and 2B is used, and only the wiring method is changed. Specifically, a change is made so that the gate terminal of the depression type NMOS 102 is connected to the ground terminal which is the lowest potential in the constant voltage circuit. Because the gate voltage of the depression type NMOS 102 is shifted to a negative side by Vout, the output voltage and the current consumption can be remarkably reduced.
  • the system of the above-mentioned constant voltage circuit is disclosed in, for example, Japanese Patent Application Laid-open No. 2008-293409.
  • the output voltage of the constant voltage circuit varies. Further, the output voltage also fluctuates when the environment such as the temperature fluctuates. Accordingly, a method of realizing an NMOS element structure or a semiconductor integrated circuit system which can reduce fluctuations in output voltage of a constant voltage circuit is desired.
  • a semiconductor integrated circuit device includes an enhancement type first N-channel type MOS transistor and a depression type second N-channel type MOS transistor, the first NMOS being formed on a P-type well region, having a gate oxide film, a gate electrode, and source and drain regions each of which includes an N-type low concentration region and an N-type high concentration region, and having a positive threshold voltage, the second NMOS being formed on a P-type well region, having a gate oxide film, a gate electrode, source and drain regions each of which includes an N-type low concentration region and an N-type high concentration region, and an N-type channel impurity region, and having a negative threshold voltage.
  • a gate terminal connected to the gate electrode and a drain terminal connected to the drain region of the first NMOS are connected to a source terminal connected to the source region and a gate terminal of the second NMOS.
  • a source terminal and a body terminal connected to the P-type well region of the first NMOS are connected to a ground potential which is the lowest potential in a circuit, a drain terminal of the second NMOS is connected to a power supply voltage which is the highest potential in the circuit, and a body terminal of the second NMOS is connected to the ground potential.
  • the impurity concentration of the P-type well region on which the second NMOS is arranged is higher than the impurity concentration of the P-type well region on which the first NMOS is arranged.
  • a semiconductor integrated circuit device includes an enhancement type first N-channel type MOS transistor and a depression type second N-channel type MOS transistor, the first NMOS being formed on a P-type well region, having a gate oxide film, a gate electrode, and source and drain regions each of which includes an N-type low concentration region and an N-type high concentration region, and having a positive threshold voltage, the second NMOS being formed on a P-type well region, having a gate oxide film, a gate electrode, source and drain regions each of which includes an N-type low concentration region and an N-type high concentration region, and an N-type channel impurity region, and having a negative threshold voltage.
  • a gate terminal connected to the gate electrode and a drain terminal connected to the drain region of the first NMOS are connected to a source terminal connected to the source region of the second NMOS.
  • a source terminal and a body terminal connected to the P-type well region of the first NMOS are connected to a ground potential which is the lowest potential in a circuit
  • a drain terminal of the second NMOS is connected to a power supply voltage which is the highest potential in the circuit
  • a gate terminal and a body terminal of the second NMOS are connected to the ground potential.
  • the impurity concentration of the P-type well region on which the second NMOS is arranged is higher than the impurity concentration of the P-type well region on which the first NMOS is arranged.
  • the impurity concentration of the P-type well region on which the first NMOS is arranged is lower than 1 ⁇ 10 17 /cm 3 and the impurity concentration of the P-type well region on which the second NMOS is arranged is higher than 1 ⁇ 10 17 /cm 3 .
  • the P-type well regions of the first and second NMOSs have the same impurity concentration, but a P-type impurity layer having a partly higher impurity concentration than that of the P-type well region is provided under the N-type channel impurity region of the second NMOS.
  • the impurity concentration of the P-type well region on which the first NMOS is arranged is lower than 1 ⁇ 10 17 /cm 3 and the impurity concentration of the P-type impurity layer having a partly higher impurity concentration than that of the P-type well region under the N-type channel impurity region of the second NMOS is higher than 1 ⁇ 10 17 /cm 3 .
  • each of the source/drain regions of the second NMOS includes an N-type low concentration region in proximity to the gate electrode and an N-type high concentration region which is formed under a contact hole and in contact with the N-type low concentration region, and the length of the N-type low concentration region in the source region from an end of the gate electrode to the N-type high concentration region is larger than the length of the N-type low concentration region in the drain region from another end of the gate electrode to the N-type high concentration region.
  • a highly accurate analog semiconductor integrated circuit device can be provided which can inhibit fluctuations in output voltage of a constant voltage circuit.
  • FIG. 1 is a schematic sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention
  • FIG. 2A is a schematic sectional view of a conventional semiconductor integrated circuit device
  • FIG. 2B is a circuit connection diagram of the conventional semiconductor integrated circuit device
  • FIG. 3A is a schematic sectional view of another conventional semiconductor integrated circuit device
  • FIG. 3B is a circuit connection diagram of the conventional semiconductor integrated circuit device
  • FIG. 4 is a process flow chart for manufacturing the conventional semiconductor integrated circuit device
  • FIG. 5 is a process flow chart for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.
  • FIG. 6 is a graph showing the relationship between a gate voltage and a drain current in a depression type NMOS transistor
  • FIG. 7 is a schematic sectional view of another semiconductor integrated circuit device according to the first embodiment of the present invention.
  • FIG. 8 is a schematic sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention.
  • FIG. 9 is a schematic sectional view of another semiconductor integrated circuit device according to the second embodiment of the present invention.
  • FIG. 10 is a process flow chart for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention.
  • FIG. 11 is a schematic sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention.
  • FIG. 12 is a schematic sectional view of another semiconductor integrated circuit device according to the third embodiment of the present invention.
  • FIG. 1 is a sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention, and is an example in which a constant voltage circuit effectively uses a back bias applied to a depression type NMOS.
  • FIG. 1 is a sectional view in which the conventional constant voltage circuit illustrated in FIGS. 2A and 2B has a feature of the present invention added thereto. The difference is that a P-well region on which an enhancement type NMOS 101 is arranged and a P-well region on which a depression type NMOS 102 is arranged are individually formed, and the impurity concentrations of the P-well regions are different from each other.
  • the impurity concentration of a P-well region 5 on which the enhancement type NMOS 101 is arranged is 1 ⁇ 10 15 /cm 3 or higher and lower than 1 ⁇ 10 17 /cm 3 , which is an ordinary concentration, while the impurity concentration of a P-well region 6 on which the depression type NMOS 102 is arranged is a special concentration of 1 ⁇ 10 17 /cm 3 or higher.
  • the threshold voltage When a negative back bias is applied to a body terminal of an NMOS, depending on the impurity profile in a channel, the threshold voltage generally shifts to a higher side and the transconductance (corresponding to the slope of the voltage-current characteristics shown in FIG. 6 ) generally shifts to a lower side.
  • the threshold voltage becomes higher by an amount corresponding to the gate voltage necessary for keeping the balance with charge in a depletion layer under the gate which is caused when the back bias is applied. Because an increase in the impurity concentration of the P-well region increases the charge density in the depletion layer, the threshold voltage becomes further higher. Further, in that case, because the electric field becomes stronger in a direction perpendicular to a current in a plane direction through the channel, the carrier mobility is lowered to lower the transconductance.
  • FIG. 5 a method of manufacturing the semiconductor integrated circuit device of this embodiment is schematically described with reference to FIG. 5 .
  • like reference numerals are used to designate like members in FIG. 1 .
  • a P-type semiconductor substrate or an N-type semiconductor substrate 1 is prepared. After P-type impurities of boron (B) or BF 2 are injected by ion implantation into desired regions in which the NMOSs are to be formed, thermal diffusion is performed to form the P-well regions ( 5 and 6 ) having different impurity concentrations from each other (Steps a and b).
  • the amounts of the injected impurities and the conditions of the thermal diffusion are selected so that the impurity concentration in the P-well region 5 is 1 ⁇ 10 16 cm ⁇ 3 or higher and lower than 1 ⁇ 10 17 cm ⁇ 3 , the impurity concentration in the P-well region 6 is 1 ⁇ 10 17 cm ⁇ 3 or higher, and the depths of the P-well regions 5 and 6 are several micrometers.
  • Step c in order to electrically isolate the elements from each other, LOCOS or the like is used to form an element isolation region.
  • P-type impurities of boron (B) or BF 2 are injected by ion implantation into the region in which the enhancement type NMOS is to be formed (Step d).
  • N-type impurities of phosphorus (P) or arsenic (As) are injected by ion implantation into the region in which the depression type NMOS is to be formed to form an N-type channel impurity region 10 (Step e).
  • a gate oxide film 9 of the enhancement type NMOS and the depression type NMOS is formed by thermal oxidation (Step f).
  • a poly-Si film is deposited and impurities at a high concentration are injected so as to attain 1 ⁇ 10 19 cm ⁇ 3 or higher by ion implantation or thermal diffusion, and patterning is carried out (Step g).
  • source/drain regions 7 and regions for giving potentials of P-well regions (referred to as body regions) under channels of the enhancement type NMOS and the depression type NMOS impurities are injected by ion implantation.
  • N-type high concentration impurities for forming the source/drain are injected at a concentration so as to attain 1 ⁇ 10 19 cm ⁇ 3 or higher at a predetermined distance from ends of the gate electrode.
  • N-type low concentration impurity regions of 5 ⁇ 10 16 cm 3 to 5 ⁇ 10 17 cm ⁇ 3 are formed from the high concentration source impurity regions to the ends of the gate electrode, respectively.
  • the N-type low concentration impurity regions function to alleviate the electric field when a high voltage is applied (Step h).
  • an insulating film which is an oxide film is deposited on the entire surface.
  • metal wiring 2 to 4 is formed by sputtering and patterning a metal film (Step i).
  • the gate terminal of the depression type NMOS 102 in FIG. 1 is connected to a VSS terminal 104 , and the semiconductor integrated circuit device in FIG. 7 corresponds to the conventional semiconductor integrated circuit device illustrated in FIGS. 3A and 3B .
  • the gate potential of the depression type NMOS is linked with increase or decrease in output voltage, feedback acts so as to inhibit fluctuations in output voltage.
  • the feedback due to the back bias effect described above with reference to FIG. 1 acts. In this way, a more stable output potential can be realized.
  • FIG. 8 illustrates a second embodiment for realizing the back bias effect as described with reference to FIG. 1 .
  • the enhancement type NMOS 101 and the depression type NMOS 102 have the same P-well region 5 , but a P-type channel impurity region 11 having the impurity concentration higher than that of the P-well region is locally formed immediately below the N-type channel impurity region 10 of the depression type NMOS 102 .
  • Such a structure enables the depression type NMOS 102 to obtain a sufficient back bias effect similarly to the case illustrated in FIG. 1 , and the stability of the output voltage of the constant voltage circuit can be improved.
  • the gate terminal of the depression type NMOS 102 illustrated in FIG. 8 is connected to a VSS terminal 103 .
  • the feedback due to the back bias effect according to the present invention acts, and a more stable output potential can be realized.
  • FIG. 10 schematically illustrates semiconductor manufacturing steps of the second embodiment.
  • a step (e) of injecting P-type impurities such as boron (B) or BF 2 for the depression type NMOS is added.
  • the P-type impurity region is formed by ion implantation, and the energy for the step is selected so that, in terms of injection depth, the impurity concentration becomes the highest immediately below the N-type channel impurity region.
  • this step By carrying out this step as the same mask step as the step of injecting the N-type impurities prior to the step, the number of the mask steps is prevented from being increased. Because it is not necessary to prepare a mask for forming the P-well region dedicated to the depression type NMOS as in the first embodiment, there is an advantage over the case of the first embodiment in that the manufacturing steps can be reduced to realize cost reduction.
  • FIG. 11 illustrates a third embodiment of the present invention in which the back bias effect as described with reference to FIG. 1 is obtained by another method.
  • the source side extends longer than the drain side.
  • the low concentration source/drain regions be short insofar as no degradation in characteristics is caused. The reason is to reduce the footprint to contribute to cost reduction.
  • the length of the N-type low concentration region on the source side of the depression type NMOS 102 is extended to be at the level of several micrometers to several tens of micrometers, while the other N-type low concentration region is at the ordinary level of several micrometers and is caused to be as small as possible.
  • this N-type low concentration region has a surface resistivity of several kilo-ohms per square to several tens of kilo-ohms per square, when the depression type NMOS is operated, a drive current of the transistor also passes through this N-type low concentration region, and voltage drop of several hundreds of millivolts to several volts is caused. This voltage drop causes voltage difference between the source terminal and the body terminal in the channel region of the depression type NMOS for the voltage drop, which is the back bias in the depression type NMOS.
  • this embodiment is a highly versatile method which can be applied to various kinds of semiconductor processes, because, although the necessary area increases, no special semiconductor manufacturing step is added.
  • the gate terminal of the depression type NMOS 102 illustrated in FIG. 11 is connected to the VSS terminal 103 .
  • the feedback due to the back bias effect according to the present invention acts, and a more stable output potential can be realized.
  • the impurity concentration of the P-well region can be set to be higher and a P-type high concentration impurity region can be formed under the N-type channel impurity region at the same time. Further, by setting the impurity concentration of the P-well region to be higher and providing the P-type channel impurity region, and in addition, extending the N-type low concentration region on the source side at the same time, the back bias effect can be enhanced to further improve the stability of the output voltage of the constant voltage circuit.

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KR102074124B1 (ko) 2020-02-06
CN103699164A (zh) 2014-04-02
TWI612639B (zh) 2018-01-21
CN103699164B (zh) 2018-04-06
JP6095927B2 (ja) 2017-03-15
US20160372465A1 (en) 2016-12-22
TW201428939A (zh) 2014-07-16
JP2014072235A (ja) 2014-04-21
US10014294B2 (en) 2018-07-03
KR20140041374A (ko) 2014-04-04

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