US20050017236A1 - Semiconductor device and semiconductor substrate - Google Patents

Semiconductor device and semiconductor substrate Download PDF

Info

Publication number
US20050017236A1
US20050017236A1 US10/920,432 US92043204A US2005017236A1 US 20050017236 A1 US20050017236 A1 US 20050017236A1 US 92043204 A US92043204 A US 92043204A US 2005017236 A1 US2005017236 A1 US 2005017236A1
Authority
US
United States
Prior art keywords
layer
strained
strain
strain applying
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/920,432
Other languages
English (en)
Inventor
Nobuyuki Sugii
Kiyokazu Nakagawa
Shinya Yamaguchi
Masanobu Miyao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to US10/920,432 priority Critical patent/US20050017236A1/en
Publication of US20050017236A1 publication Critical patent/US20050017236A1/en
Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HITACHI, LTD.
Priority to US12/010,123 priority patent/US7579229B2/en
Priority to US12/505,942 priority patent/US8304810B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Definitions

  • the present invention relates to a semiconductor device and a method for manufacture thereof, and more particularly to a semiconductor device including an field effect transistor.
  • Si-MOSFET's SiMOS field effect transistors
  • the various improvements as mentioned above are ironically enough caught in the result that the mobility in Si in the real device is smaller than 100 or is far less than the value of mobility in bulk.
  • the further improvement in performance has a need to contemplate the enhancement in speed by improving a semiconductor material itself.
  • One solution is to use a so-called compound semiconductor which provides a high speed in itself.
  • this solution is not realistic since it is very difficult to combine the compound semiconductor technology with the Si integrated circuit technology and the manufacture cost becomes stupendous.
  • One object of the present invention is to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like in the same group as that of Si.
  • a strain applying semiconductor layer applies a strain to a channel forming layer in which a channel of a field effect transistor is formed.
  • the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.
  • the strain application makes the in-plane lattice constant of the Si channel forming layer larger than that of unstrained Si.
  • a semiconductor device having a p-type field effect transistor in which the energy at a top of the valence band of the interface between a channel forming layer and one of layers adjacent to opposite surfaces of the channel forming layer lying on a gate insulating film side of the channel forming layer is made larger than that of the interface between the channel forming layer and the other adjoining layer lying on the other side of the channel forming layer.
  • a semiconductor device having an n-type field effect transistor in which the energy at a top of the conduction band of the interface between a channel forming layer and one of layers adjacent to opposite surfaces of the channel forming layer lying on a gate insulating film side of the channel forming layer is made smaller than that of the interface between the channel forming layer and the other adjoining layer lying on the other side of the channel forming layer.
  • an energy barrier for carriers in a channel of a field effect transistor exists on a side of the channel opposite to a gate insulating film, and the lattice of a channel forming layer having the channel formed therein is strained so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.
  • FIG. 1 is a diagram for explaining the principle of operation of the present invention or a band diagram of the multilayered structure of an SiO 2 gate insulating film, a strained Si layer and an Si 1-x Ge x strain applying layer;
  • FIG. 2 is a band diagram in a state in which a positive bias is applied to a gate of the structure shown in FIG. 1 ;
  • FIG. 3 is a band diagram in a state in which a negative bias is applied to the gate of the structure shown in FIG. 1 ;
  • FIG. 4 is a band diagram in a state in which a steep n-type doping is applied to the uppermost portion of the Si 1-x Ge x strain applying layer of the structure shown in FIG. 1 ;
  • FIG. 5 is a band diagram in a state in which a substrate biasing voltage is applied to the structure shown in FIG. 1 ;
  • FIG. 6 is another diagram for explaining the principle of operation of the present invention or a band diagram of the multilayered structure of an SiO 2 gate insulating film, a strained Si layer, a strained Si 1-y Ge y layer and an Si 1x Ge x strain applying layer;
  • FIG. 7 is a cross section showing the structure of complementary field effect transistors according to Embodiment 1 of the present invention.
  • FIG. 8 is a cross section showing the structure of complementary field effect transistors according to Embodiment 2 of the present invention.
  • FIG. 9 is a cross section showing the structure of complementary field effect transistors according to Embodiment 3 of the present invention.
  • FIG. 10 is a cross section showing the structure of complementary field effect transistors according to Embodiment 4 of the present invention.
  • FIG. 11 is a cross section showing the structure of complementary field effect transistors according to Embodiment 5 of the present invention.
  • FIG. 12 is a cross section showing the structure of complementary field effect transistors according to Embodiment 6 of the present invention.
  • FIG. 13 is a cross section showing the structure of complementary field effect transistors according to Embodiment 7 of the present invention.
  • FIG. 14 is the cross section of an SOI substrate according to Embodiment 8 of the present invention.
  • FIG. 15 is the cross section of an SOI substrate according to Embodiment 9 of the present invention.
  • FIGS. 16 a to 16 d are cross sections showing the manufacture steps of an SOI substrate according to Embodiment 10 of the present invention.
  • FIG. 1 shows a band diagram of the multilayered structure of an SiO 2 gate insulating film 3 , a strained Si layer 1 and an Si 1-x Ge x strain applying layer 2 .
  • the band diagram exhibits a band discontinuity the type of which is such that the band gap 6 of the strained Si layer 1 is wider than the band gap 7 of the Si 1-x Ge x strain applying layer 2 and the energies of the valence band 5 and the conduction band 4 of the strained Si layer 1 are both lowered.
  • the application of a positive voltage to the gate causes a band bend in the vicinity of the interface between the gate insulating film 3 and the strained Si layer 1 , as shown in FIG. 2 , so that electrons are stored in a notch 10 of the conduction band in the strained Si layer 1 formed in the bent portion, thereby enabling a transistor operation.
  • This is quite the same as an ordinary MOS type field effect transistor.
  • the application of a negative voltage to the gate causes a band bend in the vicinity of the interface between the gate insulating film 3 and the strained Si layer 1 , as shown in FIG. 3 .
  • more holes are stored in a notch 12 of the valence band in the Si 1-x Ge x strain applying layer 2 formed in the interface between the strained Si layer 1 and the Si -x Ge x strain applying layer 2 than a notch 11 of the valence band in the strained Si layer 1 formed in the bent portion.
  • the source/drain junction depth is made sufficiently shallower than the thickness of the strained Si layer 1 , thereby preventing the effluence of holes into the Si 1-x Ge x strain applying layer 2 . More particularly, for example, when the thickness of the strained Si layer 1 is 70 nm, the junction depth may be selected to be about 40 nm. Since this is much the same as a value used in a short-channel device having a channel length shorter than 0.1 microns, it is sufficiently realizable.
  • a steep n-type doping preferably, with the doping depth in the range of 0.1 to 30 nm is applied in the vicinity of the interface between the Si 1-x Ge x strain applying layer 2 and the strained Si layer 1 .
  • the energy level at the top 43 of the notch 12 of the valence band in the Si 1-x Ge x strain applying layer 2 is lowered, as shown in FIG. 4 .
  • the storage of holes in the notch 12 is reduced.
  • This method can also be realized by applying the n-type doping to the strained Si layer 1 or both the strained Si layer and the Si 1-x Ge x strain applying layer 2 .
  • the doping depth is in the range of 0.1 to 30 nm.
  • a substrate biasing voltage is controlled so that a positive voltage is applied onto the Si 1-x Ge x strain applying layer 2 side.
  • this method provides a band structure with a downward inclination on the right side, that is, a falling on the Si 1-x Ge x strain applying layer 2 side so that the energy level at the top 43 of the notch 12 of the valence band in the Si 1-x Ge x strain applying layer 2 becomes lower than the energy level at the top 42 of the notch 11 of the valence band in the strained Si layer 1 .
  • the storage of holes in the notch 12 is reduced.
  • the prevention of the effluence of holes from the strained Si channel into the strain applying layer is a factor indispensable to the realization of a p-type field effect transistor or complementary field effect transistors.
  • the employment of the following construction is also effective. Namely, the material of a drain region in the case of a p-type field effect transistor or a source region in the case of an n-type field effect transistor is selected to be the same parent material as the Si 1-x Ge x strain applying layer or to have the same composition ratio as the Si 1-x Ge x strain applying layer.
  • a band discontinuity between the strained Si and the SiGe causes a change in electric field distribution between the source and the drain to enable the more effective acceleration of carriers.
  • a further enhancement in speed can be contemplated and the reduction in pinch off voltage enables an operation at a low voltage.
  • the effluence of holes into the strain applying layer 2 becomes hard to generate.
  • the mobility of holes in the strained Si 1-y Ge y layer 25 is higher than the mobility of electrons in the strained Si layer 1
  • a construction having the strained Si 1-y Ge y layer 25 far from the gate electrode or overlaid by the strained Si layer 1 is more preferable considering a balance in mutual conductance in the case where complementary field effect transistors are formed.
  • an additional SiGe layer may be sandwiched between the strained Si layer 1 or the strained Si 1-y Ge y layer 25 and the gate insulating film 3 .
  • electrons or holes are confined in the strained Si layer 1 or the strained Si -y Ge y layer 25 in the vicinity of the interface thereof with the additional SiGe layer, they are free of the influences of the interface state with respect to the gate insulating film 3 and the scattering thereat.
  • the strained Si layer and the strained Si 1-y Ge y layer may be grown by use of a selective growth method so that the strained Si 1-y Ge y layer is grown in a p-channel area while the strained Si layer is grown in an n-channel area.
  • the lattice constant of Ge is larger than that of Si by about 4%.
  • the lattice constant of Si 1-x Ge x takes an interpolated value in accordance with the Ge composition ratio. Accordingly, if a proper value of x is selected, it is possible to apply a desired strain to Si or Ge overlying Si 1-x Ge x . For example, if x is selected to be 0.5, it is possible to apply an in-plane tensile strain of 2% and an in-plane compressive strain of 2% to Si and Ge, respectively. The magnitude of the strain of each of Si and Si 1-y Ge y can be controlled in accordance with the selected value of x.
  • the in-plane lattice constant of a strained Si layer can be made larger than that of unstrained Si within a range of proportions less than 4% and the in-plane lattice constant of a strained Si 1-y Ge y layer can be made smaller than that of unstrained Ge within a range of proportions less than 4%.
  • a balance in mobility between electrons and holes can be controlled to make a balance in transconductance between complementary field effect transistors with each other.
  • the adjustment has been made only by changing the dimensions of the device.
  • the present method mentioned above provides an increase of the degree of freedom in design and is advantageous to an increase in degree of integration.
  • the way for strain control excepting the change in Ge composition ratio of Si 1-x Ge x may be to change the composition ratio y in (Si 1-x Ge x ) 1-y C y having the addition of C.
  • a method of adding C may be the addition of C at the time of growth of a strain applying layer or the addition of C through ion implantation or the like after the growth of a strain applying layer.
  • the strain applying layer may be provided by a method of growing Si 1-x Ge x having a fixed composition or may be a so-called graded buffer layer formed by a method of increasing a composition ratio x gradually toward the direction of growth from an Si substrate. Also, a method of growing an Si layer with high defect density on an Si substrate at a low temperature or forming a defect layer on an Si substrate, for example, through the implantation of ions of hydrogen, Si, Ge or the like and thereafter growing Si 1-x Ge x is preferable since a threading dislocation density can be reduced as compared with the case where Si 1-x Ge x is directly grown on an Si substrate and since there results in a satisfactory surface flatness.
  • a further enhancement in speed can be contemplated by virtue of the reduction of a stray capacity.
  • SOI Silicon On Insulator
  • a wafer-bonding type SOI substrate, an SIMOX (Separation by Implanted Oxygen) substrate and so forth are commercially available for SOI.
  • An Si 1-x Ge x strain applying layer can be grown on such a substrate to manufacture a strained Si (S 1-y Ge y (0 ⁇ y ⁇ 1)) field effect transistor in which the best use of the feature of SOI is made.
  • a method which includes the steps of first growing an Si 1-x Ge x strain applying layer on an Si substrate, thereafter performing the implantation of oxygen ions and a heat treatment to bury an SiO 2 insulating layer in the Si 1-x Ge x strain applying layer or in Si just therebelow and thereafter growing a strained Si layer or a method which includes the steps of first growing an Si 1-x Ge x strain applying layer and a strained Si layer on an Si substrate and thereafter performing the implantation of oxygen ions and a heat treatment to bury an SiO 2 insulating layer in the strained Si layer.
  • the thickness of the SOI active layer can be reduced, excellent device isolation is provided and no pMOS/nMOS well layer is required.
  • the SiO 2 insulating layer lies just below the strained Si layer, there is not generated the earlier-mentioned problem in pMOS that holes flow into the strain applying layer.
  • a substrate is prepared by growing an Si 1-x Ge x strain applying layer on an Si substrate, further growing an Si layer and thereafter subjecting a part or the whole of the Si layer to thermal oxidation.
  • the thermal oxidation of the Si layer may be replaced by the growth of an SiO 2 layer on the Si 1-x Ge x strain applying layer through a vapor growth method or the like.
  • the resultant structure and a separately prepared supporting substrate are bonded so that SiO 2 faces the supporting substrate.
  • the Si 1-x Ge x strain applying layer is exposed by polishing the Si substrate having the Si 1-x Ge x strain applying layer grown thereon or performing the cutting through the implantation of hydrogen ions, the insertion of an intermediate porous Si layer, or the like.
  • the wafer-bonded SOI substrate with the Si 1-x Ge x strain applying layer can be manufactured.
  • the reduction in defect density can be contemplated.
  • the polishing, etching or the like is made, the insurance of a surface flatness is facilitated.
  • the thickness of the SOI active layer can be reduced, excellent device isolation is provided and no pMOS/nMOS well layer is required.
  • a substrate having a strained Si layer placed on an SiO 2 layer can be manufactured by growing an Si 1-x Ge x strain applying layer on an Si substrate, further growing a strained Si layer, subjecting a part of the strained Si layer to thermal oxidation, bonding the resultant substrate and a separately prepared supporting substrate so that SiO 2 faces the supporting substrate, and performing the polishing or the peeling off with the portion of the strained Si layer left.
  • this substrate is quite the same as the conventional laminated SOI substrate excepting that the SOI layer is applied with a strain.
  • the present substrate can be handled in a manner quite similar to the conventional SOI substrate, is excellent in device isolation and requires no pMOS/nMOS well layer. And, the present substrate is provided with the feature of strained Si that by virtue of the effect of strain, the effective mass in the SOI active layer is light and the electron and hole mobilities therein are high. Also, since the SiO 2 insulating layer lies just below the strained Si layer, there is not generated the earlier-mentioned problem in pMOS that holes flow into the strain applying layer.
  • the thickness of the strained Si layer is subject to a fixed restriction. The reason is that an upper limit imposed on the thickness of a strained Si layer capable of growing without strain relaxation exists depending upon the magnitude of strain. This is called a critical thickness.
  • the thickness of the strained Si layer falls within a range between 1 nm and 200 nm. The reason is that the thickness smaller than 1 nm is insufficient as the thickness of an active layer forming a channel of a field effect transistor. On the other hand, as the thickness becomes larger than 200 nm, a strain relaxation occurs so that a bad influence on electric characteristics begins to appear.
  • the orientation of the substrate is advantageous in connection with the conventional device and the utilization of the same process as the conventional device since this orientation has hitherto been used in many Si semiconductor devices. Also, this orientation is preferable since the mobility is greatly increased when a strain is applied.
  • the in-plane direction of the channel is selected to be a ⁇ 110> or ⁇ 001> direction. This is advantageous in enhancing the controllability of processes such as epitaxial growth and etching.
  • ⁇ 110 ⁇ plane As the substrate surface orientation, it is also possible to use a ⁇ 110 ⁇ plane as the substrate surface orientation.
  • the selection of a ⁇ 110> or ⁇ 001> direction as the channel direction is advantageous in view of an increase in mobility caused by the application of a strain.
  • the ⁇ 110> direction is used as the channel for electrons.
  • a balance between an nMOSFET and a PMOSEFT it is not necessarily required that such an arrangement should be used.
  • a field effect transistor or complementary field effect transistors with a strain-applied active layer forming a channel and a semiconductor device using such transistor(s) have a very high industrial value since the effective mass of carriers flowing through the channel is light as compared with the case of the conventional transistor(s) and semiconductor device, the mobility is therefore high, the enhancement in speed can be contemplated and the increase in degree of integration and the improvement in performance of the device can further be contemplated.
  • FIG. 7 is the cross section of CMOSFET's according to the present embodiment.
  • an Si substrate 13 is cleaned, it is immediately introduced into a chemical vapor growth chamber to grow an Si 0.7 Ge 0.3 strain applying layer 2 .
  • the surface orientation of the Si substrate 13 is selected to be ⁇ 100 ⁇ .
  • the thickness of the layer 2 is 500 nm.
  • Source materials used include Si 2 H 6 and GeH 4 and the layer is grown at a growing temperature of 700° C.
  • no doping for determining the conduction type is conducted.
  • the strained Si layer 1 is formed on the Si 1-x Ge x strain applying layer 2 through a chemical vapor deposition.
  • no doping for determining the conductivity type is conducted.
  • the thickness is 60 nm.
  • This layer is subjected to an in-plane tensile strain because the lattice constant of the Si 1-x Ge x strain applying layer 2 is larger than that of Si. This results in that the mobilities of carriers (electrons and holes) in the strained Si layer 1 are larger than those in unstrained Si.
  • the growth of the Si layer and the SiGe layer is not limited to the chemical vapor deposition.
  • a device isolation region 19 is formed through a trench isolation method and ion implantation for well formation is made over a lower portion of the strained Si layer 1 and the Si 1-x Ge x strain applying layer 2 .
  • the lower portion of a PMOS area is implanted with a V-group element such as P so that it has an n type
  • the lower portion of an NMOS area is implanted with a III-group element such as B so that it has a p type.
  • an upper portion of the strained Si layer 1 is implanted with a III-group element in the PMOS area and a V-group element in the NMOS area to adjust a threshold voltage.
  • the surface of the strained Si layer 1 is subjected to thermal oxidation to form an SiO 2 gate insulating film 3 .
  • a polycrystalline silicon gate electrode 16 is formed on the film 3 .
  • the other than the gate region is etched away.
  • source/drain regions are formed in a self-alignment manner through an ion implantation method.
  • p-type source/drain regions 17 can be formed by the implantation of a III-group element such as B and n-type source/drain regions 18 can be formed by the implantation of a V-group element such as P. Accordingly, it is possible to fabricate both the PMOS and the NMOS on the same wafer.
  • the ion implantation depth is selected to be 30 nm which is equal to or smaller than the thickness of the strained Si layer 1 .
  • an inter-layer insulating film (not shown) is formed, contact holes are provided, and a metal film such as Al is vapor-deposited and patterned to form a metal wiring, thereby completing the field effect transistor.
  • This transistor has a transconductance about 3 times as large as and a cut-off frequency 2.4° times as high as a field effect transistor of unstrained Si directly formed with the same dimension on an Si substrate.
  • FIG. 8 is the cross section of CMOSFET's according to the present embodiment.
  • the depth of the source/drain regions 17 and 18 is selected to be 50 nm which is deeper than 30 nm in Embodiment 1 and is used in the ordinary case.
  • an upper depth portion of the layer 2 down to 30 nm is subjected to steep n-type doping at a high concentration of 10 18 per cubic centimeter with a P doping gas mixed.
  • the nMOS area is covered with an oxide film in order to subject only the PMOS area to the doping. The oxide film is removed after the doping is conducted.
  • the ion implantation for well formation is not made to the pMOS area subjected to the steep doping.
  • FIG. 9 is the cross section of CMOSFET's according to the present embodiment.
  • the application of a positive bias to the pMOS well region is substituted for the steep doping in Embodiment 2.
  • a contact hole is provided at the outside of a device area and an ohmic contact is formed thereat as a bias applying electrode 22 .
  • a punch through current can be reduced to 5% or less as compared with that in the case where no bias is applied.
  • Embodiments 1 to 3 can be applied simultaneously and the combination of two or three thereof is possible.
  • FIG. 10 is the cross section of CMOSFET's according to the present embodiment.
  • a drain region 15 of the strained Si layer 1 in the p-type MOSFET and a source region 14 of the strained Si layer 1 in the n-type MOSFET in Embodiment 1 are selectively etched and the etched portions are filled up with Si 1-x Ge x layers 23 selectively grown therein.
  • the surface layer of this portion with 5 nm is made of Si, thereby preventing the Si 1-x Ge x layer 23 from being damaged in the subsequent process.
  • the operating voltage of the transistor according to the present embodiment can be reduced as compared with the operating voltage of 3 V which are often used in conventional MOSFET's.
  • FIG. 11 is the cross section of CMOSFET's according to the present embodiment.
  • the present embodiment is characterized in that a strained Ge y layer is used as a channel for PMOS.
  • An Si substrate 13 is subjected to hydrogen ion implantation beforehand so that a layer with a high defect density is formed extending from the surface to the 100 nm depth. After this substrate is cleaned, it is immediately introduced into a chemical vapor deposition chamber to grow a lower strain applying layer 2 made of Si 1-x Ge x with x changed from 0.3 to 0.5 toward the growth direction. The thickness is 300 nm. Source materials used include Si 2 H 6 and GeH 4 and the layer is grown at a growing temperature of 700° C.
  • an upper strain applying layer 24 with 30 nm thickness made of Si 0.5 Ge 0.5 , a strained Ge layer 25 with 10 nm thickness, and a strained Si layer 1 with 13 nm thickness are similarly formed in the mentioned order so that they overlie each other.
  • the growth of the Si, Ge and SiGe layers is not limited to the chemical vapor deposition method. Any method capable of crystal growth having the above composition may be used.
  • the strained Ge layer 25 is subjected to an in-plane compressive strain and the strained Si layer 1 is subjected to an in-plane tensile strain. Thereby, both holes in the strained Ge layer 25 and electrons in the strained Si layer 1 have effective masses reduced as compared with those in ordinary Si so that the mobilities thereof are increased.
  • the ion implantation depth of the source/drain regions 17 and 18 is selected such that the depth for nMOS is 10 nm which is on the same order as the thickness of the strained Si layer 1 and the depth for pMOS is 20 nm which reaches the strained Ge layer 25 .
  • the strained Ge y layer is used for the channel.
  • a strained Si 1-y Ge y layer (0 ⁇ y ⁇ 1) with the mixture of Si may be used.
  • the composition ratio y is selected to be larger than the composition ration x of the Si 1-x Ge x strain applying layer.
  • FIG. 12 is the cross section of CMOSFET's according to the present embodiment.
  • an Si 0.5 Ge 0.5 barrier layer 30 with 2 nm is formed on the strained Si layer 1 in Embodiment 5.
  • the Si 0.5 Ge 0.5 barrier layer 30 is thus provided between the strained Si layer 1 and the gate insulating film 3 , electrons are not scattered at the interface between the strained Si layer 1 and the gate insulating film 3 or they are stored in the strained Si layer 1 in the vicinity of the interface between the Si 0.5 Ge 0.5 barrier layer 30 and the strained Si layer 1 .
  • the strained Si layer 1 is formed as an overlying layer on the strained Ge layer 25 .
  • this overlying sequence may be reversed.
  • the ion implantation depth of the source/drain regions 17 and 18 is selected such that the depth for nMOS is 12 nm which is on the same order as the thickness of the strained Si layer 1 and the depth for pMOS is 22 nm which reaches the strained Ge layer 25 .
  • FIG. 13 is the cross section of CMOSFET's according to the present embodiment.
  • the overlying arrangement of the strained Si layer 1 and the strained Ge layer 25 in Embodiment 5 is replaced by the juxtaposition or parallel arrangement.
  • strained Ge layer 25 with 10 nm for the pMOS area and a strained Si layer 1 with 12 nm for the nMOS area which are selectively grown on the SiO 0.5 Ge 0.5 strain applying layer 24 .
  • the strained Ge layer 25 is subjected to an in-plane compressive strain and the strained Si layer 1 is subjected to an in-plane tensile strain.
  • both holes in the strained Ge layer 25 and electrons in the strained Si layer 1 have effective masses reduced as compared with those in ordinary Si so that the mobilities thereof are increased.
  • FIG. 14 is the cross section of an SOI substrate according to the present embodiment.
  • the Si substrate 13 After an Si substrate 13 having an epitaxial layer 100 nm thick with high defect density formed on a surface thereof is cleaned, the Si substrate 13 is immediately introduced into a chemical vapor deposition chamber to grow an Si 1-x Ge x strain applying layer 2 .
  • the thickness is 150 nm.
  • Source materials used include Si 2 H 6 and GeH 4 and the layer is grown at a temperature of 700° C.
  • the growth of the Si and SiGe layers is not limited to the chemical vapor deposition. Any method capable of crystal growth having the above composition may be used.
  • oxygen ions are implanted from the upper side of the Si 1-x Ge x strain applying layer 2 under the conditions of the accelerating voltage of 180 KeV and the dosage of 4 ⁇ 10 17 /cm 2 ⁇ and the annealing is performed for 8 hours at 1350° C.
  • an SiO 2 insulating layer 26 is formed just below the Si 1-x Ge x strain applying layer 2 .
  • the thickness of the SiO 2 insulating layer 26 is about 100 nm so that a breakdown voltage equal to or higher than 50 V is ensured.
  • the Si 1-x Ge x strain applying layer 2 can have a very low defect density, a flatness and a sufficient strain relaxation.
  • a strained Si layer 1 with 60 nm thickness is formed on the layer 2 through a chemical vapor deposition.
  • Embodiment 1 of the present invention Thereafter, a process similar to that in Embodiment 1 of the present invention or the like can be used to manufacture CMOSFET's.
  • the use of the present substrate makes the ion implantation into well layers unnecessary.
  • the operating speed of the circuit containing the present CMOSFETs can be enhanced by about 40% as compared with that when an ordinary Si substrate is used.
  • FIG. 15 is the cross section of another embodiment of the SOI substrate.
  • an Si 1-x Ge x strain applying layer 2 is formed.
  • a strained Si layer 1 with 120 nm thickness is formed on the Si 1-x Ge x strain applying layer 2 through a chemical vapor deposition method.
  • oxygen ions are implanted from the upper side of the strained Si layer 1 under the conditions of the accelerating voltage of 50 KeV and the dosage of 2 ⁇ 10 17 /cm 2 and the annealing is performed for 8 hours at 1300° C.
  • an SiO 2 insulating layer 26 is formed into the strained Si layer 1 .
  • the thickness of the SiO 2 insulating layer 26 is about 30 nm.
  • the ion implantation into well layers becomes unnecessary.
  • the effluence of holes into the SiGe strain applying layer in pMOS is hard to happen. Therefore, it is not necessary to use that special measure for prevention of the effluence of holes which is based on the doping, the application of a bias, or the like.
  • FIGS. 16 a to 16 d are cross sections showing the manufacture steps of an SOI substrate according to the present embodiment.
  • a Si substrate 13 having an epitaxial layer 100 nm thick with high defect density formed on a surface thereof is introduced into a chemical vapor deposition chamber immediately after the cleaning thereof so that an Si 1-x Ge x strain applying layer 2 is grown, as shown in FIG. 16 a .
  • the thickness is 300 nm.
  • Source materials used include Si 2 H 6 and GeH 4 and the layer is grown at a growing temperature of 700° C.
  • the Ge composition ratio x of the Si 1-x Ge x strain applying layer 2 is arbitrarily controllable.
  • x is selected to be 0.3.
  • the growth of the Si and SiGe layers is not limited to the chemical vapor deposition method. Any method capable of crystal growth having the above composition may be used.
  • a Ge substrate or an SiGe mixed crystal substrate may be used in place of the Si substrate 13 . In the case where the Ge compositional ratio is large, the use of a Ge substrate or an SiGe substrate having a larger Ge content facilitates the growth of the Si 1-x Ge x strain applying layer 2 or makes it unnecessary.
  • the separating position 28 may lie in either the Si 1-x Ge x strain applying layer 2 or the strained Si layer 1 .
  • the surface oxide film and a separately prepared supporting substrate 29 are bonded to each other at a bonding position 27 , thereby resulting in a state shown in FIG. 16 b .
  • the annealing is made at 500° C., thereby causing the separation at the separating position 28 .
  • the separating position 28 lies in the Si 1-x Ge x strain applying layer 2
  • the separating position 28 lies in the strained Si layer 1
  • FIG. 16 d there results in a state as shown in FIG. 16 d .
  • an additional strained Si layer 1 with 60 nm is epitaxially grown on the surface.
  • the operating speed of the circuit containing the present CMOSFETs can be enhanced by about 40% as compared with that when an ordinary Si substrate is used.
  • pMOSFET's are fabricated with the ⁇ 100 ⁇ plane Si substrate 13 used and the Ge composition ratio x of the Si 1-x Ge x strain applying layer 2 variously changed.
  • the hole mobility along the ⁇ 001> direction in the strained Ge channel is estimated from the transconductance of the devices. As shown in Table 2, the mobility makes a rapid increase as there is subjected to the in-plane compressive strain.
  • the unit is % for strain (positive value for tensile strain) and cm 2 /Vs for mobility.
  • complementary field effect transistors are fabricated with the ⁇ 110 ⁇ plane Si substrate 13 used.
  • the electron and hole mobilities along the ⁇ 001> direction and the ⁇ 110> direction in the strained Si channel are estimated from the transconductance of the devices.
  • the electron mobility in the ⁇ 110> direction is larger than that in the ⁇ 001> direction.
  • the unit is % for strain (positive value for tensile strain) and cm 2 /Vs for mobility.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
US10/920,432 1999-03-30 2004-08-18 Semiconductor device and semiconductor substrate Abandoned US20050017236A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/920,432 US20050017236A1 (en) 1999-03-30 2004-08-18 Semiconductor device and semiconductor substrate
US12/010,123 US7579229B2 (en) 1999-03-30 2008-01-22 Semiconductor device and semiconductor substrate
US12/505,942 US8304810B2 (en) 1999-03-30 2009-07-20 Semiconductor device and semiconductor substrate having selectively etched portions filled with silicon germanium

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP11-087831 1999-03-30
JP08783199A JP4521542B2 (ja) 1999-03-30 1999-03-30 半導体装置および半導体基板
US53644600A 2000-03-28 2000-03-28
US10/920,432 US20050017236A1 (en) 1999-03-30 2004-08-18 Semiconductor device and semiconductor substrate

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US53644600A Continuation 1999-03-30 2000-03-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/010,123 Continuation US7579229B2 (en) 1999-03-30 2008-01-22 Semiconductor device and semiconductor substrate

Publications (1)

Publication Number Publication Date
US20050017236A1 true US20050017236A1 (en) 2005-01-27

Family

ID=13925896

Family Applications (3)

Application Number Title Priority Date Filing Date
US10/920,432 Abandoned US20050017236A1 (en) 1999-03-30 2004-08-18 Semiconductor device and semiconductor substrate
US12/010,123 Expired - Fee Related US7579229B2 (en) 1999-03-30 2008-01-22 Semiconductor device and semiconductor substrate
US12/505,942 Expired - Fee Related US8304810B2 (en) 1999-03-30 2009-07-20 Semiconductor device and semiconductor substrate having selectively etched portions filled with silicon germanium

Family Applications After (2)

Application Number Title Priority Date Filing Date
US12/010,123 Expired - Fee Related US7579229B2 (en) 1999-03-30 2008-01-22 Semiconductor device and semiconductor substrate
US12/505,942 Expired - Fee Related US8304810B2 (en) 1999-03-30 2009-07-20 Semiconductor device and semiconductor substrate having selectively etched portions filled with silicon germanium

Country Status (8)

Country Link
US (3) US20050017236A1 (zh)
EP (1) EP1174928A4 (zh)
JP (1) JP4521542B2 (zh)
KR (1) KR100447492B1 (zh)
CN (2) CN1210809C (zh)
AU (1) AU3330600A (zh)
TW (1) TW557577B (zh)
WO (1) WO2000060671A1 (zh)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030052334A1 (en) * 2001-06-18 2003-03-20 Lee Minjoo L. Structure and method for a high-speed semiconductor device
US20050151164A1 (en) * 2001-06-21 2005-07-14 Amberwave Systems Corporation Enhancement of p-type metal-oxide-semiconductor field effect transistors
US20050156246A1 (en) * 2002-06-07 2005-07-21 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator device structures
US20050199954A1 (en) * 2002-06-07 2005-09-15 Amberwave Systems Corporation Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain
US20060001088A1 (en) * 2004-07-01 2006-01-05 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US20060266997A1 (en) * 2001-08-09 2006-11-30 Amberwave Systems Corporation Methods for forming semiconductor structures with differential surface layer thicknesses
US20070032009A1 (en) * 2002-06-07 2007-02-08 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US20070072354A1 (en) * 2001-08-06 2007-03-29 Massachusetts Institute Of Technology Structures with planar strained layers
US20070290264A1 (en) * 2006-06-14 2007-12-20 Nobuyuki Sugii Semiconductor device and a method of manufacturing the same
DE102008062685A1 (de) * 2008-12-17 2010-06-24 Siltronic Ag Halbleiterscheibe mit einer SiGe-Schicht und Verfahren zur Herstellung der SiGe-Schicht
WO2013010828A1 (en) * 2011-07-18 2013-01-24 Epigan Nv Method for growing iii-v epitaxial layers
US9362273B2 (en) 2001-04-27 2016-06-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same

Families Citing this family (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784035B2 (en) * 2002-01-23 2004-08-31 Spinnaker Semiconductor, Inc. Field effect transistor having source and/or drain forming Schottky or Schottky-like contact with strained semiconductor substrate
US6528033B1 (en) * 2000-01-18 2003-03-04 Valence Technology, Inc. Method of making lithium-containing materials
US6602613B1 (en) 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6969875B2 (en) 2000-05-26 2005-11-29 Amberwave Systems Corporation Buried channel strained silicon FET using a supply layer created through ion implantation
EP1309989B1 (en) 2000-08-16 2007-01-10 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
US6649480B2 (en) 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
WO2002052652A1 (fr) * 2000-12-26 2002-07-04 Matsushita Electric Industrial Co., Ltd. Composant a semi-conducteur et son procede de fabrication
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6723661B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
AU2002322105A1 (en) 2001-06-14 2003-01-02 Amberware Systems Corporation Method of selective removal of sige alloys
AU2002319801A1 (en) 2001-08-09 2003-02-24 Amberwave Systems Corporation Optimized buried-channel fets based on sige heterostructures
ATE449420T1 (de) * 2001-08-09 2009-12-15 Amberwave Systems Corp Cmos bauelemente mit doppelter schicht
US6974735B2 (en) 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
JP2005504436A (ja) 2001-09-21 2005-02-10 アンバーウェーブ システムズ コーポレイション 画定された不純物勾配を有するひずみ材料層を使用する半導体構造、およびその構造を製作するための方法。
AU2002341803A1 (en) 2001-09-24 2003-04-07 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
JP2003115587A (ja) 2001-10-03 2003-04-18 Tadahiro Omi ＜１１０＞方位のシリコン表面上に形成された半導体装置およびその製造方法
DE10218381A1 (de) * 2002-04-24 2004-02-26 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer oder mehrerer einkristalliner Schichten mit jeweils unterschiedlicher Gitterstruktur in einer Ebene einer Schichtenfolge
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
EP2267762A3 (en) 2002-08-23 2012-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor heterostructures having reduced dislocation pile-ups and related methods
JP4546021B2 (ja) * 2002-10-02 2010-09-15 ルネサスエレクトロニクス株式会社 絶縁ゲート型電界効果型トランジスタ及び半導体装置
JP4190906B2 (ja) * 2003-02-07 2008-12-03 信越半導体株式会社 シリコン半導体基板及びその製造方法
US6887798B2 (en) 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
TWI242232B (en) 2003-06-09 2005-10-21 Canon Kk Semiconductor substrate, semiconductor device, and method of manufacturing the same
US7329923B2 (en) 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US7049898B2 (en) * 2003-09-30 2006-05-23 Intel Corporation Strained-silicon voltage controlled oscillator (VCO)
US20050116290A1 (en) * 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US7662689B2 (en) * 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
US7161169B2 (en) * 2004-01-07 2007-01-09 International Business Machines Corporation Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain
US7579636B2 (en) 2004-01-08 2009-08-25 Nec Corporation MIS-type field-effect transistor
WO2005067058A1 (ja) * 2004-01-08 2005-07-21 Nec Corporation Ｍｉｓ型電界効果トランジスタ
US7037794B2 (en) 2004-06-09 2006-05-02 International Business Machines Corporation Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain
US7227205B2 (en) * 2004-06-24 2007-06-05 International Business Machines Corporation Strained-silicon CMOS device and method
US6991998B2 (en) 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US7384829B2 (en) 2004-07-23 2008-06-10 International Business Machines Corporation Patterned strained semiconductor substrate and device
DE102004036971B4 (de) * 2004-07-30 2009-07-30 Advanced Micro Devices, Inc., Sunnyvale Technik zur Bewertung lokaler elektrischer Eigenschaften in Halbleiterbauelementen
JP2006108365A (ja) * 2004-10-05 2006-04-20 Renesas Technology Corp 半導体装置およびその製造方法
JP4604637B2 (ja) * 2004-10-07 2011-01-05 ソニー株式会社 半導体装置および半導体装置の製造方法
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7274084B2 (en) 2005-01-12 2007-09-25 International Business Machines Corporation Enhanced PFET using shear stress
US7432553B2 (en) 2005-01-19 2008-10-07 International Business Machines Corporation Structure and method to optimize strain in CMOSFETs
US7220626B2 (en) 2005-01-28 2007-05-22 International Business Machines Corporation Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels
US7470972B2 (en) 2005-03-11 2008-12-30 Intel Corporation Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress
US7291539B2 (en) 2005-06-01 2007-11-06 International Business Machines Corporation Amorphization/templated recrystallization method for hybrid orientation substrates
US7202513B1 (en) 2005-09-29 2007-04-10 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US7655511B2 (en) 2005-11-03 2010-02-02 International Business Machines Corporation Gate electrode stress control for finFET performance enhancement
US7564081B2 (en) 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
US7863197B2 (en) 2006-01-09 2011-01-04 International Business Machines Corporation Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
KR20090038653A (ko) * 2007-10-16 2009-04-21 삼성전자주식회사 Ｃｍｏｓ 소자 및 그 제조방법
US7842982B2 (en) 2008-01-29 2010-11-30 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
WO2010085754A1 (en) * 2009-01-23 2010-07-29 Lumenz Inc. Semiconductor devices having dopant diffusion barriers
JP5601848B2 (ja) * 2010-02-09 2014-10-08 三菱電機株式会社 ＳｉＣ半導体装置の製造方法
JP5703148B2 (ja) * 2011-07-04 2015-04-15 株式会社半導体エネルギー研究所 半導体装置
CN103377941B (zh) * 2012-04-28 2016-08-10 中芯国际集成电路制造(上海)有限公司 Pmos晶体管及形成方法
US20130334571A1 (en) * 2012-06-19 2013-12-19 International Business Machines Corporation Epitaxial growth of smooth and highly strained germanium
JP5695614B2 (ja) * 2012-08-22 2015-04-08 ルネサスエレクトロニクス株式会社 半導体装置
CN102967814B (zh) * 2012-10-19 2015-05-20 西安电子科技大学 晶体管晶格形变导致性能退化的测试装置及方法
US10032870B2 (en) 2015-03-12 2018-07-24 Globalfoundries Inc. Low defect III-V semiconductor template on porous silicon
FR3051596B1 (fr) 2016-05-17 2022-11-18 Soitec Silicon On Insulator Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant
FR3051595B1 (fr) * 2016-05-17 2022-11-18 Soitec Silicon On Insulator Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant
CN108766967B (zh) * 2018-05-23 2021-05-28 燕山大学 一种平面复合应变Si/SiGe CMOS器件及制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4878957A (en) * 1988-03-31 1989-11-07 Kabushiki Kaisha Toshiba Dielectrically isolated semiconductor substrate
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5384473A (en) * 1991-10-01 1995-01-24 Kabushiki Kaisha Toshiba Semiconductor body having element formation surfaces with different orientations
US5698869A (en) * 1994-09-13 1997-12-16 Kabushiki Kaisha Toshiba Insulated-gate transistor having narrow-bandgap-source
US5891769A (en) * 1997-04-07 1999-04-06 Motorola, Inc. Method for forming a semiconductor device having a heteroepitaxial layer
US6682965B1 (en) * 1997-03-27 2004-01-27 Sony Corporation Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5376769A (en) * 1976-12-20 1978-07-07 Toshiba Corp Simiconductor device
JPH03187269A (ja) * 1989-12-18 1991-08-15 Hitachi Ltd 半導体装置
JPH03280437A (ja) * 1990-03-29 1991-12-11 Toshiba Corp 半導体装置およびその製造方法
US5240876A (en) * 1991-02-22 1993-08-31 Harris Corporation Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process
US5461250A (en) 1992-08-10 1995-10-24 International Business Machines Corporation SiGe thin film or SOI MOSFET and method for making the same
JPH06177375A (ja) * 1992-12-10 1994-06-24 Hitachi Ltd 半導体装置及びその製造方法
US5344524A (en) * 1993-06-30 1994-09-06 Honeywell Inc. SOI substrate fabrication
US5461243A (en) * 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
JP3187269B2 (ja) 1994-12-12 2001-07-11 株式会社ホンダロック ロック装置
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
JPH0982944A (ja) * 1995-09-18 1997-03-28 Toshiba Corp 歪シリコン電界効果トランジスタ及びその製造方法
JP3376211B2 (ja) * 1996-05-29 2003-02-10 株式会社東芝 半導体装置、半導体基板の製造方法及び半導体装置の製造方法
US5847419A (en) * 1996-09-17 1998-12-08 Kabushiki Kaisha Toshiba Si-SiGe semiconductor device and method of fabricating the same
JP3262747B2 (ja) * 1996-09-17 2002-03-04 松下電器産業株式会社 半導体装置及びその製造方法
US6399970B2 (en) * 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
DE59707274D1 (de) * 1996-09-27 2002-06-20 Infineon Technologies Ag Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US6689211B1 (en) * 1999-04-09 2004-02-10 Massachusetts Institute Of Technology Etch stop layer system
JP2000277715A (ja) * 1999-03-25 2000-10-06 Matsushita Electric Ind Co Ltd 半導体基板，その製造方法及び半導体装置
US6326279B1 (en) * 1999-03-26 2001-12-04 Canon Kabushiki Kaisha Process for producing semiconductor article
US20020030227A1 (en) * 2000-01-20 2002-03-14 Bulsara Mayank T. Strained-silicon diffused metal oxide semiconductor field effect transistors

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4878957A (en) * 1988-03-31 1989-11-07 Kabushiki Kaisha Toshiba Dielectrically isolated semiconductor substrate
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5384473A (en) * 1991-10-01 1995-01-24 Kabushiki Kaisha Toshiba Semiconductor body having element formation surfaces with different orientations
US5698869A (en) * 1994-09-13 1997-12-16 Kabushiki Kaisha Toshiba Insulated-gate transistor having narrow-bandgap-source
US6682965B1 (en) * 1997-03-27 2004-01-27 Sony Corporation Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect
US5891769A (en) * 1997-04-07 1999-04-06 Motorola, Inc. Method for forming a semiconductor device having a heteroepitaxial layer

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9997543B2 (en) 2001-04-27 2018-06-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US9362273B2 (en) 2001-04-27 2016-06-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US7301180B2 (en) * 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
US8436336B2 (en) 2001-06-18 2013-05-07 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
US20030052334A1 (en) * 2001-06-18 2003-03-20 Lee Minjoo L. Structure and method for a high-speed semiconductor device
US20050151164A1 (en) * 2001-06-21 2005-07-14 Amberwave Systems Corporation Enhancement of p-type metal-oxide-semiconductor field effect transistors
US20070072354A1 (en) * 2001-08-06 2007-03-29 Massachusetts Institute Of Technology Structures with planar strained layers
US20060266997A1 (en) * 2001-08-09 2006-11-30 Amberwave Systems Corporation Methods for forming semiconductor structures with differential surface layer thicknesses
US20070032009A1 (en) * 2002-06-07 2007-02-08 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US8748292B2 (en) 2002-06-07 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming strained-semiconductor-on-insulator device structures
US20050156246A1 (en) * 2002-06-07 2005-07-21 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator device structures
US20050199954A1 (en) * 2002-06-07 2005-09-15 Amberwave Systems Corporation Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain
US20060001088A1 (en) * 2004-07-01 2006-01-05 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US20080220588A1 (en) * 2004-07-01 2008-09-11 International Business Machines Corporation STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI)
US7507989B2 (en) 2004-07-01 2009-03-24 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US8017499B2 (en) 2004-07-01 2011-09-13 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US20070155130A1 (en) * 2004-07-01 2007-07-05 International Business Machines Corporation STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI)
US20080042166A1 (en) * 2004-07-01 2008-02-21 International Business Machines Corporation STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI)
US7217949B2 (en) * 2004-07-01 2007-05-15 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US20070290264A1 (en) * 2006-06-14 2007-12-20 Nobuyuki Sugii Semiconductor device and a method of manufacturing the same
DE102008062685A1 (de) * 2008-12-17 2010-06-24 Siltronic Ag Halbleiterscheibe mit einer SiGe-Schicht und Verfahren zur Herstellung der SiGe-Schicht
WO2013010828A1 (en) * 2011-07-18 2013-01-24 Epigan Nv Method for growing iii-v epitaxial layers
US9230803B2 (en) 2011-07-18 2016-01-05 Epigan Nv Method for growing III-V epitaxial layers
US9748331B2 (en) 2011-07-18 2017-08-29 Epigan Nv Method for growing III-V epitaxial layers

Also Published As

Publication number Publication date
CN100386863C (zh) 2008-05-07
AU3330600A (en) 2000-10-23
US7579229B2 (en) 2009-08-25
CN1349662A (zh) 2002-05-15
JP4521542B2 (ja) 2010-08-11
JP2000286418A (ja) 2000-10-13
US8304810B2 (en) 2012-11-06
TW557577B (en) 2003-10-11
US20090283839A1 (en) 2009-11-19
KR20010110690A (ko) 2001-12-13
CN1716570A (zh) 2006-01-04
EP1174928A1 (en) 2002-01-23
KR100447492B1 (ko) 2004-09-07
US20080206961A1 (en) 2008-08-28
WO2000060671A1 (fr) 2000-10-12
CN1210809C (zh) 2005-07-13
EP1174928A4 (en) 2007-05-16

Similar Documents

Publication Publication Date Title
US7579229B2 (en) Semiconductor device and semiconductor substrate
JP4912123B2 (ja) 電界効果トランジスタを形成するための層状構造
US7208754B2 (en) Strained silicon structure
US5534713A (en) Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
KR100347623B1 (ko) 반도체장치
US7244972B2 (en) Semiconductor devices and method for manufacturing the same
EP1178532A2 (en) NMOS and PMOS with strained channel layer
US7465619B2 (en) Methods of fabricating dual layer semiconductor devices
US7393735B2 (en) Structure for and method of fabricating a high-mobility field-effect transistor
JP3512701B2 (ja) 半導体装置及びその製造方法
US7791107B2 (en) Strained tri-channel layer for semiconductor-based electronic devices
US7301180B2 (en) Structure and method for a high-speed semiconductor device having a Ge channel layer
JP2000031491A (ja) 半導体装置，半導体装置の製造方法，半導体基板および半導体基板の製造方法
JP3618319B2 (ja) 半導体装置及びその製造方法
JPH05114708A (ja) 半導体装置
JP2001044425A (ja) 半導体装置
JP2010141349A (ja) 半導体装置の製造方法
WO2002103801A1 (en) Structures and methods for a high-speed semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: RENESAS TECHNOLOGY CORP., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HITACHI, LTD.;REEL/FRAME:019881/0288

Effective date: 20070329

Owner name: RENESAS TECHNOLOGY CORP.,JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HITACHI, LTD.;REEL/FRAME:019881/0288

Effective date: 20070329

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION