CN108766967B - 一种平面复合应变Si/SiGe CMOS器件及制备方法 - Google Patents
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Abstract
一种平面复合应变Si/SiGe CMOS器件及制备方法，选取晶向为100的N掺杂的单晶Si衬底；在衬底上外延一层Ge组分渐变的SiGe层；在SiGe层表面外延一层Si0.85Ge0.15层；光刻Si0.85Ge0.15虚拟衬底右侧区域，赝晶生长一层应变Si0.69Ge0.30C0.01层；光刻应变Si0.69Ge0.30C0.01层，在两端嵌入Si0.5Ge0.5层，采用CMP技术将器件表面平面化；赝晶生长一层应变Si层；在器件中部形成STI结构；光刻并进行离子注入形成P阱和N阱；淀积栅氧化层和NMOS多晶硅层并光刻形成NMOS栅结构；在NMOS的两端形成嵌入SiC层，进行离子注入形成源/漏区；淀积PMOS多晶硅栅，光刻多晶硅栅，利用自对准工艺形成PMOS的源/漏区。本发明在NMOS和PMOS沟道区同时采用单轴和双轴复合应变，大幅度提高载流子的移率和器件工作速度，整个器件均采用平面工艺，和已有的硅工艺兼容，可实现大规模集成。
Description
技术领域
本发明涉及半导体集成电路技术领域，尤其涉及一种平面复合应变Si/SiGe CMOS器件及其制备方法。
背景技术
随着微电子技术的高速发展，硅基集成电路的速度及性能已接近其工艺技术、材料与器件物理的极限。为支撑摩尔定理的持续发展，一种新技术—应变硅技术应运而生，应变硅器件及电路以其速度快，性能高等特点，已成为高速/高性能集成电路研究、应用的前沿与发展方向，以集成电路为代表的微电子技术已进入应变技术新时代。
目前国际上在小尺寸MOS器件中采用的成熟应变硅技术是局部应变，即单轴应变技术。局部应力的引入主要通过两种方法：一种方法是通过器件表面淀积SiN薄膜在MOSFET沟道形成应变Si的DSL(Dual Stress Liner，双应力衬垫)；另一种是采用源漏区嵌入SiGe而形成应变Si沟道。然而采用该方法引入的应力，受到工艺条件的制约，应力的大小受到了很大限制，使得载流子的迁移率及器件的频率特性提高幅度只有10％左右。因此，从工艺技术的角度考虑，完全可以将全局应变，即双轴应力引入到小尺寸MOS器件结构中，进而可以通过合理改变器件的能带结构与材料物理参数，进一步提高器件的高频特性。该方法完全和已有的硅工艺兼容，同时兼顾工艺成本，可以满足高频SOC系统对器件性能的要求。
发明内容
本发明目的在于提供一种大幅度提高载流子迁移率、提高器件工作速度的可工作于高频的平面复合应变Si/SiGe CMOS器件及制备方法。
为实现上述目的，采用了以下技术方案：本发明所述器件选取晶向为100的N掺杂的单晶Si衬底；在N掺杂的单晶Si衬底上外延一层Ge组分渐变的SiGe层，顶层的Ge组分为15％；在渐变SiGe层表面外延一层Si0.85Ge0.15层作为虚拟衬底；光刻Si0.85Ge0.15虚拟衬底右侧区域，并赝晶生长一层应变Si0.69Ge0.30C0.01层；光刻应变Si0.69Ge0.30C0.01层，在应变Si0.69Ge0.30C0.01层的两端嵌入Si0.5Ge0.5层，采用CMP技术对所形成的器件表面平面化；接着赝晶生长一层应变Si层；在器件中部形成STI结构；光刻并进行离子注入分别形成P阱和N阱；淀积栅氧化层和NMOS多晶硅层并光刻，形成NMOS栅结构；采用自对准工艺及嵌入式SiC技术，在NMOS的两端形成嵌入SiC层，同时进行离子注入形成源/漏区；淀积PMOS多晶硅栅，并光刻多晶硅栅，利用自对准工艺，进行离子注入形成PMOS的源/漏区。
进一步的，在NMOS器件中采用嵌入式SiC工艺，结合SiGe虚拟衬底赝晶生长的应变Si层，在沟道中同时引入了双轴和单轴的复合应变，因此进一步提高了电子的迁移率，提高了NMOS器件的频率特性；
进一步的，PMOS器件中两端，采用嵌入SiGe工艺及在SiGe虚拟衬底上赝晶生长Si0.69Ge0.30C0.01层，在埋沟层中同时引入了单轴和双轴压应变。同时，1％组分C的引入可以保证应变Si0.69Ge0.30C0.01的晶格完整性，降低载流子的传输散射，提高载流子迁移率，提高PMOS的速度及其频率特性。
一种平面复合应变Si/SiGe CMOS器件制备方法，步骤如下：
步骤1，选取单晶硅掺杂浓度为1015cm-3晶向为100的N型Si为初始材料，作为衬底；
步骤2，在N掺杂的单晶Si衬底上的外延一层Ge组分渐变的SiGe层，顶层的Ge组分为15％；
步骤3，在渐变SiGe层表面外延一层Ge组分固定为15％的Si0.85Ge0.15层作为虚拟衬底；
步骤4，光刻Si0.85Ge0.15虚拟衬底右侧区域，并赝晶生长一层应变Si0.69Ge0.30C0.01层；
步骤5，光刻应变Si0.69Ge0.30C0.01层，在应变Si0.69Ge0.30C0.01层的两端嵌入Si0.5Ge0.5层，并采用CMP技术，将所形成的器件表面平面化；
步骤6，在步骤5形成的器件表面，赝晶生长一层应变Si层；
步骤7，在器件中部形成STI结构，以实现NMOS和PMOS的隔离；
步骤8，光刻并进行离子注入形成P阱；
步骤9，光刻并进行离子注入形成N阱；
步骤10，淀积栅氧化层；
步骤11，淀积NMOS多晶硅栅，并光刻形成NMOS栅结构；
步骤12，采用自对准工艺以及嵌入式SiC技术，在NMOS的两端形成嵌入SiC层，同时进行离子注入形成源/漏区；
步骤13，淀积PMOS多晶硅栅，并光刻多晶硅栅，利用自对准工艺，进行离子注入形成PMOS的源/漏区。
与现有技术相比，本发明具有如下优点：将成熟的CMOS工艺以及“硅基应变技术”这二者有机结合，通过在NMOS和PMOS的沟道区域同时引入单轴和双轴应力来形成一种新的平面复合应变Si/SiGe CMOS新结构，沟道区复合应力的引入均可以大幅提高载流子的迁移率，从而提高器件的高频特性；尤其在PMOS沟道区，采用埋沟结构以及应变Si0.69Ge0.30C0.01层，1％C的引入可以提高晶格完整性，降低载流子的传输散射，进一步提高空穴迁移率，提高PMOS的速度及其频率特性。
附图说明
图1是本发明CMOS器件的剖面示意图。
图2a—图2l为本发明CMOS器件的制备方法示意图。
附图标号：100-N型Si衬底、101-渐变SiGe层、102-Si0.85Ge0.15虚拟衬底、103-应变Si0.69Ge0.30C0.01层、104-嵌入Si0.5Ge0.5层、105-应变Si层、106-STI结构、107-P阱、108-N阱、109-栅氧化层、110-NMOS多晶硅栅、111-嵌入SiC层、112-PMOS多晶硅栅、113-PMOS源/漏区。
具体实施方式
下面结合附图对本发明做进一步说明：
如图1所示，本发明所述晶体管选取晶向为(100)的N掺杂的单晶Si衬底；在所述的N掺杂的单晶Si衬底上的外延一层Ge组分渐变的SiGe层，顶层的Ge组分为15％；在渐变SiGe层表面外延一层Si0.85Ge0.15层作为虚拟衬底；光刻Si0.85Ge0.15虚拟衬底右侧区域，并赝晶生长一层应变Si0.69Ge0.30C0.01层；光刻应变Si0.69Ge0.30C0.01层，在应变Si0.69Ge0.30C0.01层的两端嵌入Si0.5Ge0.5层，并采用CMP技术，将器件表面平面化；接着赝晶生长一层应变Si层；在器件中部形成STI结构；光刻并进行离子注入分别形成P阱和N阱；淀积栅氧化层和NMOS多晶硅层并光刻形成NMOS栅结构；采用自对准工艺以及嵌入式SiC技术，在NMOS的两端形成嵌入SiC层，同时进行离子注入形成源/漏区；淀积PMOS多晶硅栅，并光刻多晶硅栅，利用自对准工艺，进行离子注入形成PMOS的源/漏区。
一种平面复合应变Si/SiGeCMOS器件制备方法，制备步骤如下：
步骤1，N掺杂的Si衬底100，如图2a所示；选取单晶硅掺杂浓度为1015cm-3晶向为(100)的N型Si为初始材料，作为衬底；
步骤2，在N掺杂的单晶Si衬底上的外延一层Ge组分渐变的SiGe层101，如图2b所示，顶层的Ge组分为15％；
步骤3，在渐变SiGe层表面外延一层Ge组分固定为15％的Si0.85Ge0.15层102作为虚拟衬底，如图2c所示；
步骤4，采用Mask1，光刻Si0.85Ge0.15虚拟衬底102右侧区域，并赝晶生长一层应变Si0.69Ge0.30C0.01层103，如图2d所示；
赝晶生长的Si0.69Ge0.30C0.01层103，其晶格常数和Si0.85Ge0.15虚拟衬底102的晶格常数保持一致，因此在Si0.69Ge0.30C0.01层103中引入了压应变，压应变的引入使得空穴的有效质量降低、迁移率提高，因此可以提高PMOS的速度及其频率特性；同时，1％组分C的引入可以保证应变Si0.69Ge0.30C0.01的晶格完整性，降低载流子的传输散射，提高载流子迁移率。
步骤5，采用Mask2，光刻应变Si0.69Ge0.30C0.01层103，采用嵌入式SiGe技术，在应变Si0.69Ge0.30C0.01层103的两端嵌入Si0.5Ge0.5层104，并采用CMP技术，将器件表面平面化，如图2e所示；
由于Si0.5Ge0.5和Si0.69Ge0.30C0.01晶格常数和热膨胀系数的差异，沿着PMOS沟道方向，引入了单轴压应力；这样就在应变应变Si0.69Ge0.30C0.01层103中形成了沿着沟道方向的复合压应变；复合应变的引入，进一步提高了空穴的迁移率和PMOS器件的工作速度；
步骤6，在步骤5形成的器件表面，赝晶生长一层应变Si层105，如图2f所示；
由于Si和SiGe的晶格差异，通过控制工艺条件，赝晶生长的Si层和底层的SiGe层晶格常数一致，因此在Si层中引入了张应变；张应变的引入，降低了电子的有效质量，提高了电子的迁移率，所以可以提高NMOS器件的工作速度；
步骤7，采用Mask3和Mask4，在器件中部形成STI结构106，如图2g所示，该结构用于NMOS和PMOS的隔离；
步骤8，采用Mask5，光刻并进行离子注入形成P阱107，如图2h所示；
步骤9，采用Mask5，光刻并进行离子注入形成N阱108，如图2i所示；
步骤10，淀积栅氧化层109，如图2j所示；
步骤11，淀积NMOS多晶硅栅110，并采用Mask6，光刻形成NMOS栅结构，如图2k所示；
步骤12，采用自对准工艺以及嵌入式SiC技术，在NMOS的两端形成嵌入SiC层111，如图2l所示，同时进行离子注入形成源/漏区，；
由于SiC和Si晶格的差异，在Si沟道引入了沿着沟道方向的单轴张应变；这样就在NMOS的应变Si层形成了复合应变结构；复合张应变的引入，进一步提高了电子的迁移率，进而提高了NMOS器件的频率特性；
步骤13，淀积PMOS多晶硅栅112，采用Mask6，光刻多晶硅栅112，并利用自对准工艺，进行离子注入形成PMOS的源/漏区113，如图1所示。
以上所述的实施例仅仅是对本发明的优选实施方式进行描述，并非对本发明的范围进行限定，在不脱离本发明设计精神的前提下，本领域普通技术人员对本发明的技术方案做出的各种变形和改进，均应落入本发明权利要求书确定的保护范围内。
Claims (4)
1.一种平面复合应变Si/SiGe CMOS器件，其特征在于：所述器件选取晶向为100的N掺杂的单晶Si衬底；在N掺杂的单晶Si衬底上外延一层Ge组分渐变的SiGe层，顶层的Ge组分为15％；在渐变SiGe层表面外延一层Si0.85Ge0.15层作为虚拟衬底；光刻Si0.85Ge0.15虚拟衬底右侧区域，并赝晶生长一层应变Si0.69Ge0.30C0.01层；光刻应变Si0.69Ge0.30C0.01层，在应变Si0.69Ge0.30C0.01层的两端嵌入Si0.5Ge0.5层，采用CMP技术对所形成的器件表面平面化；接着赝晶生长一层应变Si层；在器件中部形成STI结构；光刻并进行离子注入分别形成P阱和N阱；淀积栅氧化层和NMOS多晶硅层并光刻，形成NMOS栅结构；采用自对准工艺及嵌入式SiC技术，在NMOS的两端形成嵌入SiC层，同时进行离子注入形成源/漏区；淀积PMOS多晶硅栅，并光刻多晶硅栅，利用自对准工艺，进行离子注入形成PMOS的源/漏区。
2.根据权利要求1所述的平面复合应变Si/SiGe CMOS器件，其特征在于：在NMOS器件中采用嵌入式SiC工艺，结合SiGe虚拟衬底赝晶生长的应变Si层，在沟道中同时引入了双轴和单轴的复合应变。
3.根据权利要求1所述的平面复合应变Si/SiGe CMOS器件，其特征在于：在PMOS器件中两端，采用嵌入SiGe工艺及在SiGe虚拟衬底上赝晶生长Si0.69Ge0.30C0.01层，在埋沟层中同时引入了单轴和双轴压应变。
4.一种平面复合应变Si/SiGe CMOS器件制备方法，其特征在于，所述制备步骤如下：
步骤1，选取单晶硅掺杂浓度为1015cm-3晶向为100的N型Si为初始材料，作为衬底；
步骤2，在N掺杂的单晶Si衬底上的外延一层Ge组分渐变的SiGe层，顶层的Ge组分为15％；
步骤3，在渐变SiGe层表面外延一层Ge组分固定为15％的Si0.85Ge0.15层作为虚拟衬底；
步骤4，光刻Si0.85Ge0.15虚拟衬底右侧区域，并赝晶生长一层应变Si0.69Ge0.30C0.01层；
步骤5，光刻应变Si0.69Ge0.30C0.01层，在应变Si0.69Ge0.30C0.01层的两端嵌入Si0.5Ge0.5层，并采用CMP技术，将所形成的器件表面平面化；
步骤6，在步骤5形成的器件表面，赝晶生长一层应变Si层；
步骤7，在器件中部形成STI结构，以实现NMOS和PMOS的隔离；
步骤8，光刻并进行离子注入形成P阱；
步骤9，光刻并进行离子注入形成N阱；
步骤10，淀积栅氧化层；
步骤11，淀积NMOS多晶硅栅，并光刻形成NMOS栅结构；
步骤12，采用自对准工艺以及嵌入式SiC技术，在NMOS的两端形成嵌入SiC层，同时进行离子注入形成源/漏区；
步骤13，淀积PMOS多晶硅栅，并光刻多晶硅栅，利用自对准工艺，进行离子注入形成PMOS的源/漏区。
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