US20020173069A1 - Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device - Google Patents

Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device Download PDF

Info

Publication number
US20020173069A1
US20020173069A1 US09/958,094 US95809401A US2002173069A1 US 20020173069 A1 US20020173069 A1 US 20020173069A1 US 95809401 A US95809401 A US 95809401A US 2002173069 A1 US2002173069 A1 US 2002173069A1
Authority
US
United States
Prior art keywords
semiconductor chip
insulated substrate
semiconductor device
protective resin
mounting structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/958,094
Other languages
English (en)
Inventor
Kazutaka Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Assigned to ROHM CO., LTD. reassignment ROHM CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHIBATA, KAZUTAKA
Publication of US20020173069A1 publication Critical patent/US20020173069A1/en
Priority to US11/065,070 priority Critical patent/US7285446B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a mounting structure of a semiconductor chip onto a polyimide substrate, a semiconductor device having this mounting structure and a method of manufacturing this semiconductor device.
  • a semiconductor device 7 shown in this figure comprises a semiconductor chip 70 and an insulated substrate 71 .
  • the semiconductor chip 70 has a mounting surface 70 a , which is connected with a surface 71 a of the insulated substrate 71 via an adhesive 72 such as an epoxy resin.
  • the semiconductor chip 70 has electrodes 70 b faced onto and electrically connected with connecting terminals 71 b of the insulated substrate 71 .
  • the insulated substrate 71 is a flexible film of e.g.
  • each of the connecting terminals 71 b is electrically connected with a solder terminal 72 formed on the other side of the insulated substrate 71 .
  • the semiconductor chip 70 has side surfaces 70 c surrounded by a protective resin 73 provided by e.g. an epoxy resin.
  • the solder terminals 72 are disposed in a grid pattern correspondingly to the through holes 71 c , and specifically called BGA (Ball Grid Array).
  • the protective resin 73 is formed by first applying the epoxy resin which is not yet fully hardened in thermosetting process, to enclose the side surfaces 70 c of the semiconductor chip 70 , and then heating at a temperature of 150° C. through 200° C. to complete the thermosetting process.
  • the protective resin 73 shrinks as it is thermally set, and shrinks further as it is cooled down to the room temperature.
  • the insulated substrate 71 also shrinks. However, an amount of shrinkage in the insulated substrate 71 is smaller than that of the protective resin 73 , since the insulated substrate 71 is formed of polyimide resin which is superior to the protective resin 73 (epoxy resin) in terms of heat resistance and has a smaller coefficient of thermal shrinkage.
  • the insulated substrate 71 is flexible, the insulated substrate 71 is sometimes warped when the epoxy resin cools after the thermal setting. If the insulated substrate 71 is warped, the insulated substrate 71 can no longer sit horizontally, and when placed, the solder terminals 72 closer to the edge of the insulated substrate 71 are raised higher. This potentially causes an open circuit when the semiconductor device 7 is mounted onto a circuit substrate for example.
  • the adhesive 74 which connects the semiconductor chip 70 with the insulated substrate 71 is commonly provided by an epoxy resin. Therefore, again due to difference in the amount of thermal shrinkage between the insulated substrate 71 and the adhesive 74 , interfaces of the adhesive 74 with the insulated substrate 71 and with the semiconductor chip 70 come under a certain strain. Therefore, according to the mounting structure as in the semiconductor device 7 shown in FIG. 12, in which an electrode bearing surface (the mounting surface) 70 a is faced to the insulated substrate 71 , the circuit element of the semiconductor chip 70 comes under the strain, and could be damaged.
  • Another object of the present invention is to provide a semiconductor device having such a mounting structure.
  • Still another object of the present invention is to provide a method for favorably manufacturing the semiconductor device having such a mounting structure.
  • a first aspect of the present invention provides a mounting structure of a semiconductor chip onto an insulated substrate, in which the insulated substrate is made of a polyimide resin, at least a side surface of the semiconductor chip is protected by a protective resin provided by a polyimide resin, and the semiconductor chip is held by the protective resin with respect to the insulated substrate.
  • the semiconductor chip as mounted has its side surface protected. Further, since the semiconductor chip is held with respect to the insulated substrate, by a polyimide resin which is the same kind of resin that provides the insulated substrate, the following effects are obtained. First, the warp in the insulated substrate can be avoided. This is because the insulated substrate and the polyimide resin that encloses the semiconductor chip expand to a more or less the same extent if heated, and shrink to a more or less the same extent when cooled, in a process such as mounting the semiconductor chip. Second, a high level of adhesion is achieved between the insulated substrate and the resin that encloses the semiconductor chip, making possible to favorably keep a state of holding (state of mounting) and a state of protection of the semiconductor chip.
  • the protective resin rides on an upper surface of the semiconductor chip.
  • This arrangement offers the following effects.
  • the protective resin may seal the semiconductor chip entirely.
  • an adhesive layer is provided between the semiconductor chip and the insulated substrate. If the semiconductor chip is formed with a bump, and the mounting to the insulated substrate is made in a facedown mode, a gap is formed between the semiconductor chip and the insulated substrate. The presence of the adhesive layer in this gap enables to avoid air inclusion in the gap, preventing such a problem that the air in the gap expands when the semiconductor chip and/or the insulated substrate are heated, causing a strain onto a circuit element in the semiconductor chip and damage the circuit element.
  • the adhesive layer is provided by a polyimide resin.
  • Polyimide resin has a superior heat resistance and a smaller coefficient of thermal expansion than epoxy resin. Therefore, even if the adhesive layer between the circuit element and the insulated substrate is made of a polyimide resin, an influence (strain) of the resin expansion and shrinkage caused by heating and cooling, on the circuit element in the semiconductor chip is smaller than in the case where an epoxy resin is used.
  • the insulated substrate has a peripheral margin extending beyond the semiconductor chip, and the protective resin is formed to rise from the margin.
  • the semiconductor chip has an electrode bearing surface formed with a plurality of electrodes, and the insulated substrate is provided with external terminals disposed in a grid pattern, each made of a solder ball and electrically connected with a corresponding one of the electrodes.
  • the electrode bearing surface may be faced to the insulated substrate when the semiconductor chip is mounted onto the insulated substrate.
  • the electrode bearing surface may be faced away from the insulated substrate, and the electrical connection of each electrode of the semiconductor chip with the corresponding external terminal is provided by a wire.
  • a second aspect of the present invention offers a semiconductor device comprising an insulated substrate and a semiconductor chip mounted on the insulated substrate.
  • the insulated substrate is made of a polyimide resin
  • at least a side surface of the semiconductor chip is protected by a protective resin provided by a polyimide resin
  • the semiconductor chip is held by the protective resin with respect to the insulated substrate.
  • a third aspect of the present invention offers a method of manufacturing a semiconductor device, comprising steps of: mounting a semiconductor chip on an insulated substrate; and covering at least a side surface of the semiconductor chip with a protective resin, thereby holding the semiconductor chip with respect to the insulated substrate.
  • the method is characterized in that the protective resin is formed by thermal imidization of a liquid polyamide precursor.
  • the mounting of the semiconductor chip to the insulated substrate includes steps of: forming a non-hardened or semi-hardened adhesive layer on the insulated substrate; and pressing the semiconductor chip onto the insulated substrate under heat via the adhesive layer. Further, it is advantageous if ultrasonic wave is applied to the semiconductor chip when pressing the semiconductor chip onto the insulated substrate under heat via the adhesive layer.
  • FIG. 1 is an overall perspective view of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is an overall perspective view of the semiconductor device in FIG. 1 viewed from a back side.
  • FIG. 3 is a sectional view taken in lines III-III in FIG. 1 .
  • FIG. 4 is a perspective view showing a principal portion of a carrier tape used in manufacture of the semiconductor device shown in FIGS. 1 through 3.
  • FIGS. 5 through 9 are sectional views illustrating steps of manufacture of the semiconductor device shown in FIGS. 1 through 3.
  • FIG. 10 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 11 is a sectional view of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 12 is a sectional view of a prior art semiconductor device.
  • FIGS. 1 through 3 show a semiconductor device according to a first embodiment of the present invention.
  • the semiconductor device according to the present embodiment has a structure so called BGA (Ball Grid Array).
  • a semiconductor device 1 according to the first embodiment comprises an insulated substrate 2 , and a semiconductor chip 3 mounted on an upper surface 2 a of the insulated substrate 2 .
  • the insulated substrate 2 and the semiconductor chip 3 sandwich an adhesive layer 4 in between.
  • the semiconductor chip 3 is generally a rectangular parallelepiped, including an electrode bearing surface (the bottom surface in the figure) 3 a , an upper surface 3 b , and four side surfaces 3 c .
  • the side surface 3 c of the semiconductor chip 3 is enclosed by a protective resin 5 .
  • the insulated substrate 2 has a back surface 2 b provided with a plurality of external terminals 9 projecting from the surface and disposed in a grid pattern. Each of the external terminals 9 is ball-shaped.
  • the semiconductor chip 3 is a bear chip such as an IC chip and an LSI chip.
  • the electrode bearing surface 3 a is formed with a plurality of electrodes 30 .
  • Each of the electrodes 30 includes an electrode pad 30 a formed integrally with the semiconductor chip 3 and a bump 30 b formed by e.g. gold plating on the terminal pad 30 a .
  • the bump 30 b projects out of the electrode bearing surface 3 a.
  • the insulated substrate 2 is made of a polyimide resin. As shown clearly in FIG. 2 and FIG. 3, the upper surface 2 a and the back surface 2 b of the insulated substrate 2 are both generally rectangular. The upper surface 2 a and the back surface 2 b of the insulated substrate 2 each has an area greater than that of the electrode bearing surface 3 a . Thus, once the insulated substrate 2 is mounted with the semiconductor chip 3 , the insulated substrate 2 has its peripheral margins 23 extend beyond the semiconductor chip 3 .
  • the insulated substrate 2 is formed with a plurality of through holes 20 in a grid pattern. Further, the upper surface 2 a of the insulated substrate 2 is formed with a plurality of connecting terminals 21 each connected with a corresponding one of the-electrodes 30 of the semiconductor chip 3 . Though not clearly shown in the figures, each of the connecting terminals 21 has an end faced to the corresponding electrode 30 and another end extending to a corresponding through hole 20 , closing an upper opening of the through hole 20 . Further, as clearly shown in FIG. 3, each of the external terminals 9 fills a corresponding one of the through holes 20 and connects with a corresponding one of the connecting terminals 21 .
  • the adhesive layer 4 is provided by e.g. an epoxy resin, connecting the electrode bearing surface 3 a of the semiconductor chip 3 with the upper surface 2 a of the insulated substrate 2 .
  • the adhesive layer 4 may be formed of a polyimide resin, or may be formed of an electrically conductive anisotropic adhesive.
  • the electrically conductive anisotropic adhesive can bond, with its resin component, the semiconductor chip to the insulated substrate whereas its electrically conductive particles provide electrical connection between the electrode of the semiconductor chip and the connecting terminal of the insulated substrate.
  • a common resin component for the electrically conductive anisotropic adhesive is an epoxy resin, which may be replaced by a polyimide resin, however.
  • the protective resin 5 is provided by a polyimide resin, completely coats the extended margins 23 of the upper surface 2 a of the insulated substrate 2 and the side surfaces 3 c of the semiconductor chip 3 , and rides on an outer edges of the upper surface 3 b of the semiconductor chip 3 .
  • the margins 23 of the insulated substrate 2 and the upper surface 3 b of the semiconductor chip 3 are integrally connected by the protective resin 5 .
  • the insulated substrate 2 is made of polyimide resin, and thus has a high level of adhesion with the polyimide protective resin 5 .
  • the polyimide resin which has a good heat resistance and a small thermal expansion coefficient, does not expand very much when the semiconductor device 1 is mounted and driven on a circuit substrate for example.
  • the thermal expansion causes only a small stress acting on a place where the semiconductor device 1 is bonded, making possible to keep a stable state of operation.
  • the side surfaces 3 c of the semiconductor chip 3 and the edges of the upper surface 3 b are directly protected by the protective resin 5 . Therefore, if an external force is applied to the semiconductor chip 3 when handling the semiconductor device 1 , damage to the semiconductor chip 3 is small. Further, since the margins 23 of the insulated substrate 2 is integrated with the semiconductor chip 3 by the protective resin 5 , the margins 23 is not prone to direct influence of external force. This appropriately prevents such a situation in which the insulated substrate 2 comes off the semiconductor chip 3 due to external force acting on the margins 23 of the insulated substrate 2 .
  • the semiconductor device 1 is manufactured by using a carrier tape 2 A shown in FIG. 4.
  • the carrier tape 2 A is like a long ribbon, and includes, at a predetermined longitudinal pitch, a plurality of square unit regions 25 (regions surrounded by imaginative lines in FIG. 4) each to be mounted with the semiconductor chip 3 .
  • the carrier tape 2 A is formed of a polyimide resin.
  • the through holes 20 are formed in a grid pattern, on which the connecting terminals 21 are formed.
  • These connecting terminals 21 are formed for example by first forming and then etching a film of metal such as cupper on the surface of the carrier tape 2 A.
  • the metal film may be formed by plating, vapor deposition, or bonding a foil of metal.
  • the foil may have a pattern formed in advance.
  • Each of the connecting terminals 21 has an end positioned to corresponding one of the electrodes 30 of the semiconductor chip 3 , and another end closing a corresponding one of the through holes 20 from above.
  • the carrier tape 2 A has two widthwise margins each formed with a plurality of engaging holes 24 at a predetermined interval. By using these engaging holes 24 , the carrier tape 2 A is transported on an appropriate table.
  • the carrier tape 2 A When manufacturing the semiconductor device 1 by using the carrier tape 2 A as described, first, as shown in FIG. 4 and FIG. 5, the carrier tape 2 A is placed on a table 6 incorporating a heater (not illustrated). Under this state, the semiconductor chip 3 is mounted, in a facedown mode, onto each unit region 25 of the carrier tape 2 A via an adhesive sheet 4 . In this step, each electrode 30 of the semiconductor chip 3 must be faced to the corresponding end of the connecting terminals 21 in the unit region 25 .
  • the adhesive tape 4 is provided by a half-hardened epoxy resin or polyimide resin. Alternatively to the adhesive sheet 4 , a liquid adhesive may be applied to the unit region 25 or the electrode bearing surface 3 a of the semiconductor chip 3 , before the semiconductor chip 3 is mounted onto the unit region 25 .
  • the semiconductor chip 3 is pressed onto the carrier tape 2 A, whereby mounting of the semiconductor chip 3 onto the carrier tape 2 A is achieved.
  • ultrasonic wave is applied to the semiconductor chip 3 to make sure the contact between the electrodes 30 of the semiconductor chip 3 and the carrier tape 2 A.
  • the protective resin 5 is formed by enclosing the surrounds of the adhesive 4 , and the side surfaces 3 c of the semiconductor chip 3 .
  • the protective resin 5 is formed for example by first applying a liquid polyamide precursor, i.e. poly amicacid (a polymer of acid anhydride and diamine before cyclization (hardening)) carried in a solvent, thereby enclosing the side surfaces 3 c of the semiconductor chip and covering the edges of the upper surface 3 b of the semiconductor chip 3 . Then, the precursor is heated to cause imidization.
  • the protective resin 5 thus formed offers the following advantages since it is made of polyimide resin as is the carrier tape 2 A (the insulated substrate 2 ).
  • the carrier tape 2 A does not warp when the protective resin 5 is cooled after the thermal formation process, because the protective resin 5 and the carrier tape 2 A shrink to a more or less the same extent.
  • the carrier tape 2 A is turned upside down, and the external terminals 9 are formed in a grid pattern on the back surface of the carrier tape 2 A, corresponding to the grid pattern of the through holes 20 of the carrier tape 2 A.
  • a solder ball 90 is placed with solder flux (not illustrated) in each of the through holes 20 , and then the solder ball 90 is heated into molten and then cooled to solidify.
  • solder flux not illustrated
  • the carrier tape 2 A and the protective resin 5 are heated and then cooled, but since both are formed of polyimide resin, and therefore expand and shrink to a more or less the same extent, the carrier tape 2 A is not prone to warp.
  • the semiconductor device 1 When utilized, the semiconductor device 1 is mounted on e.g. a circuit substrate (not illustrated) formed with a predetermined wiring, together with other electronic components.
  • the mounting of the semiconductor device 1 onto the circuit substrate is performed by first placing the semiconductor device 1 , with its external terminals 9 faced to corresponding terminals formed on the circuit substrate, re-melting and then re-solidifying the external terminals 9 .
  • FIG. 10 shows a semiconductor device 1 ′ according to a second embodiment of the present invention.
  • the semiconductor device according to the present embodiment is similar to the semiconductor device 1 according to the first embodiment, but differs from the first embodiment in that the protective resin 5 ′ is formed to cover not only the side surfaces 3 c and the edges of the upper surface 3 b of the semiconductor chip 3 but also the entire upper surface 3 b of the semiconductor chip 3 .
  • the protective resin 5 ′ as described can be formed e.g. by means of transfer forming using a metal mold, and of course may be formed by means of potting, in which a liquid polyamide precursor is applied to cover the chip and then thermally hardened, into a dome-like shape.
  • FIG. 11 shows a semiconductor device 1 ′′ according to a third embodiment of the present invention.
  • the semiconductor device 1 ′′ according to the present embodiment is similar to the semiconductor device 1 ′ according to the second embodiment, but differs from the second embodiment in that the semiconductor chip 3 is mounted on the insulated substrate 2 in a face-up mode, that electrical connection between each electrode of the semiconductor chip 3 and a corresponding connecting terminal 21 of the insulated substrate 2 are provided by a wire W, and that the protective resin 5 ′ encloses the wires W, too.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
US09/958,094 2000-02-07 2001-02-06 Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device Abandoned US20020173069A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/065,070 US7285446B2 (en) 2000-02-07 2005-02-25 Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000-28818 2000-02-07
JP2000028818A JP2001217354A (ja) 2000-02-07 2000-02-07 半導体チップの実装構造、および半導体装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2001/000829 A-371-Of-International WO2001059839A1 (en) 2000-02-07 2001-02-06 Mounting structure for semiconductor chip, semiconductor device, and method of manufacturing semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/065,070 Division US7285446B2 (en) 2000-02-07 2005-02-25 Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device

Publications (1)

Publication Number Publication Date
US20020173069A1 true US20020173069A1 (en) 2002-11-21

Family

ID=18554160

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/958,094 Abandoned US20020173069A1 (en) 2000-02-07 2001-02-06 Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device
US11/065,070 Expired - Fee Related US7285446B2 (en) 2000-02-07 2005-02-25 Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/065,070 Expired - Fee Related US7285446B2 (en) 2000-02-07 2005-02-25 Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device

Country Status (5)

Country Link
US (2) US20020173069A1 (zh)
JP (1) JP2001217354A (zh)
KR (1) KR100451924B1 (zh)
TW (1) TW592386U (zh)
WO (1) WO2001059839A1 (zh)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030111734A1 (en) * 2001-02-28 2003-06-19 Hirotaka Kobayashi Semiconductor device, its manufacturing method, and electronic apparatus
FR2856517A1 (fr) * 2003-06-17 2004-12-24 St Microelectronics Sa Procede de fabrication de composant semi-conducteur et composant semi-conducteur
US20060030129A1 (en) * 2004-08-05 2006-02-09 Disco Corporation Method and apparatus for dividing an adhesive film mounted on a wafer
WO2006013197A1 (fr) * 2004-08-03 2006-02-09 United Monolithic Semiconductors S.A.S. Boitier miniature hyperfrequence pour montage en surface et procede de fabrication du boitier
US20100289132A1 (en) * 2009-05-13 2010-11-18 Shih-Fu Huang Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing of the substrate and package
US20100288541A1 (en) * 2009-05-13 2010-11-18 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package
US20110057301A1 (en) * 2009-09-08 2011-03-10 Advanced Semiconductor Engineering, Inc. Semiconductor package
US20110084370A1 (en) * 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US8367473B2 (en) 2009-05-13 2013-02-05 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US9349611B2 (en) 2010-03-22 2016-05-24 Advanced Semiconductor Engineering, Inc. Stackable semiconductor package and manufacturing method thereof
US9564346B2 (en) 2009-10-14 2017-02-07 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6518089B2 (en) * 2001-02-02 2003-02-11 Texas Instruments Incorporated Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly
JP3952963B2 (ja) * 2003-02-21 2007-08-01 ヤマハ株式会社 半導体装置及びその製造方法
JP2008084959A (ja) * 2006-09-26 2008-04-10 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
EP1914798A3 (en) 2006-10-18 2009-07-29 Panasonic Corporation Semiconductor Mounting Substrate and Method for Manufacturing the Same
US7838859B2 (en) * 2008-09-29 2010-11-23 Scully Signal Company Fluid overfill probe with thermal stress prevention
GB0914562D0 (en) 2009-08-20 2009-09-30 Johnson Matthey Plc Catalyst layer
JP2012069919A (ja) * 2010-08-25 2012-04-05 Toshiba Corp 半導体装置の製造方法
CN104584210B (zh) 2012-12-21 2017-09-26 松下知识产权经营株式会社 电子部件封装件及其制造方法
CN104584207A (zh) 2012-12-21 2015-04-29 松下知识产权经营株式会社 电子部件封装以及其制造方法
US9425122B2 (en) 2012-12-21 2016-08-23 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing the same
WO2014097645A1 (ja) * 2012-12-21 2014-06-26 パナソニック株式会社 電子部品パッケージおよびその製造方法
KR102377522B1 (ko) * 2015-04-16 2022-03-22 삼성디스플레이 주식회사 가요성 표시 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5450283A (en) * 1992-11-03 1995-09-12 Motorola, Inc. Thermally enhanced semiconductor device having exposed backside and method for making the same
US5814894A (en) * 1995-04-07 1998-09-29 Nitto Denko Corporation Semiconductor device, production method thereof, and tape carrier for semiconductor device used for producing the semiconductor device
US5864178A (en) * 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
US5937320A (en) * 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3532699B2 (ja) * 1996-05-21 2004-05-31 財団法人石油産業活性化センター 芳香族ポリイミドの製造方法
JP2904154B2 (ja) 1996-10-02 1999-06-14 サンケン電気株式会社 半導体素子を含む電子回路装置
JPH10199936A (ja) * 1997-01-14 1998-07-31 Olympus Optical Co Ltd フレキシブル配線板へのフリップチップ実装構造
JP3134815B2 (ja) * 1997-06-27 2001-02-13 日本電気株式会社 半導体装置
JPH11220077A (ja) * 1997-10-15 1999-08-10 Toshiba Corp 半導体装置および半導体装置の製造方法
JP3743216B2 (ja) 1999-08-20 2006-02-08 セイコーエプソン株式会社 半導体装置及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5450283A (en) * 1992-11-03 1995-09-12 Motorola, Inc. Thermally enhanced semiconductor device having exposed backside and method for making the same
US5864178A (en) * 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
US5814894A (en) * 1995-04-07 1998-09-29 Nitto Denko Corporation Semiconductor device, production method thereof, and tape carrier for semiconductor device used for producing the semiconductor device
US5937320A (en) * 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6794739B2 (en) * 2001-02-28 2004-09-21 Sony Corporation Semiconductor device, process for production thereof, and electronic equipment
US20030111734A1 (en) * 2001-02-28 2003-06-19 Hirotaka Kobayashi Semiconductor device, its manufacturing method, and electronic apparatus
US7005322B2 (en) 2003-06-17 2006-02-28 Stmicroelectronics, S.A. Process for encapsulating semiconductor components using through-holes in the semiconductor components support substrates
FR2856517A1 (fr) * 2003-06-17 2004-12-24 St Microelectronics Sa Procede de fabrication de composant semi-conducteur et composant semi-conducteur
WO2006013197A1 (fr) * 2004-08-03 2006-02-09 United Monolithic Semiconductors S.A.S. Boitier miniature hyperfrequence pour montage en surface et procede de fabrication du boitier
US7602071B2 (en) * 2004-08-05 2009-10-13 Disco Corporation Apparatus for dividing an adhesive film mounted on a wafer
US20060030129A1 (en) * 2004-08-05 2006-02-09 Disco Corporation Method and apparatus for dividing an adhesive film mounted on a wafer
US8399776B2 (en) 2009-05-13 2013-03-19 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package
US20100289132A1 (en) * 2009-05-13 2010-11-18 Shih-Fu Huang Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing of the substrate and package
US20100288541A1 (en) * 2009-05-13 2010-11-18 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package
US8367473B2 (en) 2009-05-13 2013-02-05 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
US20110057301A1 (en) * 2009-09-08 2011-03-10 Advanced Semiconductor Engineering, Inc. Semiconductor package
US8330267B2 (en) * 2009-09-08 2012-12-11 Advanced Semiconductor Engineering, Inc. Semiconductor package
US20110084370A1 (en) * 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US8786062B2 (en) 2009-10-14 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US9165900B2 (en) 2009-10-14 2015-10-20 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US9564346B2 (en) 2009-10-14 2017-02-07 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8884424B2 (en) 2010-01-13 2014-11-11 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US9196597B2 (en) 2010-01-13 2015-11-24 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US9349611B2 (en) 2010-03-22 2016-05-24 Advanced Semiconductor Engineering, Inc. Stackable semiconductor package and manufacturing method thereof

Also Published As

Publication number Publication date
KR100451924B1 (ko) 2004-10-12
WO2001059839A1 (en) 2001-08-16
US7285446B2 (en) 2007-10-23
US20050142691A1 (en) 2005-06-30
JP2001217354A (ja) 2001-08-10
TW592386U (en) 2004-06-11
KR20010105415A (ko) 2001-11-28

Similar Documents

Publication Publication Date Title
US7285446B2 (en) Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device
US7138706B2 (en) Semiconductor device and method for manufacturing the same
KR100281830B1 (ko) 열적개량된플립칩패키지및그제조방법
US5610442A (en) Semiconductor device package fabrication method and apparatus
US7144245B2 (en) Packages for semiconductor die
US5786271A (en) Production of semiconductor package having semiconductor chip mounted with its face down on substrate with protruded electrodes therebetween and semiconductor package
US6515357B2 (en) Semiconductor package and semiconductor package fabrication method
JP3414342B2 (ja) 集積回路チップの実装構造および実装方法
US6461890B1 (en) Structure of semiconductor chip suitable for chip-on-board system and methods of fabricating and mounting the same
US6285086B1 (en) Semiconductor device and substrate for semiconductor device
JP2001015679A (ja) 半導体装置及びその製造方法
JP2001127186A (ja) ボールグリッドアレイパッケージ及びその製造方法と半導体装置
WO2000070677A1 (fr) Appareil semi-conducteur, son procede de fabrication, carte a circuit imprime et appareil electronique
JP3565090B2 (ja) 半導体装置の製造方法
JP2001298115A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
US6413797B2 (en) Semiconductor device and method for making the same
JP2000277649A (ja) 半導体装置及びその製造方法
KR100412157B1 (ko) 반도체장치 및 그 제조방법
US6620652B1 (en) Semiconductor device and method of making the same
JPH10125734A (ja) 半導体ユニットおよびその製造方法
US5982026A (en) Inexpensive resin molded semiconductor device
JPH11297752A (ja) 半導体チップの実装構造、およびこの実装構造を有する半導体装置
JP4038021B2 (ja) 半導体装置の製造方法
US6291893B1 (en) Power semiconductor device for “flip-chip” connections
JP3676590B2 (ja) 半導体装置

Legal Events

Date Code Title Description
AS Assignment

Owner name: ROHM CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SHIBATA, KAZUTAKA;REEL/FRAME:012301/0123

Effective date: 20010925

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION