US20010040255A1 - Electrode contact section of semiconductor device - Google Patents

Electrode contact section of semiconductor device Download PDF

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US20010040255A1
US20010040255A1 US09/853,661 US85366101A US2001040255A1 US 20010040255 A1 US20010040255 A1 US 20010040255A1 US 85366101 A US85366101 A US 85366101A US 2001040255 A1 US2001040255 A1 US 2001040255A1
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layer
type
semiconductor substrate
contact
electrode
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Masahiro Tanaka
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Toshiba Corp
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TANAKA, MASAHIRO
Publication of US20010040255A1 publication Critical patent/US20010040255A1/en
Priority to US11/347,321 priority Critical patent/US7271040B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon

Definitions

  • the present invention relates to an electrode contact section incorporated in a semiconductor device.
  • en electrode section incorporated in a semiconductor device is formed of an impurity layer provided in a semiconductor layer, and an electrode (made of, for example, a metal such as aluminum) that is in contact with the impurity layer.
  • the impurity layer is often formed by ion implantation for the purpose of low cost.
  • the concentration of an impurity in the impurity layer is generally increased.
  • the concentration profile of the impurity layer shows a curved line with a peak.
  • the impurity concentration of a surface portion of the semiconductor layer is lower than a peak concentration assumed at an inner portion thereof.
  • a longitudinal power device such as an IGBT
  • an impurity layer is provided at the other surface thereof.
  • the impurity layer at the other surface of the semiconductor layer cannot be annealed at a high temperature for a long time, with the result that the difference between the peak concentration and the surface concentration of the impurity layer is increased, and hence the contact resistance cannot sufficiently be reduced.
  • an IGBT Insulated Gate Bipolar Transistor
  • an electrode contact section a contact section between the impurity layer 2 and an anode layer 3
  • the present invention has been may provided an electrode contact section of a sufficiently low contact resistance even when forming an impurity layer by ion implantation.
  • the invention has been may provided an electrode contact section in which the contact resistance and the carrier injection coefficient can simultaneously be reduced.
  • an electrode contact section incorporated in a semiconductor device, comprising: a first-conductivity-type semiconductor substrate; a second-conductivity-type impurity layer formed in one surface of the semiconductor substrate and having a thickness of not more than 1.0 ⁇ m from a surface of the semiconductor substrate; a second-conductivity-type contact layer formed in the impurity layer and having a thickness of not more than 0.2 ⁇ m from the surface of the semiconductor substrate, the contact layer being thinner than the impurity layer and having a higher impurity concentration than the impurity layer; and a first electrode formed on the contact layer.
  • an electrode contact section incorporated in a semiconductor device, comprising: a first-conductivity-type semiconductor substrate; a second-conductivity-type impurity layer formed in one surface of the semiconductor substrate; a second-conductivity-type contact layer formed in the impurity layer, being thinner than the impurity layer and having a higher impurity concentration than the impurity layer; a first electrode formed on the contact layer; and a silicide layer formed between the first electrode and the contact layer, the silicide layer having a contact-layer-side end thereof made to substantially correspond to that portion of the contact layer, at which a concentration profile of the contact layer assumes a peak value.
  • FIG. 1 is a sectional view illustrating an IGBT to which the present invention is applied;
  • FIG. 2 is a view illustrating an electrode contact section incorporated as an example in a semiconductor device according to the invention
  • FIG. 3 is a view illustrating an electrode contact section incorporated as a second example in a semiconductor device according to the invention.
  • FIG. 4 is a sectional view illustrating an IGBT to which the present invention is applied;
  • FIG. 5 is a sectional view illustrating an IGBT structure as a first example according to the invention.
  • FIG. 6 is a sectional view illustrating an IGBT structure as a second example according to the invention.
  • FIG. 7 is a sectional view illustrating an IGBT to which the present invention is applied.
  • FIG. 8 is a sectional view illustrating an IGBT structure as a third example according to the invention.
  • FIG. 9 is a sectional view illustrating an IGBT structure as a fourth example according to the invention.
  • FIG. 10 is a sectional view illustrating an IGBT to which the present invention is applied.
  • FIG. 11 is a sectional view illustrating an IGBT structure as a fifth example according to the invention.
  • FIG. 12 is a sectional view illustrating an IGBT structure as a sixth example according to the invention.
  • FIG. 13 is a graph illustrating the characteristics of an IGBT according to the invention.
  • Electrode contact sections each incorporated in a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
  • FIG. 2 shows an electrode contact section incorporated as an example in a semiconductor device according to the invention.
  • a p-type impurity layer 2 is formed in an n-type semiconductor substrate 1 .
  • the n-type semiconductor layer 1 contains an n-type impurity such as phosphor (P) with a substantially constant concentration of approx. 10 14 ions/cm 3 .
  • the p-type impurity layer 2 is formed in a surface area of the semiconductor substrate 1 and contains a p-type impurity such as boron (B).
  • the depth of the p-type impurity layer 2 from the surface of the semiconductor substrate 1 is set at 1.0 ⁇ m or less, for example, approx. 0.8 ⁇ m. Further, the peak value of the concentration profile of the p-type impurity layer 2 is set at a value falling within the range of 10 17 -10 18 ions/cm 3 .
  • a p + -type contact layer 4 is formed in the p-type impurity layer 2 , and an electrode 3 is formed on the p + -type contact layer 4 .
  • the p + -type contact layer 4 is thus interposed between the p-type impurity layer 2 and the electrode 3 and has a higher impurity concentration than the p-type impurity layer 2 .
  • the p + -type contact layer 4 contains a p-type impurity such as boron (B) or boron fluoride (BF 2 ), etc., and has an impurity concentration peak value of 10 19 ions/cm 3 or more and a surface impurity concentration of 10 18 ions/cm 3 or more.
  • the depth of the p + -type contact layer 4 from the surface of the semiconductor substrate 1 is set at 0.2 ⁇ m or less, for example, approx. 0.16 ⁇ m.
  • the electrode 3 is formed of, for example, aluminum.
  • the p-type impurity layer 2 has a low impurity concentration, and a sufficiently shallow depth of 1.0 ⁇ m or less from the surface of the semiconductor substrate 1 . Accordingly, when this electrode contact structure is applied to the collector (anode) electrode of an IGBT, the coefficient of carrier (positive hole) injection at the time of turning off the semiconductor device can be reduced, thereby increasing the speed of the turn-off operation.
  • the p + -type contact layer 4 having a higher impurity concentration than the p-type impurity layer 2 is provided between the p-type impurity layer 2 and the electrode 3 . Since the depth of the p + -type contact layer 4 from the surface of the semiconductor substrate 1 is set at 0.2 ⁇ m or less, the p + -type contact layer 4 does not influence the carrier injection coefficient at the time of turning off the semiconductor device. In other words, the p + -type contact layer 4 does not increase the carrier injection coefficient.
  • the contact resistance at the electrode contact section can be reduced.
  • the electrode contact section of the invention can have a sufficiently low contact resistance, and simultaneously realize a low carrier injection coefficient when turning off the semiconductor device.
  • the semiconductor substrate 1 is of the n-type and the impurity layer 2 and the p + -type contact layer 4 are of the p-type, a similar advantage can be obtained if the semiconductor substrate 1 is made to be of the p-type and the impurity layer 2 and the p + -type contact layer 4 are made to be of the n-type.
  • an n-type semiconductor substrate e.g. a silicon substrate 1 having, for example, an impurity concentration of approx. 1.5 ⁇ 10 14 ions/cm 2 is prepared.
  • a p-type impurity such as boron (B) is implanted into the semiconductor substrate by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 60 keV and approx. 1 ⁇ 10 13 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 1050° C. for approx. 20 min.
  • a p-type impurity layer e.g. a p-type emitter layer
  • a depth of approx. 0.8 ⁇ m from the surface of the semiconductor substrate 1 is formed.
  • a p-type impurity such as boron (B) is implanted into the p-type impurity layer 2 in the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 10 keV and approx. 1 ⁇ 10 14 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 800° C. for approx. 30 min.
  • a p + -type contact layer 4 having a depth of approx. 0.16 ⁇ m from the surface of the semiconductor substrate 1 is formed.
  • the p + -type contact layer 4 must be formed very shallow, and must have a very high impurity concentration. To this end, the acceleration voltage is set low, the dose is set high, and the period for executing the thermal diffusion process is set short, as is described above.
  • Boron fluoride (BF 2 ) may be used as the p-type impurity, instead of boron (B) (i.e. the element is changed from a light one to a heavy one), and implanted into the p-type impurity layer 2 in the semiconductor substrate 1 , thereby forming a p + -type contact layer 4 .
  • B boron
  • a thermal oxide film formed on a surface portion of the semiconductor substrate 1 i.e. on a surface portion of the p + -type contact layer 4 , is removed using antimony fluoride.
  • the electrode 3 made of a metal such as aluminum is provided on the p + -type contact layer 4 by sputtering or CVD.
  • the resultant structure is subjected to a heat treatment executed for approx. 30 min. in the atmosphere of nitrogen of approx. 450° C., thereby diffusing the atoms (e.g. aluminum atoms) of the electrode 3 into the semiconductor substrate 1 , i.e. into the p + -type contact layer 4 so as to reduce the contact resistance of the electrode 3 and the p + -type contact layer 4 .
  • atoms e.g. aluminum atoms
  • the depth and impurity concentration of the p-type impurity layer 2 substantially determine the carrier injection coefficient.
  • the peak value of the impurity concentration profile of the p-type impurity layer 2 falls within the range of 10 17 -10 18 ions/cm 3 , and the depth of the layer 2 is set at a sufficiently low value of 1.0 ⁇ m or less. Accordingly, if this structure is applied to the collector electrode of an IGBT, the carrier injection coefficient when turning off the IGBT can be reduced, thereby increasing the speed of the turn-off operation.
  • the p + -type contact layer 4 which has a higher impurity concentration than the p-type impurity layer 2 and is provided between the p-type impurity layer 2 and the electrode 3 , is set to have a depth of 0.2 ⁇ m or less from the surface of the semiconductor substrate 1 , it does not influence the carrier injection coefficient at the time of turning off the semiconductor device. In other words, the p + -type contact layer 4 does not increase the carrier injection coefficient. Further, since the peak value of the impurity concentration profile of the p + -type contact layer 4 is set at approx. 10 19 ions/cm 3 , the contact resistance of the electrode contact section is also reduced.
  • the p-type impurity layer 2 is made to be sufficiently shallow (1.0 ⁇ m or less) and have a low concentration (10 17 -10 18 ions/cm 3 ), and the p + -type contact layer 4 interposed between the p-type impurity layer 2 and the electrode 3 has a sufficiently high impurity concentration (approx. 10 19 ions/cm 3 ).
  • This structure simultaneously realizes a low contact resistance and a low carrier injection coefficient.
  • a silicide layer 5 is formed between the electrode 3 and the p + -type contact layer 4 .
  • This example is not characterized by the provision of the silicide layer 5 , but by the depth of the silicide layer 5 from the surface of the semiconductor substrate 1 , more specifically, by the relationship between the depth of the silicide layer 5 from the surface of the semiconductor substrate 1 , and the peak value of the impurity profile of the p + -type contact layer 4 .
  • FIG. 3 shows the second example.
  • a p-type impurity layer 2 is formed in an n-type semiconductor substrate 1 .
  • the n-type semiconductor layer 1 contains an n-type impurity such as phosphor (P) with a substantially constant concentration of approx. 10 14 ions/cm 3 .
  • the p-type impurity layer 2 is formed in a surface area of the semiconductor substrate 1 and contains a p-type impurity such as boron (B).
  • the depth of the p-type impurity layer 2 from the surface of the semiconductor substrate 1 is set at 1.0 ⁇ m or less, for example, approx. 0.8 ⁇ m. Further, the peak value of the concentration profile of the p-type impurity layer 2 is set at a value falling within the range of 10 17 -10 18 ions/cm 3 .
  • a p + -type contact layer 4 is formed in the p-type impurity layer 2 , and an electrode 3 is formed on the p + -type contact layer 4 .
  • the p + -type contact layer 4 is thus interposed between the p-type impurity layer 2 and the electrode 3 and has a higher impurity concentration than the p-type impurity layer 2 .
  • the p + -type contact layer 4 contains a p-type impurity such as boron (B) or boron fluoride (BF 2 ), etc., and has an impurity concentration peak value of 10 19 ions/cm 3 or more and a surface impurity concentration of 10 18 ions/cm 3 or more.
  • the depth of the p + -type contact layer 4 from the surface of the semiconductor substrate 1 is set at 0.2 ⁇ m or less, for example, approx. 0.16 ⁇ m.
  • the electrode 3 is formed of, for example, aluminum.
  • a silicide layer 5 is provided between the electrode 3 and the p + -type contact layer 4 .
  • the silicide layer 5 is formed by, for example, a thermal treatment in which atoms (e.g. aluminum atoms) constituting the electrode 3 react with atoms (silicon atoms) constituting the semiconductor substrate 1 .
  • the depth of the silicide layer 5 from the surface of the semiconductor substrate 1 is set equal to or shallower than the depth of the p + -type contact layer 4 from the surface of the semiconductor substrate 1 .
  • the depth of the silicide layer 5 from the surface of the semiconductor substrate 1 is also set at 0.2 ⁇ m or less.
  • the electrode 3 is electrically connected to the lowest resistance portion of the p + -type contact layer 4 (corresponding to a portion thereof at which the concentration profile assumes the peak value) via the silicide layer 5 , thereby reducing the contact resistance.
  • the p-type impurity layer 2 has a low impurity concentration, and a sufficiently shallow depth of 1.0 ⁇ m or less from the surface of the semiconductor substrate 1 . Accordingly, if this electrode contact structure is applied to the collector electrode (anode electrode) of an IGBT, the carrier (positive hole) injection coefficient when turning off the IGBT can be reduced, thereby increasing the speed of the turn-off operation.
  • the p + -type contact layer 4 which has a higher impurity concentration than the p-type impurity layer 2 and is provided between the p-type impurity layer 2 and the electrode 3 , is set to have a depth of 0.2 ⁇ m or less from the surface of the semiconductor substrate 1 , it does not influence the carrier injection coefficient at the time of turning off the semiconductor device. In other words, the p + -type contact layer 4 does not increase the carrier injection coefficient.
  • the p + -type contact layer 4 has a sufficiently high impurity concentration
  • the silicide layer 5 is provided between the electrode 3 and the p + -type contact layer 4 .
  • the position of the bottom of the silicide layer 5 is made to correspond to that portion of the p + -type contact layer 4 , at which the concentration profile of the layer 4 assumes a peak value. Accordingly, the contact resistance of the electrode contact section is further reduced.
  • FIG. 13 shows the relationship between a saturation voltage Vce (sat) between the collector and the emitter and the thickness of the silicide layer 5 (the depth from the surface of the semiconductor substrate 1 ), obtained when the concentration profile of the p + -type contact layer 4 assumes a peak value at a depth of 0.04 ⁇ m from the surface of the semiconductor substrate 1 .
  • the saturation voltage Vce (sat) between the collector and the emitter is minimum when the position of the bottom of the silicide layer 5 (i.e. the thickness of the layer 5 ) corresponds to that portion of the p + -type contact layer 4 , at which the concentration profile of the layer 4 assumes the peak value, i.e., when the thickness of the layer 5 is 0.04 ⁇ m.
  • the contact resistance is minimum when the position of the bottom of the silicide layer 5 (i.e. the thickness of the layer 5 ) corresponds to that portion of the p + -type contact layer 4 , at which the concentration profile of the layer 4 assumes the peak value.
  • the electrode contact section of the invention simultaneously realizes a low contact resistance and a low carrier injection coefficient.
  • the semiconductor substrate 1 is of the n-type and the impurity layer 2 and the contact layer 4 are of the p-type, the same advantage can be obtained by making the semiconductor substrate 1 be of the p-type and the impurity layer 2 and the contact layer 4 be of the n-type.
  • an n-type semiconductor substrate e.g. a silicon substrate 1 having, for example, an impurity concentration of approx. 1.5 ⁇ 10 14 ions/cm 2 is prepared.
  • a p-type impurity such as boron (B) is implanted into the semiconductor substrate by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 60 keV and approx. 1 ⁇ 10 13 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 1050° C. for approx. 20 min.
  • a p-type impurity layer e.g. a p-type emitter layer
  • a depth of approx. 0.8 ⁇ m from the surface of the semiconductor substrate 1 is formed.
  • a p-type impurity such as boron (B) is implanted into the p-type impurity layer 2 in the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 10 keV and approx. 1 ⁇ 10 14 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 800° C. for approx. 30 min.
  • a p + -type contact layer 4 having a depth of approx. 0.16 ⁇ m from the surface of the semiconductor substrate 1 is formed.
  • the p + -type contact layer 4 must be formed very shallow, and must have a very high impurity concentration. To this end, the acceleration voltage is set low, the dose is set high, and the period for executing the thermal diffusion process is set short, as is described above.
  • Boron fluoride (BF 2 ) may be used as the p-type impurity, instead of boron (B) (i.e. the element is changed from a light one to a heavy one), and implanted into the p-type impurity layer 2 in the semiconductor substrate 1 , thereby forming a p + -type contact layer 4 .
  • B boron
  • a thermal oxide film formed on a surface portion of the semiconductor substrate 1 i.e. on a surface portion of the p + -type contact layer 4 , is removed using antimony fluoride.
  • an electrode 3 made of a metal such as aluminum and having a thickness of approx. 0.05 ⁇ m is provided on the p + -type contact layer 4 by sputtering or CVD.
  • the resultant structure is subjected to a heat treatment executed for approx. 30 min. in the atmosphere of nitrogen of approx. 450° C., thereby diffusing the atoms (e.g. aluminum atoms) of the electrode 3 into the semiconductor substrate 1 , i.e. into the p + -type contact layer 4 .
  • a silicide layer 5 is formed.
  • the thickness of the silicide layer 5 (the depth from the surface of the semiconductor substrate 1 ) is made substantially equal to that thickness of the p + -type contact layer 4 from the surface of the semiconductor substrate 1 , at which the concentration profile of the layer 4 assumes a peak value.
  • the silicide layer 5 is made to have a thickness of approx. 0.04 ⁇ m.
  • the carrier injection coefficient is basically determined from the depth and impurity concentration of the p-type impurity layer 2 .
  • the peak value of the concentration profile of the p-type impurity layer 2 is set at a value falling within the range of 10 17 -10 18 ions/cm 3 .
  • the depth of the p-type impurity layer 2 from the surface of the semiconductor substrate 1 is set at a sufficient low value of 1.0 ⁇ m or less. Accordingly, when this electrode contact structure is applied to the collector electrode of an IGBT, the coefficient of carrier injection at the time of turning off the semiconductor device can be reduced, thereby increasing the speed of the turn-off operation.
  • the p + -type contact layer 4 having a higher impurity concentration than the p-type impurity layer 2 is provided between the p-type impurity layer 2 and the electrode 3 . Since the depth of the p + -type contact layer 4 from the surface of the semiconductor substrate 1 is set at 0.2 ⁇ m or less, the p + -type contact layer 4 does not influence the carrier injection coefficient at the time of turning off the semiconductor device. In other words, the p + -type contact layer 4 does not increase the carrier injection coefficient. Moreover, since the peak value of the impurity concentration profile of the p + -type contact layer 4 is set at approx. 10 19 ions/cm 3 , the contact resistance of the electrode contact section is also reduced.
  • the p + -type contact layer 4 has a sufficiently high impurity concentration
  • the silicide layer 5 is provided between the electrode 3 and the p + -type contact layer 4 .
  • the position of the bottom of the silicide layer 5 is made to correspond to that portion of the p + -type contact layer 4 , at which the concentration profile of the layer 4 assumes a peak value. Accordingly, the contact resistance of the electrode contact section is further reduced.
  • FIG. 4 shows a general structure for the IGBT.
  • An n-type semiconductor substrate (silicon substrate) 1 serves as an n-type base layer.
  • a p-type base layer 7 is formed on one surface of the semiconductor substrate 1 , and an n + -type emitter layer 8 is formed in the p-type base layer 7 .
  • a gate electrode 10 is formed on the p-type base layer (channel section) 7 between the n-type base layer 1 and the n + -type emitter layer 8 , with an insulating layer 9 interposed therebetween. Further, an emitter electrode 11 is formed on the p-type base layer 7 and the n + -type emitter layer 8 .
  • a p + -type emitter layer 2 is formed on the other surface of the semiconductor substrate 1 .
  • the p + -type emitter layer 2 serves as a p-type impurity layer that constitutes an electrode contact section according to the invention.
  • a collector electrode 3 is formed on the p + -type emitter layer 2 .
  • FIG. 5 shows an IGBT as a first example of the invention.
  • This example relates to an IGBT to which the above-described first electrode contact section is applied.
  • a p-type base layer 7 is formed on one surface of an n-type semiconductor substrate (n-type base layer) 1 , and an n + -type emitter layer 8 is formed in the p-type base layer 7 .
  • a gate electrode 10 is formed on the p-type base layer (channel section) 7 between the n-type base layer 1 and the n + -type emitter layer 8 , with an insulating layer 9 interposed therebetween.
  • an emitter electrode 11 is formed on the p-type base layer 7 and the n + -type emitter layer 8 .
  • a p + -type emitter layer 2 is formed on the other surface of the semiconductor substrate 1 .
  • the p + -type emitter layer 2 contains a p-type impurity such as boron (B).
  • the depth of the p + -type emitter layer 2 from the other surface of the semiconductor substrate 1 is set at 1.0 ⁇ m or less, for example, approx. 0.8 ⁇ m. Further, the peak value of the concentration profile of the p + -type emitter layer 2 is set at a value falling within the range of 10 17 -10 18 ions/cm 3 .
  • a p ++ -type contact layer 4 is formed in the p + -type emitter layer 2 , and a collector electrode 3 is formed on the p + +-type contact layer 4 .
  • the p ++ -type contact layer 4 is thus interposed between the p + -type emitter layer 2 and the collector electrode 3 and has a higher impurity concentration than the p + -type emitter layer 2 .
  • the p ++ -type contact layer 4 contains a p-type impurity such as boron (B) or boron fluoride (BF 2 ), etc., and has an impurity concentration peak value of 10 19 ions/cm 3 or more and a surface impurity concentration of 10 18 ions/cm 3 or more.
  • the depth of the p ++ -type contact layer 4 from the surface of the semiconductor substrate 1 is set at 0.2 ⁇ m or less, for example, approx. 0.16 ⁇ m.
  • the collector electrode 3 is formed of, for example, aluminum.
  • the p + -type emitter layer 2 has a low impurity concentration, and a sufficiently shallow depth of 1.0 ⁇ m or less from the surface of the semiconductor substrate 1 . Accordingly, the coefficient of carrier (positive hole) injection at the time of turning off the IGBT can be reduced, thereby increasing the speed of the turn-off operation.
  • the p + +-type contact layer 4 having a higher impurity concentration than the p + -type emitter layer 2 is provided between the p + -type emitter layer 2 and the collector electrode 3 . Since the depth of the p ++ -type contact layer 4 from the surface of the semiconductor substrate 1 is set at 0.2 ⁇ m or less, the p + -type contact layer 4 does not influence the carrier injection coefficient at the time of turning off the IGBT. In other words, the p ++ -type contact layer 4 does not increase the carrier injection coefficient.
  • the contact resistance of the electrode contact section is reduced.
  • the electrode contact section of the IGBT enables the simultaneous realization of a sufficient reduction of the contact resistance and reduction of the carrier injection coefficient.
  • the semiconductor substrate 1 is of the n-type and the emitter layer 2 and the contact layer 4 are of the p-type, the same advantage can be obtained by making the semiconductor substrate 1 be of the p-type and the emitter layer 2 and the contact layer 4 be of the n-type.
  • an n-type semiconductor substrate e.g. a silicon substrate 1 having, for example, an impurity concentration of approx. 1.5 ⁇ 10 14 ions/cm 2 is prepared.
  • a p-type base layer 7 , an n + -type emitter layer 8 , an insulating film 9 , a gate electrode 10 and an emitter electrode 11 are formed on one surface of the semiconductor substrate 1 .
  • a p-type impurity such as boron (B) is implanted into the other surface of the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 60 keV and approx. 1 ⁇ 10 13 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 1050° C. for approx. 20 min.
  • a p + -type emitter layer 2 having a depth of approx. 0.8 ⁇ m from the other surface of the semiconductor substrate 1 is formed.
  • a p-type impurity such as boron (B) is implanted into the p + -type emitter layer 2 in the other surface of the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 10 keV and approx. 1 ⁇ 10 14 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 800° C. for approx. 30 min.
  • a p ++ -type contact layer 4 having a depth of approx. 0.16 ⁇ m from the other surface of the semiconductor substrate 1 is formed.
  • the p ++ -type contact layer 4 must be formed very shallow, and must have a very high impurity concentration. To this end, the acceleration voltage is set low, the dose is set high, and the period for executing the thermal diffusion process is set short, as is described above.
  • Boron fluoride (BF 2 ) may be used as the p-type impurity, instead of boron (B) (i.e. the element is changed from a light one to a heavy one), and implanted into the p + -type emitter layer 2 in the semiconductor substrate 1 , thereby forming a p ++ -type contact layer 4 .
  • B boron
  • a thermal oxide film formed on a surface portion of the other surface of the semiconductor substrate 1 i.e. on a surface portion of the p ++ -type contact layer 4 , is removed using antimony fluoride.
  • a collector electrode 3 made of a metal such as aluminum is provided on the p ++ -type contact layer 4 by sputtering or CVD.
  • the resultant structure is subjected to a heat treatment executed for approx. 30 min. in the atmosphere of nitrogen of approx. 450° C., thereby diffusing the atoms (e.g. aluminum atoms) of the collector electrode 3 into the semiconductor substrate 1 , i.e. into the p ++ -type contact layer 4 so as to reduce the contact resistance of the collector electrode 3 and the p ++ -type contact layer 4 .
  • atoms e.g. aluminum atoms
  • FIG. 6 shows an IGBT as a second example of the invention.
  • This example relates to an IGBT to which the above-described second electrode contact section is applied.
  • a p-type base layer 7 is formed on one surface of an n-type semiconductor substrate (n-type base layer) 1 , and an n + -type emitter layer 8 is formed in the p-type base layer 7 .
  • a gate electrode 10 is formed on the p-type base layer (channel section) 7 between the n-type base layer 1 and the n + -type emitter layer 8 , with an insulating layer 9 interposed therebetween.
  • an emitter electrode 11 is formed on the p-type base layer 7 and the n + -type emitter layer 8 .
  • a p + -type emitter layer 2 is formed on the other surface of the semiconductor substrate 1 .
  • the p + -type emitter layer 2 contains a p-type impurity such as boron (B).
  • the depth of the p + -type emitter layer 2 from the other surface of the semiconductor substrate 1 is set at 1.0 ⁇ m or less, for example, approx. 0.8 ⁇ m. Further, the peak value of the concentration profile of the p + -type emitter layer 2 is set at a value falling within the range of 10 17 -10 18 ions/cm 3 .
  • a p ++ -type contact layer 4 is formed in the p + -type emitter layer 2 , and a collector electrode 3 is formed on the p ++ -type contact layer 4 .
  • the p ++ -type contact layer 4 is thus interposed between the p + -type emitter layer 2 and the collector electrode 3 and has a higher impurity concentration than the p + -type emitter layer 2 .
  • the p ++ -type contact layer 4 contains a p-type impurity such as boron (B) or boron fluoride (BF 2 ), etc., and has an impurity concentration peak value of 10 19 ions/cm 3 or more and a surface impurity concentration of 10 18 ions/cm 3 or more.
  • the depth of the p ++ -type contact layer 4 from the surface of the semiconductor substrate 1 is set at 0.2 ⁇ m or less, for example, approx. 0.16 ⁇ m.
  • the collector electrode 3 is formed of, for example, aluminum.
  • a silicide layer 5 is provided between the collector electrode 3 and the p ++ -type contact layer 4 .
  • the silicide layer 5 is formed by, for example, a thermal treatment in which atoms (e.g. aluminum atoms) constituting the collector electrode 3 react with atoms (silicon atoms) constituting the semiconductor substrate 1 .
  • the depth of the silicide layer 5 from the other surface of the semiconductor substrate 1 is set equal to or shallower than the depth of the p ++ -type contact layer 4 from the other surface of the semiconductor substrate 1 .
  • the depth of the silicide layer 5 from the other surface of the semiconductor substrate 1 is also set at 0.2 ⁇ m or less.
  • the collector electrode 3 is electrically connected to the lowest resistance portion of the p ++ -type contact layer 4 (corresponding to a portion thereof at which the concentration profile assumes the peak value) via the silicide layer 5 , thereby reducing the contact resistance.
  • the p + -type emitter layer 2 has a low impurity concentration, and a sufficiently shallow depth of 1.0 ⁇ m or less from the other surface of the semiconductor substrate 1 . Accordingly, the carrier (positive hole) injection coefficient when turning off the IGBT can be reduced, thereby increasing the speed of the turn-off operation.
  • the p ++ -type contact layer 4 which has a higher impurity concentration than the p + -type emitter layer 2 and is provided between the p + -type emitter layer 2 and the collector electrode 3 , is set to have a depth of 0.2 ⁇ m or less from the surface of the semiconductor substrate 1 , it does not influence the carrier injection coefficient at the time of turning off the IGBT. In other words, the p ++ -type contact layer 4 does not increase the carrier injection coefficient.
  • the p ++ -type contact layer 4 has a sufficiently high impurity concentration
  • the silicide layer 5 is provided between the collector electrode 3 and the p ++ -type contact layer 4 .
  • the position of the bottom of the silicide layer 5 is made to correspond to that portion of the p ++ -type contact layer 4 , at which the concentration profile of the layer 4 assumes a peak value. Accordingly, the contact resistance of the electrode contact section is further reduced.
  • the electrode contact section of the IGBT according to the invention enables the simultaneous realization of a sufficient reduction of the contact resistance and reduction of the carrier injection coefficient.
  • the semiconductor substrate 1 is of the n-type and the emitter layer 2 and the contact layer 4 are of the p-type, the same advantage can be obtained by making the semiconductor substrate 1 be of the p-type and the emitter layer 2 and the contact layer 4 be of the n-type.
  • an n-type semiconductor substrate e.g. a silicon substrate 1 having, for example, an impurity concentration of approx. 1.5 ⁇ 10 14 ions/cm 2 is prepared.
  • a p-type base layer 7 , an n+-type emitter layer 8 , an insulating film 9 , a gate electrode 10 and an emitter electrode 11 are formed on one surface of the semiconductor substrate 1 .
  • a p-type impurity such as boron (B) is implanted into the other surface of the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 60 keV and approx. 1 ⁇ 10 13 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 1050° C. for approx. 20 min.
  • a p + -type emitter layer 2 having a depth of approx. 0.8 ⁇ m from the other surface of the semiconductor substrate 1 is formed.
  • a p-type impurity such as boron (B) is implanted into the p + -type emitter layer 2 in the other surface of the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 10 keV and approx. 1 ⁇ 10 14 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 800° C. for approx. 30 min.
  • a p ++ -type contact layer 4 having a depth of approx. 0.16 ⁇ m from the other surface of the semiconductor substrate 1 is formed.
  • the p ++ -type contact layer 4 must be formed very shallow, and must have a very high impurity concentration. To this end, the acceleration voltage is set low, the dose is set high, and the period for executing the thermal diffusion process is set short, as is described above.
  • Boron fluoride (BF 2 ) may be used as the p-type impurity, instead of boron (B) (i.e. the element is changed from a light one to a heavy one), and implanted into the p + -type emitter layer 2 in the semiconductor substrate 1 , thereby forming a p ++ -type contact layer 4 .
  • B boron
  • a thermal oxide film formed on a surface portion of the other surface of the semiconductor substrate 1 i.e. on a surface portion of the p ++ -type contact layer 4 , is removed using antimony fluoride.
  • a collector electrode 3 made of a metal such as aluminum and having a thickness of approx. 0.05 ⁇ m is provided on the p ++ -type contact layer 4 by sputtering or CVD.
  • the resultant structure is subjected to a heat treatment executed for approx. 30 min. in the atmosphere of nitrogen of approx. 450° C., thereby diffusing the atoms (e.g. aluminum atoms) of the collector electrode 3 into the semiconductor substrate 1 , i.e. into the p ++ -type contact layer 4 so as to form a silicide layer 5 .
  • the thickness of the silicide layer 5 (the depth from the other surface of the semiconductor substrate 1 ) is made substantially equal to that thickness of the p ++ -type contact layer 4 from the other surface of the semiconductor substrate 1 , at which the concentration profile of the layer 4 assumes a peak value.
  • the silicide layer 5 is made to have a thickness of approx. 0.04 ⁇ m.
  • the collector electrode 3 may be formed after forming the silicide layer 5 .
  • FIG. 8 shows an IGBT as a third example of the invention.
  • This example relates to an IGBT (a reference example) as shown in FIG. 7, in which a plurality of p + -type emitter layers 2 A isolated from each other are formed, and to which the above-described first electrode contact section is applied.
  • a p-type base layer 7 is formed on one surface of an n-type semiconductor substrate (n-type base layer) 1 , and an n + -type emitter layer 8 is formed in the p-type base layer 7 .
  • a gate electrode 10 is formed on the p-type base layer (channel section) 7 between the n-type base layer 1 and the n + -type emitter layer 8 , with an insulating layer 9 interposed therebetween.
  • an emitter electrode 11 is formed on the p-type base layer 7 and the n + -type emitter layer 8 .
  • a plurality of p + -type emitter layers 2 A isolated from each other are formed on the other surface of the semiconductor substrate 1 .
  • Each p + -type emitter layer 2 A contains a p-type impurity such as boron (B).
  • the depth of each p + -type emitter layer 2 A from the other surface of the semiconductor substrate 1 is set at 1.0 ⁇ m or less, for example, approx. 0.8 ⁇ m.
  • the peak value of the concentration profile of each p + -type emitter layer 2 A is set at a value falling within the range of 10 17 -10 18 ions/cm 3 .
  • a p ++ -type contact layer 4 A is formed in each p + -type emitter layer 2 A, and a collector electrode 3 is formed on the resultant p ++ -type contact layers 4 A. Further, insulating films 6 are formed on respective exposed portions of the other surface of the n-type base layer (semiconductor substrate) 1 . Accordingly, the collector electrode 3 is electrically connected to the plurality of p + -type emitter layers 2 A, and electrically isolated from the n-type base layer 1 .
  • the p ++ -type contact layers 4 A are interposed between the respective p + -type emitter layers 2 A and the collector electrode 3 , and have a higher impurity concentration than the p + -type emitter layers 2 A.
  • each p ++ -type contact layer 4 A contains a p-type impurity such as boron (B) or boron fluoride (BF 2 ), etc., and has an impurity concentration peak value of 10 19 ions/cm 3 or more and a surface impurity concentration of 10 18 ions/cm 3 or more.
  • the depth of each p ++ -type contact layer 4 A from the other surface of the semiconductor substrate 1 is set at 0.2 ⁇ m or less, for example, approx. 0.16 ⁇ m.
  • the collector electrode 3 is formed of, for example, aluminum.
  • the p + -type emitter layers 2 A have a low impurity concentration, and a sufficiently shallow depth of 1.0 ⁇ m or less from the other surface of the semiconductor substrate 1 . Accordingly, the carrier (positive hole) injection coefficient when turning off the IGBT can be reduced, thereby increasing the speed of the turn-off operation.
  • the carrier injection coefficient can be controlled by changing the depth of the p + -type emitter layers 2 A or contact ratio W 1 /W 2 .
  • the p ++ -type contact layers 4 which have a higher impurity concentration than the p + -type emitter layers 2 A and are provided between the respective p + -type emitter layers 2 A and the collector electrode 3 , are set to have a depth of 0.2 ⁇ m or less from the other surface of the semiconductor substrate 1 , they do not influence the carrier injection coefficient at the time of turning off the IGBT. In other words, the p ++ -type contact layers 4 A do not increase the carrier injection coefficient.
  • the electrode contact section of the IGBT according to the invention enables the simultaneous realization of a sufficient reduction of the contact resistance and reduction of the carrier injection coefficient.
  • the semiconductor substrate 1 is of the n-type and the emitter layers 2 A and the contact layers 4 A are of the p-type, the same advantage can be obtained by making the semiconductor substrate 1 be of the p-type and the emitter layers 2 A and the contact layers 4 A be of the n-type.
  • an n-type semiconductor substrate e.g. a silicon substrate 1 having, for example, an impurity concentration of approx. 1.5 ⁇ 10 14 ions/cm 2 is prepared.
  • a p-type base layer 7 , an n + -type emitter layer 8 , an insulating film 9 , a gate electrode 10 and an emitter electrode 11 are formed on one surface of the semiconductor substrate 1 .
  • a p-type impurity such as boron (B) is implanted into the other surface of the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 60 keV and approx. 1 ⁇ 10 13 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 1050° C. for approx. 20 min.
  • p + -type emitter layers 2 A having a depth of approx. 0.8 ⁇ m from the other surface of the semiconductor substrate 1 are formed.
  • a p-type impurity such as boron (B) is implanted into the p + -type emitter layers 2 A in the other surface of the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 10 keV and approx. 1 ⁇ 10 14 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 800° C. for approx. 30 min.
  • p ++ -type contact layers 4 A having a depth of approx. 0.16 ⁇ m from the other surface of the semiconductor substrate 1 are formed.
  • the p ++ -type contact layers 4 A must be formed very shallow, and must have a very high impurity concentration. To this end, the acceleration voltage is set low, the dose is set high, and the period for executing the thermal diffusion process is set short, as is described above.
  • Boron fluoride (BF 2 ) may be used as the p-type impurity, instead of boron (B) (i.e. the element is changed from a light one to a heavy one), and implanted into the p + -type emitter layers 2 A in the semiconductor substrate 1 , thereby forming p ++ -type contact layers 4 A.
  • B boron
  • a thermal oxide film formed on a surface portion of the other surface of the semiconductor substrate 1 i.e. on a surface portion of the p ++ -type contact layers 4 A, is removed using antimony fluoride.
  • an insulating film 6 is formed on the other surface side of the semiconductor substrate 1 by, for example, CVD.
  • the insulating film 6 is patterned by PEP or RIE, thereby forming contact holes that extend to the respective p ++ -type contact layers 4 A.
  • a collector electrode 3 extending to the p ++ -type contact layers 4 A is formed by sputtering or CVD.
  • the resultant structure is subjected to a heat treatment executed for approx. 30 min. in the atmosphere of nitrogen of approx. 450° C., thereby diffusing the atoms (e.g. aluminum atoms) of the collector electrode 3 into the semiconductor substrate 1 , i.e. into the p ++ -type contact layers 4 A.
  • the contact resistance between the collector electrode 3 and the p ++ -type contact layers 4 is reduced.
  • FIG. 9 shows an IGBT as a fourth example of the invention.
  • This example relates to an IGBT (a reference example) as shown in FIG. 7, in which a plurality of p + -type emitter layers 2 A isolated from each other are formed, and to which the above-described second electrode contact section is applied.
  • a p-type base layer 7 is formed on one surface of an n-type semiconductor substrate (n-type base layer) 1 , and an n + -type emitter layer 8 is formed in the p-type base layer 7 .
  • a gate electrode 10 is formed on the p-type base layer (channel section) 7 between the n-type base layer 1 and the n + -type emitter layer 8 , with an insulating layer 9 interposed therebetween.
  • an emitter electrode 11 is formed on the p-type base layer 7 and the n + -type emitter layer 8 .
  • a plurality of p + -type emitter layers 2 A isolated from each other are formed on the other surface of the semiconductor substrate 1 .
  • Each p + -type emitter layer 2 A contains a p-type impurity such as boron (B).
  • the depth of each p + -type emitter layer 2 A from the other surface of the semiconductor substrate 1 is set at 1.0 ⁇ m or less, for example, approx. 0.8 ⁇ m.
  • the peak value of the concentration profile of each p + -type emitter layer 2 A is set at a value falling within the range of 10 17 -10 18 ions/cm 3 .
  • a p ++ -type contact layer 4 A is formed in each p + -type emitter layer 2 A, and a collector electrode 3 is formed on the resultant p ++ -type contact layers 4 A. Further, insulating films 6 are formed on respective exposed portions of the other surface of the n-type base layer (semiconductor substrate) 1 . Accordingly, the collector electrode 3 is electrically connected to the plurality of p + -type emitter layers 2 A, and electrically isolated from the n-type base layer 1 .
  • the p ++ -type contact layers 4 A are interposed between the respective p + -type emitter layers 2 A and the collector electrode 3 , and have a higher impurity concentration than the p + -type emitter layers 2 A.
  • each p ++ -type contact layer 4 A contains a p-type impurity such as boron (B) or boron fluoride (BF 2 ), etc., and has an impurity concentration peak value of 10 19 ions/cm 3 or more and a surface impurity concentration of 10 18 ions/cm 3 or more.
  • the depth of each p ++ -type contact layer 4 A from the other surface of the semiconductor substrate 1 is set at 0.2 ⁇ m or less, for example, approx. 0.16 ⁇ m.
  • the collector electrode 3 is formed of, for example, aluminum.
  • a silicide layer 5 is provided between the collector electrode 3 and each p + -type contact layer 4 A.
  • the silicide layer 5 is formed by, for example, a thermal treatment in which atoms (e.g. aluminum atoms) constituting the electrode 3 react with atoms (silicon atoms) constituting the semiconductor substrate 1 .
  • the depth of the silicide layer 5 from the other surface of the semiconductor substrate 1 is set equal to or shallower than the depth of each p + -type contact layer 4 A from the other surface of the semiconductor substrate 1 .
  • the depth of each p + -type contact layer 4 A from the other surface of the semiconductor substrate 1 is set at 0.2 ⁇ m or less, the depth of the silicide layer 5 from the surface of the semiconductor substrate 1 is also set at 0.2 ⁇ m or less.
  • the collector electrode 3 is electrically connected to the lowest resistance portion of each p + -type contact layer 4 A (corresponding to a portion thereof at which the concentration profile assumes the peak value) via the silicide layer 5 , thereby reducing the contact resistance.
  • the p + -type emitter layers 2 A have a low impurity concentration, and a sufficiently shallow depth of 1.0 ⁇ m or less from the other surface of the semiconductor substrate 1 . Accordingly, the carrier (positive hole) injection coefficient when turning off the IGBT can be reduced, thereby increasing the speed of the turn-off operation.
  • the carrier injection coefficient can be controlled by changing the depth of the p + -type emitter layers 2 A or contact ratio W 1 /W 2 .
  • the p ++ -type contact layers 4 which have a higher impurity concentration than the p + -type emitter layers 2 A and are provided between the respective p + -type emitter layers 2 A and the collector electrode 3 , are set to have a depth of 0.2 ⁇ m or less from the other surface of the semiconductor substrate 1 , they do not influence the carrier injection coefficient at the time of turning off the IGBT. In other words, the p ++ -type contact layers 4 A do not increase the carrier injection coefficient.
  • the p ++ -type contact layers 4 have a sufficiently high impurity concentration, and the silicide layer 5 is provided between the collector electrode 3 and each p ++ -type contact layer 4 A.
  • the position of the bottom of the silicide layer 5 is made to correspond to that portion of each p ++ -type contact layer 4 A, at which the concentration profile of the layer 4 A assumes a peak value. Accordingly, the contact resistance of the electrode contact section is further reduced.
  • the electrode contact section of the IGBT according to the invention enables the simultaneous realization of a sufficient reduction of the contact resistance and reduction of the carrier injection coefficient.
  • the semiconductor substrate 1 is of the n-type and the emitter layers 2 A and the contact layers 4 A are of the p-type, the same advantage can be obtained by making the semiconductor substrate 1 be of the p-type and the emitter layers 2 A and the contact layers 4 A be of the n-type.
  • an n-type semiconductor substrate e.g. a silicon substrate 1 having, for example, an impurity concentration of approx. 1.5 ⁇ 10 14 ions/cm 2 is prepared.
  • a p-type base layer 7 , an n + -type emitter layer 8 , an insulating film 9 , a gate electrode 10 and an emitter electrode 11 are formed on one surface of the semiconductor substrate 1 .
  • a p-type impurity such as boron (B) is implanted into the other surface of the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 60 keV and approx. 1 ⁇ 10 13 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 1050° C. for approx. 20 min.
  • p + -type emitter layers 2 A having a depth of approx. 0.8 ⁇ m from the other surface of the semiconductor substrate 1 are formed.
  • a p-type impurity such as boron (B) is implanted into the p + -type emitter layers 2 A in the other surface of the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 10 keV and approx. 1 ⁇ 10 14 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 800° C. for approx. 30 min.
  • p ++ -type contact layers 4 A having a depth of approx. 0.16 ⁇ m from the other surface of the semiconductor substrate 1 are formed.
  • the p ++ -type contact layers 4 A must be formed very shallow, and must have a very high impurity concentration. To this end, the acceleration voltage is set low, the dose is set high, and the period for executing the thermal diffusion process is set short, as is described above.
  • Boron fluoride (BF 2 ) may be used as the p-type impurity, instead of boron (B) (i.e. the element is changed from a light one to a heavy one), and implanted into the p + -type emitter layers 2 A in the semiconductor substrate 1 , thereby forming p ++ -type contact layers 4 A.
  • B boron
  • a thermal oxide film formed on a surface portion of the other surface of the semiconductor substrate 1 i.e. on a surface portion of the p ++ -type contact layers 4 A, is removed using antimony fluoride.
  • an insulating film 6 is formed on the other surface side of the semiconductor substrate 1 by, for example, CVD.
  • the insulating film 6 is patterned by PEP or RIE, thereby forming contact holes that extend to the respective p ++ -type contact layers 4 A.
  • a collector electrode 3 extending to the p ++ -type contact layers 4 A is formed by sputtering or CVD.
  • the resultant structure is subjected to a heat treatment executed for approx. 30 min. in the atmosphere of nitrogen of approx. 450° C., thereby diffusing the atoms (e.g. aluminum atoms) of the collector electrode 3 into the semiconductor substrate 1 , i.e. into the p ++ -type contact layers 4 A, so as to form a silicide layer 5 .
  • the thickness of the silicide layer 5 (the depth from the surface of the semiconductor substrate 1 ) is made substantially equal to that thickness of each p + -type contact layer 4 A from the other surface of the semiconductor substrate 1 , at which the concentration profile of each layer 4 A assumes a peak value.
  • the silicide layer 5 is made to have a thickness of approx. 0.04 ⁇ m.
  • the collector electrode 3 may be formed after forming the silicide layer 5 .
  • FIG. 11 shows an IGBT as a fifth example of the invention.
  • This example relates to a so-called collector-short-circuited (or anode-short-circuited) IGBT (a reference example) as shown in FIG. 10, to which the above-described first electrode contact section is applied.
  • a p-type base layer 7 is formed on one surface of an n-type semiconductor substrate (n-type base layer) 1 , and an n + -type emitter layer 8 is formed in the p-type base layer 7 .
  • a gate electrode 10 is formed on the p-type base layer (channel section) 7 between the n-type base layer 1 and the n + -type emitter layer 8 , with an insulating layer 9 interposed therebetween.
  • an emitter electrode 11 is formed on the p-type base layer 7 and the n + -type emitter layer 8 .
  • a plurality of p + -type emitter layers 2 B and a plurality of n + -type base layers 12 are formed on the other surface of the semiconductor substrate 1 .
  • Each p + -type emitter layer 2 B contains a p-type impurity such as boron (B).
  • the depth of each p + -type emitter layer 2 B from the other surface of the semiconductor substrate 1 is set at 1.0 ⁇ m or less, for example, approx. 0.8 ⁇ m.
  • the peak value of the concentration profile of each p + -type emitter layer 2 B is set at a value falling within the range of 10 17 -10 18 ions/cm 3 .
  • a p ++ -type contact layer 4 B is formed in each p + -type emitter layer 2 B, and a collector electrode 3 is formed on the resultant p ++ -type contact layers 4 B. Further, the p ++ -type contact layers 4 B are interposed between the respective p + -type emitter layers 2 B and the collector electrode 3 , and have a higher impurity concentration than the p + -type emitter layers 2 B.
  • each p ++ -type contact layer 4 B contains a p-type impurity such as boron (B) or boron fluoride (BF 2 ), etc., and has an impurity concentration peak value of 10 19 ions/cm 3 or more and a surface impurity concentration of 10 18 ions/cm 3 or more.
  • the depth of each p ++ -type contact layer 4 B from the other surface of the semiconductor substrate 1 is set at 0.2 ⁇ m or less, for example, approx. 0.16 ⁇ m.
  • the collector electrode 3 is formed of, for example, aluminum.
  • the p + -type emitter layers 2 B have a low impurity concentration, and a sufficiently shallow depth of 1.0 ⁇ m or less from the other surface of the semiconductor substrate 1 . Accordingly, the carrier (positive hole) injection coefficient when turning off the IGBT can be reduced, thereby increasing the speed of the turn-off operation.
  • the p ++ -type contact layers 4 B which have a higher impurity concentration than the p + -type emitter layers 2 B and are provided between the respective p + -type emitter layers 2 B and the collector electrode 3 , are set to have a depth of 0.2 ⁇ m or less from the other surface of the semiconductor substrate 1 , they do not influence the carrier injection coefficient at the time of turning off the IGBT. In other words, the p ++ -type contact layers 4 B do not increase the carrier injection coefficient.
  • the electrode contact section of the IGBT according to the invention enables the simultaneous realization of a sufficient reduction of the contact resistance and reduction of the carrier injection coefficient.
  • the semiconductor substrate 1 is of the n-type and the emitter layers 2 B and the contact layers 4 B are of the p-type, the same advantage can be obtained by making the semiconductor substrate 1 be of the p-type and the emitter layers 2 B and the contact layers 4 B be of the n-type.
  • an n-type semiconductor substrate e.g. a silicon substrate 1 having, for example, an impurity concentration of approx. 1.5 ⁇ 10 14 ions/cm 2 is prepared.
  • a p-type base layer 7 , an n+-type emitter layer 8 , an insulating film 9 , a gate electrode 10 and an emitter electrode 11 are formed on one surface of the semiconductor substrate 1 .
  • an n-type impurity such as phosphor (P) is implanted into the other surface of the semiconductor substrate 1 by ion implantation, and subjected to a thermal diffusion treatment, thereby forming an n + -type base layer 12 in a surface portion of the other surface of the semiconductor substrate 1 .
  • a p-type impurity such as boron (B) is implanted into the other surface of the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 60 keV and approx. 1 ⁇ 10 13 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 1050° C. for approx. 20 min.
  • p + -type emitter layers 2 B having a depth of approx. 0.8 ⁇ m from the other surface of the semiconductor substrate 1 are formed.
  • a p-type impurity such as boron (B) is implanted into the p + -type emitter layers 2 B in the other surface of the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 10 keV and approx. 1 ⁇ 10 14 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 800° C. for approx. 30 min.
  • p ++ -type contact layers 4 B having a depth of approx. 0.16 ⁇ m from the other surface of the semiconductor substrate 1 are formed.
  • the p ++ -type contact layers 4 B must be formed very shallow, and must have a very high impurity concentration. To this end, the acceleration voltage is set low, the dose is set high, and the period for executing the thermal diffusion process is set short, as is described above.
  • Boron fluoride (BF 2 ) may be used as the p-type impurity, instead of boron (B) (i.e. the element is changed from a light one to a heavy one), and implanted into the p + -type emitter layers 2 B in the semiconductor substrate 1 , thereby forming p ++ -type contact layers 4 B.
  • B boron
  • a thermal oxide film formed on a surface portion of the other surface of the semiconductor substrate 1 i.e. on a surface portion of the p ++ -type contact layers 4 B, is removed using antimony fluoride.
  • a collector electrode 3 extending to the p ++ -type contact layers 4 B and the n + -type base layers 12 is formed by sputtering or CVD.
  • the resultant structure is subjected to a heat treatment executed for approx. 30 min. in the atmosphere of nitrogen of approx. 450° C., thereby diffusing the atoms (e.g. aluminum atoms) of the collector electrode 3 into the semiconductor substrate 1 , i.e. into the p ++ -type contact layers 4 B and the n + -type base layers 12 , so as to reduce the contact resistance between the collector electrode 3 and the p ++ -type contact layers 4 B, and that between the collector electrode 3 and the n + -type base layers 12 .
  • atoms e.g. aluminum atoms
  • FIG. 12 shows an IGBT as a sixth example of the invention.
  • This example relates to a so-called collector-short-circuited (or anode-short-circuited) IGBT (a reference example) as shown in FIG. 10, to which the above-described second electrode contact section is applied.
  • a p-type base layer 7 is formed on one surface of an n-type semiconductor substrate (n-type base layer) 1 , and an n + -type emitter layer 8 is formed in the p-type base layer 7 .
  • a gate electrode 10 is formed on the p-type base layer (channel section) 7 between the n-type base layer 1 and the n + -type emitter layer 8 , with an insulating layer 9 interposed therebetween.
  • an emitter electrode 11 is formed on the p-type base layer 7 and the n + -type emitter layer 8 .
  • a plurality of p + -type emitter layers 2 B and a plurality of n + -type base layers 12 are formed on the other surface of the semiconductor substrate 1 .
  • Each p + -type emitter layer 2 B contains a p-type impurity such as boron (B).
  • the depth of each p + -type emitter layer 2 B from the other surface of the semiconductor substrate 1 is set at 1.0 ⁇ m or less, for example, approx. 0.8 ⁇ m.
  • the peak value of the concentration profile of each p + -type emitter layer 2 B is set at a value falling within the range of 10 17 -10 18 ions/cm 3 .
  • a p ++ -type contact layer 4 B is formed in each p + -type emitter layer 2 B, and a collector electrode 3 is formed on the resultant p ++ -type contact layers 4 B. Further, the p ++ -type contact layers 4 B are interposed between the respective p + -type emitter layers 2 B and the collector electrode 3 , and have a higher impurity concentration than the p + -type emitter layers 2 B.
  • each p ++ -type contact layer 4 B contains a p-type impurity such as boron (B) or boron fluoride (BF 2 ), etc., and has an impurity concentration peak value of 10 19 ions/cm 3 or more and a surface impurity concentration of 10 18 ions/cm 3 or more.
  • the depth of each p ++ -type contact layer 4 B from the other surface of the semiconductor substrate 1 is set at 0.2 ⁇ m or less, for example, approx. 0.16 ⁇ m.
  • the collector electrode 3 is formed of, for example, aluminum.
  • a silicide layer 5 is provided between the collector electrode 3 and each p + -type contact layer 4 B and the collector electrode and each n + -type base layer 12 .
  • the silicide layer 5 is formed by, for example, a thermal treatment in which atoms (e.g. aluminum atoms) constituting the electrode 3 react with atoms (silicon atoms) constituting the semiconductor substrate 1 .
  • the depth of the silicide layer 5 from the other surface of the semiconductor substrate 1 is set equal to or shallower than the depth of each p + -type contact layer 4 B from the other surface of the semiconductor substrate 1 .
  • the depth of each p + -type contact layer 4 B from the other surface of the semiconductor substrate 1 is set at 0.2 ⁇ m or less, the depth of the silicide layer 5 from the surface of the semiconductor substrate 1 is also set at 0.2 ⁇ m or less.
  • the collector electrode 3 is electrically connected to the lowest resistance portion of each p + -type contact layer 4 B (corresponding to a portion thereof at which the concentration profile assumes the peak value) via the silicide layer 5 , thereby reducing the contact resistance.
  • the p + -type emitter layers 2 B have a low impurity concentration, and a sufficiently shallow depth of 1.0 ⁇ m or less from the other surface of the semiconductor substrate 1 . Accordingly, the carrier (positive hole) injection coefficient when turning off the IGBT can be reduced, thereby increasing the speed of the turn-off operation.
  • the p ++ -type contact layers 4 B which have a higher impurity concentration than the p + -type emitter layers 2 B and are provided between the respective p + -type emitter layers 2 B and the collector electrode 3 , are set to have a depth of 0.2 ⁇ m or less from the other surface of the semiconductor substrate 1 , they do not influence the carrier injection coefficient at the time of turning off the IGBT. In other words, the p ++ -type contact layers 4 B do not increase the carrier injection coefficient.
  • the p ++ -type contact layers 4 B have a sufficiently high impurity concentration
  • the silicide layer 5 is provided between the collector electrode 3 and each p + -type contact layer 4 B and between the collector electrode 3 and each n + -type base layer 12 .
  • the position of the bottom of the silicide layer 5 is made to correspond to that portion of each p + -type contact layer 4 B, at which the concentration profile of each layer 4 B assumes a peak value. Accordingly, the contact resistance of the electrode contact section is further reduced.
  • the electrode contact section of the IGBT according to the invention enables the simultaneous realization of a sufficient reduction of the contact resistance and reduction of the carrier injection coefficient.
  • the semiconductor substrate 1 is of the n-type and the emitter layers 2 B and the contact layers 4 B are of the p-type, the same advantage can be obtained by making the semiconductor substrate 1 be of the p-type and the emitter layers 2 B and the contact layers 4 B be of the n-type.
  • an n-type semiconductor substrate e.g. a silicon substrate 1 having, for example, an impurity concentration of approx. 1.5 ⁇ 10 14 ions/cm 2 is prepared.
  • a p-type base layer 7 , an n+-type emitter layer 8 , an insulating film 9 , a gate electrode 10 and an emitter electrode 11 are formed on one surface of the semiconductor substrate 1 .
  • an n-type impurity such as phosphor (P) is implanted into the other surface of the semiconductor substrate 1 by ion implantation, and subjected to a thermal diffusion treatment, thereby forming an n + -type base layer 12 in a surface portion of the other surface of the semiconductor substrate 1 .
  • a p-type impurity such as boron (B) is implanted into the other surface of the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 60 keV and approx. 1 ⁇ 10 13 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 1050° C. for approx. 20 min.
  • p + -type emitter layers 2 B having a depth of approx. 0.8 ⁇ m from the other surface of the semiconductor substrate 1 are formed.
  • a p-type impurity such as boron (B) is implanted into the p + -type emitter layers 2 B in the other surface of the semiconductor substrate 1 by ion implantation.
  • the acceleration voltage and the dose, as implantation conditions are set at, for example, approx. 10 keV and approx. 1 ⁇ 10 14 ions/cm 2 , respectively.
  • the resultant structure is subjected to a thermal diffusion process executed in the atmosphere of nitrogen of approx. 800° C. for approx. 30 min.
  • p ++ -type contact layers 4 B having a depth of approx. 0.16 ⁇ m from the other surface of the semiconductor substrate 1 are formed.
  • the p ++ -type contact layers 4 B must be formed very shallow, and must have a very high impurity concentration. To this end, the acceleration voltage is set low, the dose is set high, and the period for executing the thermal diffusion process is set short, as is described above.
  • Boron fluoride (BF 2 ) may be used as the p-type impurity, instead of boron (B) (i.e. the element is changed from a light one to a heavy one), and implanted into the p + -type emitter layers 2 B in the semiconductor substrate 1 , thereby forming p ++ -type contact layers 4 B.
  • B boron
  • a thermal oxide film formed on a surface portion of the other surface of the semiconductor substrate 1 i.e. on a surface portion of the p ++ -type contact layers 4 B, is removed using antimony fluoride.
  • a collector electrode 3 having a thickness of approx. 0.05 ⁇ m is formed on the p ++ -type contact layers 4 B and the n + -type base layers 12 by sputtering or CVD.
  • the resultant structure is subjected to a heat treatment executed for approx. 30 min. in the atmosphere of nitrogen of approx. 450° C., thereby diffusing the atoms (e.g. aluminum atoms) of the collector electrode 3 into the semiconductor substrate 1 , i.e. into the p ++ -type contact layers 4 B and the n + -type base layers 12 , so as to form a silicide layer 5 .
  • the thickness of the silicide layer 5 (the depth from the other surface of the semiconductor substrate 1 ) is made substantially equal to that thickness of each p ++ -type contact layer 4 B from the other surface of the semiconductor substrate 1 , at which the concentration profile of each layer 4 B assumes a peak value.
  • the silicide layer 5 is made to have a thickness of approx. 0.04 ⁇ m.
  • the collector electrode 3 may be formed after forming the silicide layer 5 .
  • the peak value of the concentration profile of the p-type impurity layer (the p + -type emitter layer) is set at a value falling within the range of 10 17 -10 18 ions/cm 3 .
  • the depth of the p-type impurity layer from the surface of the semiconductor substrate is set at a sufficient low value of 1.0 ⁇ m or less. Accordingly, the carrier injection coefficient when turning off the IGBT can be reduced, thereby increasing the speed of the turn-off operation.
  • a p + -type contact layer having a higher impurity concentration than the p-type impurity layer is provided between the p-type impurity layer and the electrode 3 . Since the depth of the p + -type contact layer from the surface of the semiconductor substrate is set at 0.2 ⁇ m or less, the p + -type contact layer does not influence the carrier injection coefficient at the time of turning off the semiconductor device. Further, since the peak value of the concentration profile of the p + -type contact layer is set at approx. 10 19 ions/cm 3 , the contact resistance of the electrode contact section is reduced.
  • the p + -type contact layer has a sufficiently high impurity concentration
  • a silicide layer is provided between the electrode and the p + -type contact layer.
  • the position of the bottom of the silicide layer is made to correspond to that portion of the p + -type contact layer, at which the concentration profile of the contact layer assumes a peak value. Accordingly, the contact resistance of the electrode contact section is further reduced.

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US20040144992A1 (en) * 2002-10-30 2004-07-29 Armin Willmeroth IGBT with monolithic integrated antiparallel diode
US20050017290A1 (en) * 2003-07-24 2005-01-27 Mitsubishi Denki Kabushiki Kaisha Insulated gate bipolar transistor with built-in freewheeling diode
US20080064148A1 (en) * 2005-01-27 2008-03-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing process thereof
US20100301386A1 (en) * 2009-06-02 2010-12-02 Wei-Chieh Lin Integrated structure of igbt and diode and method of forming the same
US20110033988A1 (en) * 1995-03-23 2011-02-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20120187416A1 (en) * 2011-01-24 2012-07-26 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing semiconductor device
US20130029461A1 (en) * 2011-07-27 2013-01-31 Anup Bhalla Methods for fabricating anode shorted field stop insulated gate bipolar transistor
US9070737B2 (en) 2010-10-27 2015-06-30 Fuji Electric Co., Ltd. Semiconductor device with low-lifetime region
US20160155735A1 (en) * 2007-11-30 2016-06-02 Infineon Technologies Ag Semiconductor component including a short-circuit structure
US10290729B2 (en) 2012-06-11 2019-05-14 Renesas Electronics Corporation Narrow active cell IE type trench gate IGBT and a method for manufacturing a narrow active cell IE type trench gate IGBT
CN113345959A (zh) * 2020-03-02 2021-09-03 三菱电机株式会社 半导体装置及半导体装置的制造方法

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CN100461619C (zh) * 2004-12-24 2009-02-11 立积电子股份有限公司 功率放大器及其形成方法
JP2006228961A (ja) * 2005-02-17 2006-08-31 Toyota Central Res & Dev Lab Inc 半導体装置
DE102005032074B4 (de) * 2005-07-08 2007-07-26 Infineon Technologies Austria Ag Halbleiterbauelement mit Feldstopp
JP2008042013A (ja) * 2006-08-08 2008-02-21 Sanyo Electric Co Ltd 半導体装置の製造方法
US8507352B2 (en) * 2008-12-10 2013-08-13 Denso Corporation Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode
WO2012042640A1 (ja) * 2010-09-30 2012-04-05 株式会社日立製作所 半導体装置
WO2015049788A1 (ja) * 2013-10-04 2015-04-09 株式会社日立製作所 半導体装置およびその製造方法、並びに電力変換器
JP2016201563A (ja) * 2016-07-26 2016-12-01 ルネサスエレクトロニクス株式会社 狭アクティブセルｉｅ型トレンチゲートｉｇｂｔ

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US10290729B2 (en) 2012-06-11 2019-05-14 Renesas Electronics Corporation Narrow active cell IE type trench gate IGBT and a method for manufacturing a narrow active cell IE type trench gate IGBT
CN113345959A (zh) * 2020-03-02 2021-09-03 三菱电机株式会社 半导体装置及半导体装置的制造方法

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US7271040B2 (en) 2007-09-18
US20060125005A1 (en) 2006-06-15

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