UA98989C2 - Адаптация ширины импульсов словарной шины в запоминающих системах - Google Patents

Адаптация ширины импульсов словарной шины в запоминающих системах Download PDF

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Publication number
UA98989C2
UA98989C2 UAA201008919A UAA201008919A UA98989C2 UA 98989 C2 UA98989 C2 UA 98989C2 UA A201008919 A UAA201008919 A UA A201008919A UA A201008919 A UAA201008919 A UA A201008919A UA 98989 C2 UA98989 C2 UA 98989C2
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UA
Ukraine
Prior art keywords
pulse width
self
test
memory device
pulse
Prior art date
Application number
UAA201008919A
Other languages
English (en)
Ukrainian (uk)
Inventor
Мохамед Х. Абу-Рахма
Сей Сеунг ЙООН
Original Assignee
Квелкомм Инкорпорейтед
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Квелкомм Инкорпорейтед filed Critical Квелкомм Инкорпорейтед
Publication of UA98989C2 publication Critical patent/UA98989C2/ru

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0407—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals on power on
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1202—Word line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Раскрыты системы, схемы и способы для адаптации ширины импульсов словарной шины (WL), которая используется в запоминающих системах. Один вариант осуществления изобретения направлен на устройство, содержащее запоминающую систему. Запоминающая система содержит: запоминающее устройство, работающее по импульсам словарной шины (WL) с ассоциированной шириной импульса WL; модуль встроенного самотестирования (BIST), который взаимодействует с запоминающим устройством, причем BIST-модуль выполнен с возможностью проводить самотестирование внутренней функциональности запоминающего устройства и предоставлять сигнал, который указывает на то, прошло или не прошло самотестирование запоминающее устройс
UAA201008919A 2007-12-17 2008-12-15 Адаптация ширины импульсов словарной шины в запоминающих системах UA98989C2 (ru)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US1425707P 2007-12-17 2007-12-17

Publications (1)

Publication Number Publication Date
UA98989C2 true UA98989C2 (ru) 2012-07-10

Family

ID=40754896

Family Applications (1)

Application Number Title Priority Date Filing Date
UAA201008919A UA98989C2 (ru) 2007-12-17 2008-12-15 Адаптация ширины импульсов словарной шины в запоминающих системах

Country Status (15)

Country Link
US (1) US7882407B2 (ru)
EP (1) EP2232502B1 (ru)
JP (3) JP2011507148A (ru)
KR (2) KR20130042652A (ru)
CN (2) CN107068197B (ru)
AU (1) AU2008338531B2 (ru)
BR (1) BRPI0821275B1 (ru)
CA (1) CA2709424C (ru)
CR (1) CR11503A (ru)
IL (1) IL206374A (ru)
MX (1) MX2010006685A (ru)
MY (1) MY152831A (ru)
RU (1) RU2455713C2 (ru)
UA (1) UA98989C2 (ru)
WO (1) WO2009079457A1 (ru)

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EP2529374A4 (en) 2010-01-28 2014-04-02 Hewlett Packard Development Co MEMORY ACCESS METHODS AND APPARATUS
US9146867B2 (en) 2011-10-31 2015-09-29 Hewlett-Packard Development Company, L.P. Methods and apparatus to access memory using runtime characteristics
US8787099B2 (en) 2012-06-20 2014-07-22 Lsi Corporation Adjusting access times to memory cells based on characterized word-line delay and gate delay
US8773927B2 (en) 2012-09-07 2014-07-08 Lsi Corporation Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay
TWI489245B (zh) * 2012-12-04 2015-06-21 Univ Nat Cheng Kung 具有能預測因製程與環境變異所造成時序錯誤的嵌入式脈衝時序電路系統
US9514844B2 (en) * 2014-08-26 2016-12-06 Globalfoundries Inc. Fast auto shift of failing memory diagnostics data using pattern detection
US9437318B2 (en) 2014-10-24 2016-09-06 Sandisk Technologies Llc Adaptive program pulse duration based on temperature
US9606742B1 (en) * 2015-12-14 2017-03-28 Oracle International Corporation Variable pulse widths for word line activation using power state information
US10768230B2 (en) 2016-05-27 2020-09-08 International Business Machines Corporation Built-in device testing of integrated circuits
US11403241B2 (en) 2017-10-02 2022-08-02 Micron Technology, Inc. Communicating data with stacked memory dies
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US10446198B2 (en) 2017-10-02 2019-10-15 Micron Technology, Inc. Multiple concurrent modulation schemes in a memory system
US10522218B2 (en) * 2017-11-15 2019-12-31 Samsung Electronics Co., Ltd. Methods and apparatuses to reduce power dissipation in a static random access memory (SRAM) device
US10783299B1 (en) * 2018-03-27 2020-09-22 Cadence Design Systems, Inc. Simulation event reduction and power control during MBIST through clock tree management
CN109658964B (zh) * 2018-11-15 2020-08-14 长江存储科技有限责任公司 闪存器的数据写入方法及装置、存储设备及存储介质
US10930364B2 (en) * 2018-11-16 2021-02-23 International Business Machines Corporation Iterative functional test exerciser reload and execution
CN111128264B (zh) * 2019-12-05 2021-08-06 海光信息技术股份有限公司 字线脉冲电路、字线脉冲侦测方法、读方法、芯片及设备
US12068024B2 (en) * 2022-04-30 2024-08-20 Ceremorphic, Inc. Address dependent wordline timing in asynchronous static random access memory

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JP3591887B2 (ja) * 1994-09-12 2004-11-24 富士通株式会社 半導体記憶装置
US5796993A (en) * 1996-10-29 1998-08-18 Maguire; Jeffrey E. Method and apparatus for semiconductor device optimization using on-chip verification
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Also Published As

Publication number Publication date
JP2014139857A (ja) 2014-07-31
US20090158101A1 (en) 2009-06-18
RU2455713C2 (ru) 2012-07-10
JP5490928B2 (ja) 2014-05-14
CA2709424C (en) 2013-12-10
CR11503A (es) 2010-08-11
CA2709424A1 (en) 2009-06-25
BRPI0821275A2 (pt) 2015-09-15
AU2008338531B2 (en) 2012-07-19
KR101274626B1 (ko) 2013-06-13
IL206374A (en) 2014-07-31
JP2011507148A (ja) 2011-03-03
JP5763233B2 (ja) 2015-08-12
IL206374A0 (en) 2010-12-30
US7882407B2 (en) 2011-02-01
RU2010129841A (ru) 2012-01-27
AU2008338531A1 (en) 2009-06-25
MY152831A (en) 2014-11-28
EP2232502A1 (en) 2010-09-29
CN107068197A (zh) 2017-08-18
KR20100094585A (ko) 2010-08-26
EP2232502B1 (en) 2016-11-09
KR20130042652A (ko) 2013-04-26
CN101925963A (zh) 2010-12-22
CN107068197B (zh) 2019-03-15
MX2010006685A (es) 2010-11-12
BRPI0821275B1 (pt) 2020-03-17
JP2013137856A (ja) 2013-07-11
WO2009079457A1 (en) 2009-06-25

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