CR11503A - Adaptar anchos de pulso de linea de palabra en sistemas de memoria - Google Patents

Adaptar anchos de pulso de linea de palabra en sistemas de memoria

Info

Publication number
CR11503A
CR11503A CR11503A CR11503A CR11503A CR 11503 A CR11503 A CR 11503A CR 11503 A CR11503 A CR 11503A CR 11503 A CR11503 A CR 11503A CR 11503 A CR11503 A CR 11503A
Authority
CR
Costa Rica
Prior art keywords
word line
pulse widths
adapt
line pulse
memory systems
Prior art date
Application number
CR11503A
Other languages
English (en)
Inventor
H Abu-Rahma Mohamed
Seung Yoon Sei
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CR11503A publication Critical patent/CR11503A/es

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0407—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals on power on
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1202—Word line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Se divulgan sistemas, circuitos y metodos para adaptar anchos de pulso de linea de palabra (WL) usados en sistemas de memoria. Un formato de la invencion se dirige a un aparato que comprende un sistema de memoria.
CR11503A 2007-12-17 2010-06-16 Adaptar anchos de pulso de linea de palabra en sistemas de memoria CR11503A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US1425707P 2007-12-17 2007-12-17
US12/328,156 US7882407B2 (en) 2007-12-17 2008-12-04 Adapting word line pulse widths in memory systems

Publications (1)

Publication Number Publication Date
CR11503A true CR11503A (es) 2010-08-11

Family

ID=40754896

Family Applications (1)

Application Number Title Priority Date Filing Date
CR11503A CR11503A (es) 2007-12-17 2010-06-16 Adaptar anchos de pulso de linea de palabra en sistemas de memoria

Country Status (15)

Country Link
US (1) US7882407B2 (es)
EP (1) EP2232502B1 (es)
JP (3) JP2011507148A (es)
KR (2) KR20130042652A (es)
CN (2) CN101925963A (es)
AU (1) AU2008338531B2 (es)
BR (1) BRPI0821275B1 (es)
CA (1) CA2709424C (es)
CR (1) CR11503A (es)
IL (1) IL206374A (es)
MX (1) MX2010006685A (es)
MY (1) MY152831A (es)
RU (1) RU2455713C2 (es)
UA (1) UA98989C2 (es)
WO (1) WO2009079457A1 (es)

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JP2006331511A (ja) * 2005-05-25 2006-12-07 Matsushita Electric Ind Co Ltd 半導体記憶装置およびその検査手法
WO2011094437A2 (en) 2010-01-28 2011-08-04 Hewlett-Packard Development Company, L.P. Memory access methods and apparatus
US9146867B2 (en) 2011-10-31 2015-09-29 Hewlett-Packard Development Company, L.P. Methods and apparatus to access memory using runtime characteristics
US8787099B2 (en) 2012-06-20 2014-07-22 Lsi Corporation Adjusting access times to memory cells based on characterized word-line delay and gate delay
US8773927B2 (en) 2012-09-07 2014-07-08 Lsi Corporation Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay
TWI489245B (zh) * 2012-12-04 2015-06-21 Univ Nat Cheng Kung 具有能預測因製程與環境變異所造成時序錯誤的嵌入式脈衝時序電路系統
US9514844B2 (en) * 2014-08-26 2016-12-06 Globalfoundries Inc. Fast auto shift of failing memory diagnostics data using pattern detection
US9437318B2 (en) 2014-10-24 2016-09-06 Sandisk Technologies Llc Adaptive program pulse duration based on temperature
US9606742B1 (en) * 2015-12-14 2017-03-28 Oracle International Corporation Variable pulse widths for word line activation using power state information
US10768230B2 (en) 2016-05-27 2020-09-08 International Business Machines Corporation Built-in device testing of integrated circuits
US10725913B2 (en) 2017-10-02 2020-07-28 Micron Technology, Inc. Variable modulation scheme for memory device access or operation
US11403241B2 (en) 2017-10-02 2022-08-02 Micron Technology, Inc. Communicating data with stacked memory dies
US10446198B2 (en) * 2017-10-02 2019-10-15 Micron Technology, Inc. Multiple concurrent modulation schemes in a memory system
US10783299B1 (en) * 2018-03-27 2020-09-22 Cadence Design Systems, Inc. Simulation event reduction and power control during MBIST through clock tree management
CN109658964B (zh) * 2018-11-15 2020-08-14 长江存储科技有限责任公司 闪存器的数据写入方法及装置、存储设备及存储介质
US10930364B2 (en) * 2018-11-16 2021-02-23 International Business Machines Corporation Iterative functional test exerciser reload and execution
CN111128264B (zh) * 2019-12-05 2021-08-06 海光信息技术股份有限公司 字线脉冲电路、字线脉冲侦测方法、读方法、芯片及设备
US20230352082A1 (en) * 2022-04-30 2023-11-02 Ceremorphic, Inc. Dynamic Adjustment of Word Line Timing in Static Random Access Memory

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JPH07130183A (ja) * 1993-10-29 1995-05-19 Sony Corp チューニング回路
JP3591887B2 (ja) * 1994-09-12 2004-11-24 富士通株式会社 半導体記憶装置
US5796993A (en) * 1996-10-29 1998-08-18 Maguire; Jeffrey E. Method and apparatus for semiconductor device optimization using on-chip verification
US6161204A (en) * 1998-02-17 2000-12-12 Micron Technology, Inc. Method and apparatus for testing SRAM memory cells
US6535752B1 (en) * 1999-04-01 2003-03-18 Ericsson Inc. Radio receiver with power saving during synchronization retries
JP2001057083A (ja) * 1999-08-11 2001-02-27 Hitachi Ltd 半導体記憶装置
JP2001101868A (ja) 1999-09-30 2001-04-13 Hitachi Ltd 半導体記憶装置
US6341093B1 (en) 2000-06-07 2002-01-22 International Business Machines Corporation SOI array sense and write margin qualification
JP2002025292A (ja) 2000-07-11 2002-01-25 Hitachi Ltd 半導体集積回路
JP2003242799A (ja) * 2002-02-12 2003-08-29 Hitachi Ltd 半導体集積回路
JP2004178729A (ja) 2002-11-28 2004-06-24 Hitachi Ltd 半導体記憶装置
RU2297032C2 (ru) * 2004-07-14 2007-04-10 Институт Инженерной Физики Российская Федерация (Ииф Рф) Самокорректирующееся запоминающее устройство
JP2006331511A (ja) * 2005-05-25 2006-12-07 Matsushita Electric Ind Co Ltd 半導体記憶装置およびその検査手法
US7355902B2 (en) 2006-05-11 2008-04-08 International Business Machines Corporation Methods and apparatus for inline characterization of high speed operating margins of a storage element
US7606097B2 (en) * 2006-12-27 2009-10-20 Micron Technology, Inc. Array sense amplifiers, memory devices and systems including same, and methods of operation
US7760565B2 (en) * 2007-07-24 2010-07-20 International Business Machines Corporation Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance
US7505340B1 (en) 2007-08-28 2009-03-17 International Business Machines Corporation Method for implementing SRAM cell write performance evaluation

Also Published As

Publication number Publication date
KR101274626B1 (ko) 2013-06-13
KR20130042652A (ko) 2013-04-26
JP2014139857A (ja) 2014-07-31
JP5490928B2 (ja) 2014-05-14
IL206374A0 (en) 2010-12-30
JP2011507148A (ja) 2011-03-03
WO2009079457A1 (en) 2009-06-25
CA2709424A1 (en) 2009-06-25
RU2455713C2 (ru) 2012-07-10
US20090158101A1 (en) 2009-06-18
CN101925963A (zh) 2010-12-22
RU2010129841A (ru) 2012-01-27
US7882407B2 (en) 2011-02-01
MX2010006685A (es) 2010-11-12
UA98989C2 (uk) 2012-07-10
AU2008338531B2 (en) 2012-07-19
BRPI0821275B1 (pt) 2020-03-17
AU2008338531A1 (en) 2009-06-25
BRPI0821275A2 (pt) 2015-09-15
JP5763233B2 (ja) 2015-08-12
CA2709424C (en) 2013-12-10
KR20100094585A (ko) 2010-08-26
IL206374A (en) 2014-07-31
JP2013137856A (ja) 2013-07-11
MY152831A (en) 2014-11-28
CN107068197B (zh) 2019-03-15
EP2232502A1 (en) 2010-09-29
CN107068197A (zh) 2017-08-18
EP2232502B1 (en) 2016-11-09

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