TWI776164B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI776164B
TWI776164B TW109118400A TW109118400A TWI776164B TW I776164 B TWI776164 B TW I776164B TW 109118400 A TW109118400 A TW 109118400A TW 109118400 A TW109118400 A TW 109118400A TW I776164 B TWI776164 B TW I776164B
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wiring board
adhesive layer
semiconductor
semiconductor device
chip
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TW109118400A
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TW202111897A (zh
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本間荘一
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日商鎧俠股份有限公司
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Abstract

本實施形態之半導體裝置係具備電性連接於設在絕緣基板的配線的焊墊。配線基板係具有設在焊墊間的第1絕緣材。第1半導體晶片係在與該配線基板相對向的第1面具有連接於配線基板的焊墊的金屬凸塊。第1接著層係設在第1絕緣材與第1半導體晶片之間，且將配線基板與第1半導體晶片接著。絕緣樹脂係在配線基板與第1半導體晶片之間，以覆蓋第1接著層及金屬凸塊的周圍與前述配線基板上的構造體的方式而設。

Description

半導體裝置及其製造方法
在此說明的複數形的實施形態整體而言係關於半導體裝置及其製造方法。 關連申請案的引用 本申請案係以2019年9月12日申請之前案日本專利申請第2019-166283號所得之優先權的利益為基礎，而且圖求其利益，藉由引用而在此包含其內容全體。
半導體晶片係具有金屬凸塊，有覆晶連接在配線基板上的端子的情形。此外，半導體晶片係被薄膜化，有經過半導體元件的製造工程時發生翹曲的情形。若將如上所示有翹曲的半導體晶片覆晶連接在配線基板上，有半導體晶片形成缺口、或發生金屬凸塊與配線基板的端子的連接不良的情形。此外，若在半導體晶片與配線基板間填充底部填充樹脂，若半導體晶片變薄，底部填充樹脂攀上半導體晶片上，若在其上部另外積層半導體晶片，有半導體晶片破裂的可能性。
本實施形態之半導體裝置係具備電性連接於設在絕緣基板的配線的焊墊。配線基板係具有設在焊墊間的第1絕緣材。第1半導體晶片係在與該配線基板相對向的第1面具有連接於配線基板的焊墊的金屬凸塊。第1接著層係設在第1絕緣材與第1半導體晶片之間，且將配線基板與第1半導體晶片接著。絕緣樹脂係在配線基板與第1半導體晶片之間，以覆蓋第1接著層及金屬凸塊的周圍與前述配線基板上的構造體的方式而設。
以下參照圖示，說明實施形態。本發明並非為限定於實施形態。其中，在本說明書與各圖中，對關於已出之圖與之前已述者相同的要素係標註相同符號，並適當省略詳細說明。
(第1實施形態) 圖1A係顯示第1實施形態之半導體裝置的構成例的剖面圖。本實施形態之半導體裝置1係例如NAND型快閃記憶體。半導體裝置1係具備有：配線基板10、第1接著層20、控制器晶片30、第2接著層(DAF(Die Attach Film，黏晶薄膜))40、間隔件50、NAND型記憶體晶片(以下為記憶體晶片)60、接合引線80、及封裝樹脂90。封裝樹脂90係所謂壓模樹脂。其中，本實施形態並非限定於NAND型快閃記憶體，可適用在作覆晶連接的半導體裝置。
配線基板10係具備：絕緣基板11、配線12、接觸插塞13、金屬墊14、焊球15、及作為第1絕緣材的阻焊劑16。在絕緣基板11係使用例如玻璃環氧樹脂、陶瓷等絕緣材料。配線12係設在絕緣基板11的表面、背面或內部，將金屬墊14與焊球15作電性連接。接觸插塞13係設成貫穿絕緣基板11內，將配線12間作電性連接。金屬墊14係在配線基板10的表面，與控制器晶片30的金屬凸塊31相連接。焊球15係在配線基板10的背面，連接於配線12。在配線12、接觸插塞13及金屬墊14係使用例如Al、Cu、Au、Ni、Pd、Ag等導電性材料的單體膜、複合膜、合金膜。在焊球15係使用例如Sn、Ag、Cu、Au、Bi、Zn、In、Sb、Ni等單體膜、複合膜、合金膜等導電性材料。作為第1絕緣材的阻焊劑16係設在配線基板10的表面及背面，設在鄰接的金屬墊14間或鄰接的焊球15間，將該等作電性絕緣。此外，作為第1絕緣材的阻焊劑16係被覆配線12的表面來保護配線12。
作為第1半導體晶片的控制器晶片30係具有：與配線基板10相對向的第1面F1、及位於第1面F1的相反側的第2面F2。在第1面F1係設有金屬凸塊31。金屬凸塊31係被連接(熔接)在配線基板10的金屬墊14。亦即，控制器晶片30係被覆晶連接在配線基板10上。在金屬凸塊31係使用例如焊材等導電性金屬。
控制器晶片30係被薄化，在第1面F1或第2面F2上具有半導體元件。控制器晶片30係有在形成半導體元件時翹曲的情形。控制器晶片30的翹曲係可形成為例如山型、碗型或鞍型。在圖1A中，並未圖示控制器晶片30的翹曲。
在控制器晶片30的第1面F1係設有柱狀的第1接著層20。第1接著層20亦可設有複數個。第1接著層20亦可為圓柱狀、角柱狀，或者亦可與第1面F1呈平行切斷時的剖面為不定形。第1接著層20係若控制器晶片30積層在配線基板10上時，設在配線基板10與控制器晶片30的第1面F1之間，且將配線基板10與控制器晶片30接著。
在本實施形態中，並未設有填埋配線基板10與控制器晶片30的第1面F1之間的NCP(Non Conductive Paste，非導電膏)層或NCF(Non Conductive Film，非導電膜)層。但是，第1接著層20將配線基板10與控制器晶片30接著，來取代NCP層或NCF層。藉此，第1接著層20支持金屬墊14與金屬凸塊31的連接，抑制金屬墊14與金屬凸塊31之間的破斷。此外，在第1接著層20接著控制器晶片30與配線基板10，因此減輕控制器晶片30的翹曲。
作為支持構件的間隔件50係具有：與配線基板10相對向的第3面、及位於第3面的相反側的第4面。間隔件50係設在控制器晶片30的周圍，藉由在第3面作為第2接著層的DAF40而被接著在配線基板10上。間隔件50係設至與控制器晶片30的第2面F2的高度大致相等的高度，且支持記憶體晶片60。間隔件50係如圖1B所示，具有例如四角形的框形狀或四角形且包圍控制器晶片30的形狀，在配線基板10的表面上，以包圍控制器晶片30的四方的方式而設。在間隔件50係使用例如矽、玻璃、絕緣基板、金屬板等材料。亦可在間隔件50上形成有聚醯亞胺樹脂、聚醯胺樹脂、環氧樹脂、丙烯酸樹脂、酚醛樹脂、矽氧樹脂、PBO(PolyBenzOxazole，聚苯并㗁唑)樹脂等有機膜，俾以提升密接性。
記憶體晶片60係設在控制器晶片30的上方，藉由第2接著層(DAF)40而被接著在控制器晶片30及間隔件50的第4面上。記憶體晶片60係具有例如3次元配置有複數記憶體單元的立體型記憶體單元陣列。第2接著層(DAF)40係設在控制器晶片30的第2面F2及間隔件50上，將記憶體晶片60接著在控制器晶片30及間隔件50上。
複數第2接著層(DAF)40及複數記憶體晶片60亦可交替積層在控制器晶片30及間隔件50上。如上所示，即使將複數記憶體晶片60積層在控制器晶片30的上方，亦減輕控制器晶片30的翹曲，因此複數記憶體晶片60不易受到控制器晶片30的翹曲的影響。亦即，複數記憶體晶片60不易形成缺口，且不易由第2接著層(DAF)40剝下。
接合引線80係將記憶體晶片60的金屬墊70與配線基板10的金屬墊14的任一者之間作電性連接。作為絕緣樹脂的封裝樹脂90係被覆控制器晶片30、記憶體晶片60、接合引線80等配線基板10上的構造全體來進行保護。此外，封裝樹脂90係被填充在配線基板10與控制器晶片30的第1面F1之間，設成被覆第1接著層20及金屬凸塊31的周圍。
在此，詳細說明第1接著層20。
圖2(A)及圖2(B)係顯示第1接著層20及其周邊的構成例的剖面圖。第1接著層20係設在控制器晶片30的第1面F1與配線基板10之作為第1絕緣材的阻焊劑16之間，將控制器晶片30與配線基板10接著。第1接著層20的熱膨脹係數係大於配線基板(例如玻璃環氧樹脂)10、控制器晶片(例如矽)30及封裝樹脂90的各個的熱膨脹係數。此外，控制器晶片(例如矽)30的熱膨脹係數由於小於配線基板(例如玻璃環氧樹脂)10的熱膨脹係數，因此當將控制器晶片30構裝在配線基板10時，配線基板10係依溫度而比控制器晶片30更大幅伸縮。例如矽單結晶的熱膨脹係數係約3.5ppm／℃，玻璃環氧樹脂的熱膨脹係數係約17ppm／℃。因此，若第1接著層20的熱膨脹係數小於配線基板10及控制器晶片30的熱膨脹係數，當將控制器晶片30構裝在配線基板10時，第1接著層20係無法追隨配線基板10與控制器晶片30的伸縮差，有被剝下之虞。因此，第1接著層20的熱膨脹係數係以位於20ppm／℃～100ppm／℃的範圍為佳。此外，較佳為第1接著層20的熱膨脹係數係30ppm／℃～60ppm／℃的範圍。若第1接著層20的熱膨脹係數小於20ppm／℃，接近配線基板10的熱膨脹係數，第1接著層20並無法追隨配線基板10與控制器晶片30的伸縮差，有被剝下之虞。相反地，若第1接著層20的熱膨脹係數大於100ppm／℃，第1接著層20過於伸長，有控制器晶片30由配線基板10剝下之虞。在該等情形下，金屬凸塊31破斷、或由金屬墊14剝下而成為連接不良的原因。因此，第1接著層20的熱膨脹係數係以大於配線基板(例如玻璃環氧樹脂)10及控制器晶片(例如矽)30的各個的熱膨脹係數為佳。此外，第1接著層20的熱膨脹係數係以大於封裝樹脂90的熱膨脹係數為佳，可抑制翹曲。
此外，第1接著層20的彈性模數係比配線基板(例如玻璃環氧樹脂)10之作為第1絕緣材的阻焊劑16及金屬凸塊(例如焊材)31的各個的彈性模數為較低。此外，若第1接著層20的彈性模數比作為第1絕緣材的阻焊劑16及金屬凸塊31的彈性模數為較高(較硬)，無法使控制器晶片30對配線基板10的翹曲緩和，有第1接著層20剝下之虞。因此，第1接著層20的彈性模數較佳為位於1MPa～3GPa的範圍。此外，較佳為第1接著層20的彈性模數係10MPa～1GPa的範圍。若第1接著層20的彈性模數低於1MPa，第1接著層20係過軟，難以將控制器晶片30固定在配線基板10。若第1接著層20的彈性模數超過3GPa，第1接著層20會過硬，因控制器晶片30翹曲，有由控制器晶片30或配線基板10剝離之虞。在該等情形下，金屬凸塊31破斷、或由金屬墊14剝下而造成連接不良的原因。因此，第1接著層20的彈性模數係以低於作為第1絕緣材的阻焊劑16及金屬凸塊(例如焊材)31的各個的彈性模數為佳。此外，第1接著層20的彈性模數係以低於封裝樹脂90的彈性模數為佳，可抑制翹曲。
藉此，即使控制器晶片30具有翹曲，第1接著層20將控制器晶片30接著在配線基板10，抑制控制器晶片30由配線基板10剝下。此外，第1接著層20係可將控制器晶片30的翹曲矯正一定程度。因此，在控制器晶片30與配線基板10之間，金屬凸塊31與金屬墊14可相連接，而且金屬凸塊31不易破斷。結果，可抑制金屬凸塊31與金屬墊14之間的連接不良。此外，由於控制器晶片30的翹曲被減輕，因此可抑制積層在控制器晶片30上的記憶體晶片60形成缺口的情形。
如上所示藉由本實施形態，第1接著層20設在配線基板10與控制器晶片30之間，一邊矯正控制器晶片30的翹曲，一邊補強金屬凸塊31與金屬墊14之間的連接。藉此，即使在控制器晶片30有翹曲的情形下，控制器晶片30的第2面F2亦接近平坦。因此，即使將複數記憶體晶片60積層在控制器晶片30的上方，亦可抑制記憶體晶片60的缺口或接著不良。此外，可抑制配線基板10與控制器晶片30之間的金屬凸塊31與金屬墊14之間的連接的破斷。
其中，在圖1A中係設有在同一半導體封裝體內經覆晶連接的控制器晶片30及經打線接合連接的記憶體晶片60之雙方。亦即，在圖1A中係成為混成式的多晶片封裝體。但是，本實施形態係複數記憶體晶片60亦可與控制器晶片30同樣地作覆晶連接。此時，控制器晶片30及複數記憶體晶片60亦可透過貫穿電極(TSV(Through Silicon Via，矽穿孔))而作電性連接。其中，在圖2中係在控制器晶片30上無絕緣樹脂90，惟若在控制器晶片的上部未裝載其他晶片時等，在控制器晶片30上亦可存在絕緣樹脂90。
接著，說明本實施形態之半導體裝置1之製造方法。
圖3(A)～圖7(C)係顯示第1實施形態之控制器晶片30之製造方法之一例的剖面圖。首先，如圖3(A)所示，在半導體基板W上形成半導體元件2及金屬墊4。半導體基板W係例如矽、GaAs、SiC等半導體晶圓。半導體元件2若為例如CMOS(Complementary Metal Oxide Semiconductor，互補式金屬氧化物半導體)電路等即可。在金屬墊4若使用例如Al、Cu、Au、Ni、Pd、Ag等單體膜、複合膜、合金膜即可。
接著，以被覆半導體元件2的方式形成保護絕緣膜3。使用微影技術及蝕刻技術，將保護絕緣膜3加工，且使金屬墊4的一部分露出。在保護絕緣膜3係使用例如矽氧化膜、氮化矽膜、聚醯亞胺樹脂、酚醛樹脂、PBO(PolyBenzOxazole，聚苯并㗁唑)樹脂等絕緣材料。此外，亦可為該等絕緣材料的複合膜。
接著，如圖3(B)所示，使用濺鍍法、蒸鍍法、CVD(Chemical Vapor Deposition，化學氣相沈積)法、無電解鍍敷法等，在保護絕緣膜3及金屬墊4上形成障壁金屬BM。在障壁金屬BM係使用例如鈦、銅等導電性金屬。若使用Ti、Cr、Cu、Ni、Au、Pd、W等單體膜、氮化膜、複合膜、合金膜即可。例如，以濺鍍法依序形成Ti及Cu。Ti的膜厚係例如約0.1μm，Cu的膜厚係約0.3μm。
接著，如圖4(A)所示，使用微影技術，在障壁金屬BM上形成阻劑PR。阻劑PR係以將金屬墊4的區域形成開口的方式予以圖案化。阻劑PR的厚度係例如約40μm。開口的大小係例如約20μm。
接著，如圖4(B)所示，在金屬墊4上的障壁金屬BM上進行金屬鍍敷。例如，在障壁金屬BM上形成金屬31a、31b、31c。在金屬31a係使用例如銅。在金屬31b係使用例如鎳。在金屬31c係使用例如焊材(SnAg)。金屬31a～31c係作為金屬凸塊31來發揮功能。在焊材若使用例如Sn、Ag、Cu、Au、Bi、Zn、In、Sb、Ni等單體膜、複合膜、合金膜即可。金屬31c亦可使用印刷法、焊球裝載法來形成。金屬31a係例如約20μm的厚度的銅。金屬31b係例如約3μm的厚度的鎳。金屬31c係例如約12μm的厚度的SnAg。
接著，將阻劑PR去除後，如圖5(A)所示，使用金屬凸塊31作為遮罩而將障壁金屬BM蝕刻。藉此，障壁金屬BM係僅殘置於金屬凸塊31之下。例如，若將銅蝕刻，若使用檸檬酸與過氧化氫的混合液即可。若將鈦蝕刻，若使用氫氟酸或過氧化氫水等即可。
接著，如圖5(B)所示，藉由熱處理，將金屬凸塊31的金屬31c(例如焊材)進行回焊(熔融)，而使金屬凸塊31的前端變圓。回焊處理亦可塗布助焊劑而在N2 氣體環境中進行回焊，亦可在甲酸氣體、H2 氣體、H2 及N2 的混合氣體等還原氣體環境中，一邊將焊材的氧化膜還原一邊進行回焊。亦可以Ar電漿等將焊材的氧化膜去除來進行回焊處理。例如，塗布水溶性助焊劑後，在260℃的N2 氣體環境中執行30秒鐘回焊。
接著，如圖6(A)所示，將感光性的第1接著層20的材料，塗布在第1面F1的金屬凸塊31及保護絕緣膜3上。在第1接著層20的材料係使用苯酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、環氧系、PBO系、矽氧系、苯並環丁烯系等感光性樹脂、該等混合材料、複合材料。例如，第1接著層20的材料係以比金屬凸塊31為更薄的膜厚(例如約20μm)予以塗布。第1接著層20係感光性材料，因此如圖6(B)所示，可使用微影技術而將第1接著層20圖案化。藉此，第1接著層20以柱狀選擇性形成在保護絕緣膜3上的預定部位。其中，感光性的第1接著層20係顯示塗布在控制器晶片30(半導體晶片)上之例，但是亦可形成在配線基板10上，亦可形成在控制器晶片30與配線基板10之雙方。
圖7(A)係顯示形成半導體元件後的半導體晶圓W。接著將半導體晶圓的背面研磨、弄薄。在複數控制器晶片30間係有切割線DL，如後所述，藉由切斷該切割線DL，控制器晶片30被個片化。
接著，如圖7(B)所示，在舖設在晶圓環130內的可撓性的樹脂膠帶131黏貼半導體晶圓W。接著，使用雷射振盪器150，由半導體晶圓W的表面對切割線DL所對應的部分照射雷射光。藉此，在半導體晶圓W的切割線DL形成溝。
接著，如圖7(C)所示，使用切割刀160，切斷半導體晶圓W的切割線DL。藉此，在樹脂膠帶131上，半導體晶圓W被個片化為控制器晶片30。亦可無照射雷射光，而僅以刀片切割進行個片化。或者，亦可僅以雷射光進行個片化。
接著，將紫外線照射在樹脂膠帶131，減低控制器晶片30與樹脂膠帶131之間的接著劑的黏著性，可將控制器晶片30由樹脂膠帶131卸下。此外，進行外觀檢查等。如上所示，控制器晶片30即完成。其中，記憶體晶片60若將例如記憶體單元陣列形成在半導體基板W上作為半導體元件2即可。記憶體晶片60的其他製造工程係與控制器晶片30的製造工程相同，故省略說明。
接著，說明將控制器晶片30構裝在配線基板10上的方法。在配線基板10係形成有作為第1絕緣材的阻焊劑16。作為第1絕緣材的阻焊劑16係使用環氧系、苯酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、PBO系、矽氧系等樹脂、該等混合材料、複合材料。此外，亦可在作為第1絕緣材的阻焊劑16之中包含有二氧化矽等填料。
圖8(A)～圖9(B)係顯示將控制器晶片30構裝在配線基板10上的組裝工程之一例的剖面圖。首先，配線基板10亦可予以烘烤，俾以將水分去除。或者，亦可進行電漿處理，俾使配線基板10與第1接著層20的密接性提升。
接著，如圖8(A)所示，在配線基板10上塗布具有羥基的材料Loh。以具有羥基的材料Loh而言，若為純水、醇類等即可。以醇類而言，列舉選自甲醇、乙醇、異丙醇、聚乙烯醇、乙二醇、丙二醇、二甘醇、甘油、三甘醇、三縮四乙二醇、卡必醇、溶纖素醇等的至少1種。此外，亦可為烷醚系的材料。列舉例如二乙二醇單丁醚、三乙二醇二甲醚等。亦可使用烷烴、胺化合物等。列舉例如甲醯胺、二甲基甲醯胺等。該等可為單獨，亦可混合複數。此外，亦可在該等材料添加有機酸。以有機酸而言，列舉：甲酸、乙酸、安息香酸、辛二酸、壬二酸、癸二酸、十二烷二酸、十四烷二酸、十六烷二酸、十七烷二酸、十八烷二酸、環己烷二羧酸、環庚烷二羧酸、環辛烷二羧酸、降莰烷二羧酸、金剛烷二羧酸等等。該材料Loh係以分配法、印刷法、噴射法等方法予以塗布。具有羥基的材料Loh係被供給為用以將位於金屬凸塊31或金屬墊14的表面的氧化膜(SnO、SnO2 )等還原而去除。
接著，壓接裝置100吸著控制器晶片30，如圖8(B)所示，以金屬凸塊31相對應的方式對位在配線基板10的金屬墊14上。此時，具有羥基的材料Loh係可接觸或不接觸第1接著層20。
接著，壓接裝置100係一邊使金屬凸塊31接觸金屬墊14一邊對控制器晶片30施加壓力，而且供予超音波。藉此，如圖9(A)所示，將金屬凸塊31電性連接在金屬墊14，將控制器晶片30覆晶連接在配線基板10上。此時，壓接裝置100亦可將金屬凸塊31及金屬墊14加熱。例如，壓接裝置100係將金屬凸塊31及金屬墊14以約200℃加熱，使金屬凸塊31(例如焊材)軟化，併用超音波而彼此相連接。如上所示，可藉由併用超音波，將金屬凸塊31快速連接在金屬墊14。結果，流通量(throughput)被縮短。例如施加輸出5w，作為超音波。振幅係設為1μm左右。超音波的頻率係使用30～200kHz。此外，雖顯示併用超音波之例，惟亦可僅以加熱來連接。若為僅進行加熱，係以壓接裝置100，將金屬凸塊31及金屬墊14，以焊材的熔融溫度以上例如約250℃加熱來連接。
藉由壓接裝置100，另外對控制器晶片30施加壓力，使第1接著層20接觸配線基板10之作為第1絕緣材的阻焊劑16上來進行接著。壓接裝置100亦可為覆晶接合器。
接著，將配線基板10，例如以150℃加熱1小時，如圖9(B)所示，使材料Loh蒸發。
之後，將間隔件50設在配線基板10上，且將複數記憶體晶片60及複數第2接著層(DAF)40交替積層在控制器晶片30上。例如，使第2接著層40附著在控制器晶片30的第2面F2上，且將記憶體晶片60載置於第2接著層40上來進行接著。或者，使第2接著層40附著在記憶體晶片60的背面，且接著在控制器晶片30的第2面F2上。藉此，可將記憶體晶片60黏貼在控制器晶片30上。此外，將複數第2接著層40及複數記憶體晶片60交替積層在控制器晶片30上。之後，視需要，執行打線接合，且以封裝樹脂90被覆包含配線基板10上的控制器晶片30及第1接著層20的構造，藉此，圖1A所示之半導體裝置1即完成。封裝樹脂90係以壓模樹脂為特徵。壓模樹脂係使用環氧系、苯酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、PBO系、矽氧系等樹脂、該等混合材料、複合材料。以環氧樹脂之例而言，並未特別限定，列舉例如：雙酚A型、雙酚F型、雙酚AD型、雙酚S型等雙酚型環氧樹脂、苯酚酚醛清漆型、甲酚酚醛清漆型等酚醛清漆型環氧樹脂、間苯二酚型環氧樹脂、三苯酚甲烷三縮水甘油基醚等芳香族環氧樹脂、萘型環氧樹脂、芴型環氧樹脂、雙環戊二烯型環氧樹脂、聚醚改質環氧樹脂、二苯甲酮型環氧樹脂、苯胺型環氧樹脂、NBR改質環氧樹脂、CTBN改質環氧樹脂、及該等的氫化物等。其中，由與Si的密接性佳的觀點來看，亦以萘型環氧樹脂、雙環戊二烯型環氧樹脂為佳。此外，由於容易獲得速硬化性，二苯甲酮型環氧樹脂亦佳。該等環氧樹脂係可單獨使用，亦可併用2種以上。此外，亦可在封裝樹脂90之中含有二氧化矽等填料。填料係以小於控制器晶片30與配線基板10的間隙為佳。封裝樹脂90係使用模塑裝置等而形成。作為封裝樹脂90的壓模樹脂的熱膨脹係數係以小於第1接著層20的熱膨脹係數為佳。藉此，可減低翹曲、或因應力減少而可抑制可靠性試驗時的金屬凸塊的連接部的破斷。此外，作為封裝樹脂90的壓模樹脂的彈性模數係以比第1接著層20的彈性模數為高為佳。藉此，可減低翹曲、或因應力減少而可抑制可靠性試驗時的金屬凸塊的連接部的破斷。
若控制器晶片30或配線基板10變薄，控制器晶片30或配線基板10係變得容易翹曲，容易引起金屬凸塊31與金屬墊14的連接不良。此外，難以在金屬凸塊31之上積層記憶體晶片60，所積層的記憶體晶片60容易形成缺口。
相對於此，藉由本實施形態，第1接著層20將控制器晶片30與配線基板10之間接著，一邊矯正控制器晶片30的翹曲，一邊補強金屬凸塊31與金屬墊14之間的連接。藉此，控制器晶片30的第2面F2係接近平坦，可抑制被積層在控制器晶片30的上方的記憶體晶片60的缺口或接著不良。此外，可抑制金屬凸塊31與金屬墊14之間的連接的破斷。例如，若如本實施形態所示設有第1接著層20，即使控制器晶片30的厚度為10μm～100μm的範圍，且配線基板10的厚度為20μm～500μm的範圍，金屬凸塊31與金屬墊14之間的連接亦不會破斷而予以維持。若控制器晶片30的厚度小於100μm，雖然晶片變得容易翹曲，但是藉由本實施形態，即使有控制器晶片30的翹曲，亦可安定地連接。若配線基板10厚度小於500μm，雖然配線基板10變得容易翹曲，但是藉由本實施形態，即使有配線基板10的翹曲，亦可安定地連接。
此外，在控制器晶片30與配線基板10之間塗布底部填充材的比較例中，係底部填充材攀上控制器晶片30上，而且若積層記憶體晶片60，有記憶體晶片60破裂的情形。但是，在本實施形態中，由於並不存在攀上控制器晶片30上的樹脂，因此記憶體晶片60不易破裂。
對本實施形態之半導體裝置1執行溫度循環試驗。溫度循環試驗係將-55℃(30min)～25℃(5min)～125℃(30min)作為1週期來執行。以結果而言，本實施形態之半導體裝置1係即使超過3000週期，在金屬凸塊31與金屬墊14之間的連接部位並未發現異常。
在配線基板10上亦可構裝有其他電子零件。
在本實施形態中，並未設有填埋配線基板10與控制器晶片30之間的NCP層或NCF層，與金屬凸塊31與金屬墊14之間的連接部位分離設有第1接著層20。藉此，第1接著層20支持金屬墊14與金屬凸塊31的連接，抑制金屬墊14與金屬凸塊31之間的破斷。此外，由於未使用NCP或NCF，因此NCP或NCF的樹脂或填料未進入至金屬凸塊31與金屬墊14之間，以高可靠性維持金屬凸塊31與金屬墊14之間的連接。此外，在配線基板10與控制器晶片30之間，係在第1接著層20以外的區域埋入有封裝樹脂90。此外，同一封裝樹脂90亦存在於記憶體晶片60的周圍。藉此，在控制器晶片30及記憶體晶片60的周圍與金屬凸塊31的周圍，熱膨脹係數差變小，抑制控制器晶片30及記憶體晶片60的翹曲。
(變形例1) 圖10(A)及圖10(B)係顯示控制器晶片30的第2面F2中的金屬凸塊31及第1接著層20的佈局的平面圖。如圖10(A)所示，第1接著層20亦可在以金屬凸塊31所包圍的區域的內側，一邊由金屬凸塊31分離一邊以矩陣狀作二次元配置。金屬凸塊31與第1接著層20的距離係例如10μm～1mm的範圍。若金屬凸塊31與第1接著層20的距離為未達10μm，在第1接著層20的曝光及顯影時，有第1接著層20歪斜或變形之虞。另一方面，若其超過1mm，控制器晶片30的翹曲未被矯正，有第1接著層20剝下之虞。
此外，第1接著層20的接著面積亦可大於金屬凸塊31與金屬墊14的接觸面積。藉此，可更加加強地補強金屬凸塊31與金屬墊14之間的連接。此外，可矯正控制器晶片30的翹曲。
如圖10(B)所示，第1接著層20亦可大致均一地設在以金屬凸塊31所包圍的區域的內外。如上所示，藉由在金屬凸塊31的周圍設置第1接著層20，可將控制器晶片30全體接著在配線基板10，且可更加矯正控制器晶片30的翹曲。
(變形例2) 將具有羥基的材料Loh供給至配線基板10上之後，若將控制器晶片30與配線基板10積層，有第1接著層20未接著在配線基板10的情形。
為處理此情形，在變形例2中，係在將控制器晶片30與配線基板10相連接後，將具有羥基的材料Loh放入烤箱進行烘烤，藉此使其蒸發。之後，以壓接裝置將控制器晶片30加壓加熱，且藉由第1接著層20來將控制器晶片30與配線基板10接著。變形例2的其他工程若與第1實施形態所對應的工程相同即可。
此外，具有羥基的材料Loh亦可在將控制器晶片30與配線基板10接著後，以液體狀態注入在金屬凸塊31附近。在該情形下，亦在之後，藉由以壓接裝置進行加壓加熱，可一邊藉由材料Loh來去除氧化膜，一邊將金屬凸塊31壓接在金屬墊14。此時，亦可併用超音波。
(變形例3) 如圖6(B)所示，控制器晶片30形成時，第1接著層20的高度亦可低於金屬凸塊31的高度。但是，如圖11所示，第1接著層20的高度亦可與金屬凸塊31的高度相等或比其更高。圖11係顯示藉由變形例3所得之控制器晶片30的構成例的剖面圖。
如變形例3所示，若第1接著層20的高度為金屬凸塊31的高度以上，當將控制器晶片30構裝在配線基板10時，第1接著層20比金屬凸塊31較先接觸配線基板10，充分接著後，金屬凸塊31被連接在金屬墊14。即使如上所示，亦可得本實施形態的效果。 以上係說明特定的實施形態，惟該等實施形態僅提示為例，並非為意圖限定本發明之範圍者。實際上，本說明書中所說明的新穎的方法及系統亦可以各種其他形態予以具體化。此外，本說明書所記載的方法及系統的形態的各種省略、置換、及變更可在未脫離本發明之精神的情形下進行。所附之申請專利範圍及該等的均等物係意圖涵蓋本發明之範圍及精神所包含的形態或修正。
1:半導體裝置 2:半導體元件 3:保護絕緣膜 4:金屬墊 10:配線基板 11:絕緣基板 12:配線 13:接觸插塞 14:金屬墊 15:焊球 16:阻焊劑 20:第1接著層 30:控制器晶片 31:金屬凸塊 31a,31b,31c:金屬 40:第2接著層 50:間隔件 60:NAND型記憶體晶片 80:接合引線 90:封裝樹脂 100:壓接裝置 BM:障壁金屬 DL:切割線 F1:第1面 F2:第2面 Loh:具有羥基的材料 PR:阻劑 W:半導體基板
[圖1A]係顯示第1實施形態之半導體裝置的構成例的剖面圖。 [圖1B]係顯示第1實施形態之半導體裝置的構成例的平面圖。 [圖2]係顯示第1接著層及其周邊的構成例的剖面圖。 [圖3]係顯示第1實施形態之控制器晶片之製造方法之一例的剖面圖。 [圖4]係顯示接續圖3之控制器晶片之製造方法之一例的剖面圖。 [圖5]係顯示接續圖4之控制器晶片之製造方法之一例的剖面圖。 [圖6]係顯示接續圖5之控制器晶片之製造方法之一例的剖面圖。 [圖7]係顯示接續圖6之控制器晶片之製造方法之一例的剖面圖。 [圖8]係顯示將控制器晶片構裝在配線基板上的組裝工程之一例的剖面圖。 [圖9]係顯示接續圖8之控制器晶片之製造方法之一例的剖面圖。 [圖10]係顯示控制器晶片的第2面中的金屬凸塊及第1接著層的佈局的平面圖。 [圖11]係顯示變形例3之控制器晶片的構成例的剖面圖。
10:配線基板
11:絕緣基板
12:配線
14:金屬墊
16:阻焊劑
20:第1接著層
30:控制器晶片
31:金屬凸塊
90:封裝樹脂
F1:第1面
F2:第2面

Claims (20)

  1. 一種半導體裝置，其係具備：配線基板，其係具有：電性連接於設在絕緣基板的配線的焊墊、及設在前述焊墊間的第1絕緣材；第1半導體晶片，其係在與該配線基板相對向的第1面具有連接於前述配線基板的焊墊的金屬凸塊(31)；複數第1接著層，其係設在前述第1絕緣材與前述第1半導體晶片之間，且將前述配線基板與前述第1半導體晶片接著，為柱狀，彼此不作物理性接觸且與前述金屬凸塊不作物理性接觸；及絕緣樹脂(90)，其係在前述配線基板與前述第1半導體晶片之間，覆蓋前述複數第1接著層及前述金屬凸塊(31)的周圍與前述配線基板上的構造體。
  2. 如請求項1之半導體裝置，其中，前述第1接著層的熱膨脹係數係大於前述配線基板及前述第1半導體晶片的熱膨脹係數。
  3. 如請求項1之半導體裝置，其中，前述第1接著層的彈性模數係低於前述第1絕緣材及前述金屬凸塊的彈性模數。
  4. 如請求項2之半導體裝置，其中，前述第1接著層的彈性模數係低於前述第1絕緣材及前述金屬凸塊的彈性模數。
  5. 如請求項1之半導體裝置，其中，前述第1接著層係由前述金屬凸塊分離來作配置。
  6. 如請求項1之半導體裝置，其中，前述第1接著層的接著面積係大於前述金屬凸塊與前述焊墊的接觸面積。
  7. 如請求項1之半導體裝置，其中，另外具備有：第2接著層，其係設在位於前述第1面的相反側的前述第1半導體晶片的第2面；及第2半導體晶片，其係設在前述第2接著層上。
  8. 如請求項7之半導體裝置，其中，前述第1半導體晶片係控制前述第2半導體晶片的控制器晶片，前述第2半導體晶片係記憶體晶片。
  9. 如請求項7之半導體裝置，其中，複數前述第2半導體晶片及複數前述第2接著層交替積層在前述第1半導體晶片上方。
  10. 如請求項7之半導體裝置，其中，具備支持構件(50)，其係設在前述第1半導體晶片的周圍，且具有：與前述配線基板相對向的第3面、及位於第3面的相反側的第4面，前述第2接著層係設在前述第4面。
  11. 一種半導體裝置之製造方法，其係具備：在具有金屬凸塊的第1半導體晶片的第1面或配線基板的表面塗布感光性的第1接著層；將前述第1接著層，以彼此不作物理性接觸且成為複 數柱狀的方式選擇性地殘置於前述第1面或前述表面的預定部位；將前述第1半導體晶片的前述金屬凸塊與前述配線基板的焊墊相連接，而且，以前述第1接著層的一端部與前述配線基板的表面作物理性接觸且另一端部與前述第1半導體晶片的前述第1面作物理性接觸的方式相連接，而且前述第1接著層係形成為與前述金屬凸塊不物理性接觸，形成被覆前述配線基板上的前述第1半導體晶片、前述第1接著層、及前述配線基板上的構造體的絕緣樹脂。
  12. 如請求項11之半導體裝置之製造方法，其中，前述第1接著層的熱膨脹係數係大於前述配線基板及前述第1半導體晶片的熱膨脹係數。
  13. 如請求項11之半導體裝置之製造方法，其中，前述第1接著層的彈性模數係低於前述第1絕緣材及前述金屬凸塊的彈性模數。
  14. 如請求項12之半導體裝置之製造方法，其中，前述第1接著層的彈性模數係低於前述第1絕緣材及前述金屬凸塊的彈性模數。
  15. 如請求項11之半導體裝置之製造方法，其中，在前述配線基板上塗布具有羥基的材料。
  16. 如請求項11之半導體裝置之製造方法，其中，將前述第1半導體晶片的前述金屬凸塊與配線基板的焊墊相連接時，施加超音波。
  17. 如請求項11之半導體裝置之製造方法， 其中，另外具備：在位於前述第1面的相反側的前述第1半導體晶片的第2面形成第2接著層，在前述第2接著層上黏貼第2半導體晶片。
  18. 如請求項17之半導體裝置之製造方法，其中，前述第1半導體晶片係控制前述第2半導體晶片的控制器晶片，前述第2半導體晶片係記憶體晶片。
  19. 如請求項17之半導體裝置之製造方法，其中，另外具備：複數前述第2半導體晶片及複數前述第2接著層交替積層在前述第1半導體晶片上方。
  20. 如請求項17之半導體裝置之製造方法，其中，另外具備：在前述第1半導體晶片的周圍，以第3面與前述配線基板相對向的方式設置支持構件，在位於前述支持構件的第3面的相反側的第4面形成前述第2接著層。
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