TWI772280B - 改良黏著性之方法 - Google Patents

改良黏著性之方法 Download PDF

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TWI772280B
TWI772280B TW105142212A TW105142212A TWI772280B TW I772280 B TWI772280 B TW I772280B TW 105142212 A TW105142212 A TW 105142212A TW 105142212 A TW105142212 A TW 105142212A TW I772280 B TWI772280 B TW I772280B
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semiconductor substrate
dielectric layer
silicon
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凱瑟林 克魯克
史帝芬 R 柏吉斯
安德魯 普萊斯
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英商Ｓｐｔｓ科技公司
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Abstract

依據本發明，提供一種改良一半導體基材與一介電層間的黏著性之方法，包含步驟： 藉由一第一電漿增強化學蒸氣沉積(PECVD)程序使一二氧化矽黏著層沉積於半導體基材上；以及 藉由一第二PECVD程序使介電層沉積於黏著層上； 其中，第一PECVD程序係於一氣體環境中實施，此氣體環境包含四乙氧基矽烷(TEOS)，且缺乏O2 或具有以250sccm或更少之流速引入此程序中之O2 。

Description

改良黏著性之方法
本發明係有關於一種改良一半導體基材與一介電層間的黏著性之方法。此方法亦係有關於包含一半導體基材、一介電層，及一二氧化矽黏著層之一種結構。
有很多具有商業重要性之方法、結構，及裝置，其等係涉及使一介電層沉積於一半導體基材之一表面上。一例子係CI(CMOS影像感測器)產品之製造。於此等製造方法，需藉由電漿增強化學蒸氣沉積(PECVD)沉積一介電 層以供穿孔透出應用中之TSV(直通矽穿孔)隔離及中介層鈍化。低溫高蝕刻速率矽蝕刻方法產生大量不需要之聚合物副產物。此於TSV及穿孔透出應用係特別明顯。聚合物副產物需於任何隔離層被沉積之前被移除。對於此之一理由係聚合物副產物存在危及其後沉積之介電層的黏著。副產物之移除需要多個清理步驟，包括O2 灰化及EKC聚合物剝離。此等方法本身會造成其它殘餘物留在矽表面上。此等殘餘物亦會造成介電 層差的黏著。
典型上，300mm矽基材於使矽薄化及蝕刻之前與玻璃載體基材結合。用於此結合之黏著劑具有不安定直空性質，此需要於CVD沉積之前實行除氣。但是，除氣副產物可能污染矽表面。矽表面受諸如此等方法污染係非所欲的。此污染之一結果係危及其後沉積之介電層的黏著性。因此，可看到確保介電層與半導體結構適當黏著作為商業製程之一部份會係具挑戰性。
會瞭解除了上述特別問題以外，普遍所欲及需要的是改良介電層與諸如矽之半導體基材的黏著性，無論半導體表面受否被污染。本發明於至少一些其等實施例滿足此等問題、期望，及需求。
依據本發明之第一方面，提供一種改良一半導體基材與一介電層間的黏著性之方法，包含下列步驟： 藉由第一電漿增強化學蒸氣沉積(PECVD)程序使一二氧化矽黏著層沉積於半導體基材上；以及 藉由第二PECVD程序使介電層沉積於黏著層上； 其中，第一PECVD程序係於一氣體環境中實施，此氣體環境包含四乙氧基矽烷(TEOS)，且缺乏O2 或具有以250sccm或更少之流速引入此程序中之O2 。
O2 可以100sccm或更少，較佳係10sccm或更少之流速引入此程序中。最佳地，無O2 被引入此程序中。
半導體基材可為矽。
使黏著層沉積於其上之半導體基材可包含另外之非半導體特徵。非半導體特徵可為金屬特徵。例如，半導體基材可為其上具有銅或鎢之一經部份金屬化之矽基材。典型上，非半導體特徵可僅構成可利用表面積之一小比例。一般，非半導體特徵構成半導體基材之可利用表面積的少於10%。
半導體基材可包含其上沉積黏著層之一受污染表面。
半導體基材可包含其上沉積黏著層之一表面，其中，此表面係疏水性。
沉積於黏著層上之介電層可為一含矽材料。介電層可為氮化矽、氧化矽，或碳化矽。若介電層係二氧化矽，此可為使用諸如TEOS或矽烷之一適合先質沉積之二氧化矽。
沉積於黏著層上之介電層可為親水性。
第一PECVD程序可使用一RF信號產生一電漿。RF信號可具有少於400kHz之頻率。典型上，RF信號係具有大於100kHz之頻率。特別有利之結果已使用於此頻率之單一RF信號產生電漿而獲得。
亦可使用雙重RF信號產生電漿，且此等RF信號之一者係具有相對較低頻率，且另一RF信號係具有相對較高頻率。RF功率可施用於一噴淋頭或一噴淋頭及平板總成。因此，第一PECVD程序可另外使用一第二RF信號產生電漿。第二RF信號可具有大於400kHz之頻率。較佳地，第二RF信號係具有13.56MHz之頻率。
第一PECVD程序可於包含TEOS、選擇性之O2 ，及一或多種另外組份之一氣體環境中實施。
第一PECVD程序可於包含H2 之一氣體環境中實施。H2 可以範圍500至1200sccm之流速引入第一PECVD程序中。H2 流速可於範圍800-1100sccm。
第一PECVD程序可藉由以1.3至1.6ccm之範圍的流速引入此程序中之TEOS實施。
二氧化矽黏著層可具有1000nm或更少，較佳係200nm或更少之厚度。更厚之黏著層係於本發明之範圍內。但是，於其中二氧化矽黏著層係比沉積於其上之介電層更差之一介電質的實施例，其可有利地使用一相對較薄之黏著層，諸如，具有200nm或更少之厚度的一黏著層。
黏著層可具有至少0.3%之CHx :SiO比例。CHx :SiO比例可為至少3%。此處所述之CHx :SiO比例係藉由比較與CHx 及SiO吸收相關之以傅利葉轉換紅外線光譜術(FTIR)獲得之波峰面積而計算。X可為1至3。CHx : SiO比例可為於約2900-3000cm-1 之CHx 波峰的積分面積對於約1800cm-1 之SiO波峰的積分面積的比例，其係以百分率表示。
第一PECVD程序可於範圍2.0至4.0托耳之壓力實施。壓力可於範圍2.0至3.5托耳。壓力可於範圍2.0至3.0托耳。
第一PECVD程序可於範圍100至200o C之溫度實施。
依據本發明第二方面，提供一半導體基材、一介電層，及形成於半導體基材與介電層之間的一二氧化矽黏著層，此結構係藉由依據本發明第一方面之方法製造。
依據本發明第三方面，提供一種結構，其包含一半導體基材、一介電層，及形成於半導體基材與介電層之間的一二氧化矽黏著層，其中，黏著層具有至少0.3%之CHx :SiO比例，係藉由比較與CHx 及SiO吸收相關之以FTIR獲得之波峰面積而計算，其中，x係1至3。黏著層可具有至少3%之CHx :SiO比例。
雖然本發明已於上作說明，但其係延伸至如上或於下列說明、圖式或申請專利範圍中所述特徵之任何發明性組合。
圖4係本發明結構40之一示意代表圖，包含一半導體基材42、一黏著層44，及一介電層46。本發明利用黏著層44改良半導體基材42與介電層46之間的黏著性。黏著層44係一二氧化矽層，其係於利用一低氧流或無氧流之一PECVD程序沉積於半導體基材42上。介電層46係藉由PECVD沉積於黏著層44上。本發明之範例及比較例係表示於下。 半導體基材
為複製一受污染之矽表面，低溫(50-200o C)於原位之聚合物條材電漿直接於裸矽表面上進行。典型加工條件係顯示於表1。
Figure 105142212-A0304-0001
 表1.聚合物條材加工(HF=高頻率 RF=13.56MHz，LF=低頻率 RF=380kHz)
受污染之矽表面被認為係代表於裝置晶圓上普遍發生之受污染表面。
多數個PECVD沉積於受污染之矽表面上進行。沉積層之黏著性藉由使用一標準膠帶拖拉測試量化。於此拖拉測試，一 10x10 1mm格柵經由此膜鑽石切割至矽基材內。一膠帶被施用於此膜之表面，且與矽表面呈垂直地拖拉。黏著性通過百分率被引用，其係指格柵中之膜有多少與矽保持黏著。 黏著層
二氧化矽黏著層係於一TEOS PECVD程序黏著，其係於此PECVD程序中使用極少的氧流或未使用氧流。表2顯示此PECVD程序參數之典型範圍及較佳(即使非限制性)值。使用之低RF頻率係380kHz，且使用之高RF頻率係13.56MHz。其它頻率可替代地使用。一般，低RF頻率可被認為係少於400kHz之頻率，且高RF頻率可被認為係400kHz或更多之頻率。
Figure 105142212-A0304-0002
 表2. 黏著層之加工參數
黏著層係對在不同條件下沉積之二氧化矽黏著層實施。結果係顯示於表3。
Figure 105142212-A0304-0003
 表3.二氧化矽黏著層之黏著測試(低壓力=2.5托耳，於4.0托耳之壓力的其它加工)
於表3中所述之於無流氧而沉積的膜進行進一步測試以訮究其等之電特性。圖1顯示高RF頻率、低RF頻率，及低RF頻率與低壓力之實施例的個別I-V曲線10，12，14。表4顯示外洩電流及崩潰電壓。
Figure 105142212-A0304-0004
 表4. 各種膜於崩潰電壓之外漏電流
可看出使用低RF頻率沉積之二氧化矽膜的電流特性係優於使用高RF頻率沉積者。加工壓力降低進一步改良電特性。對於一介電膜，所欲地係於諸如2MV/cm之固定電勢使崩潰電壓達最大且使外漏電流達最小。
膜安定性係藉由沉積後直接測量電性質及於使膜曝露於環境條件五天後測量電性質而研究。圖2顯示相對之I-V曲線。曲線20，22個別相對應於沉積後直接測量及五天後測量之低RF頻率沉積。曲線24，26個別相對應於沉積後直接測量及五天後測量之低RF頻率及低壓力沉積。表5顯示於沉積後直接測量及五天後測量之外漏電流。使用低RF頻率獲得之膜於五天僅顯示邊際增加。使用低RF頻率及低壓力沉積而獲得之膜顯示於外漏電流未增加，此指示最小再吸收。
Figure 105142212-A0304-0005
 表5. 沉積時及五天後於崩潰電壓之外漏電流
FTIR光譜亦於此段時間後獲得。表6顯示相對應於3400cm-1 及950cm-1 –OH吸收之正規化FTIR波峰面積。再次地，使用低RF頻率及低沉積壓力沉積之黏著層顯示比其它膜更低之含水量。關於以較高加工壓力條件獲得之膜，低RF頻率黏著層顯示比高RF頻率黏著層明顯更低之含水量。
Figure 105142212-A0304-0006
 表6. 各種膜由FTIR光譜之正規化–OH波峰面積比例
二氧化矽黏著層之碳含量被測量，且與使用傳統TEOS PECVD程序沉積之二氧化矽層相比。此等結果係顯示於表7。可看出本發明之二氧化矽黏著層具有比傳統獲得之二氧化矽膜更高之CHx 含量。CHx 含量係以CHx :SiO比例表示。此比例係藉由比較相對應於CHx 及SiO吸收之FTIR光譜中的波峰面積而獲得。
圖3顯示本發明之一二氧化矽黏著層及使用一傳統TEOS PECVD程序沉積之一二氧化矽層的FTIR光譜。於約1080cm-1 之大波峰係SiO拉伸吸收。於紡2900-3000cm-1 之波峰係與CHx 吸收相關。以下呈現之CHx :SiO波峰面積比例係藉由計算2900-3000cm-1 波峰之積分面積對1080cm-1 波峰之積分面 積的比例而獲得。
CHx 基使二氧化矽黏著層些微疏水。此係可與矽基材之疏水性污染表面相容。注意使用以矽烷為主之PECVD沉積之二氧化矽層不具有碳鍵結且性質亦係親水性。
Figure 105142212-A0304-0007
 表7. 以TEOS為主之SiO2 沉積的CHx :SiO比例 介電層之沉積
沉積一系列之介電膜，包括藉由以TEOS為主之PECVD及以矽烷為主之PECVD膜沉積之氮化矽及二氧化矽膜。膜係以範圍從500nm至3微米之厚度及從50-400oC 之溫度沉積。膜係直接沉積於受污染之矽表面上或一二氧化矽沉積層上。代表性之沉積條件係顯示於表8。
Figure 105142212-A0304-0008
 表8.用於樣品製備之沉積條件(HF=高頻率 RF=13.56MHz，LF=低頻率 RF=380kHz) 經沉積之介電層的性質
黏著性測試係以直接沉積於受污染之矽表面上的介電膜實施。亦實施實驗使一100nm二氧化矽黏著層沉積於矽表面上，及其後藉由PECVD使介電層沉積於黏著層上。黏著層係使用上述之低RF頻率低壓力PECVD程序沉積。經沉積之介電層的厚度對於以TEOS為主之二氧化矽膜、以矽烷為主之二氧化矽膜，及氮化矽膜個別係3 微米、600nm及500nm。黏著測試之結果顯示於表9。
Figure 105142212-A0304-0009
 表 9. 沉積於受污染之矽表面上且具有及不具有一中間黏著層的介電層之黏著測試
不欲受任何特別理論或推測限制，二氧化矽黏著層被認為作為受污染之矽的疏水性層與些微親水性之介電層間之一結合層。再次地不欲受任何特別理論或推測限制，認為藉由用於本發明之低氧流或無氧流製造二氧化矽黏著層，此程序實質上或甚至完全依靠自TEOS釋出之氧形成二氧化矽層。
本發明可用於藉由以PECVD使廣泛範圍之介電層沉積於黏著層上。此於經沉積之介電層亦係二氧化矽時係特別便利。然後，結合強度係藉由使黏著層之‘籽’沉積無中斷沉積地繼續進行至主要二氧化矽介電層內而最大化。此於膜間造成一連續轉化，促進複合層之優異黏著。
40‧‧‧結構 42‧‧‧半導體基材 44‧‧‧黏著層 46‧‧‧介電層
依據本發明之方法及結構的實施例現將參考所附圖式作說明，其中：- 圖1顯示三黏著層之I-V曲線； 圖2顯示於沉積後直接獲得及於五天後獲得之I-V曲線； 圖3顯示使用一傳統以TEOS為主之PECVD程序及使用不具有O2 存在之一以TEOS為主之PECVD程序獲得之一二氧化矽層的FTIR光譜；以及 圖4係本發明之一結構的一示意代表圖。

Claims (15)

  1. 一種改良一半導體基材與一介電層間的黏著性之方法，包含下列步驟：藉由第一電漿增強化學蒸氣沉積(PECVD)程序使一二氧化矽黏著層沉積於該半導體基材上；以及藉由第二PECVD程序使該介電層沉積於該黏著層上；其中，該第一PECVD程序係於一氣體環境中實施，該氣體環境包含四乙氧基矽烷(TEOS)，且缺乏O2或具有以250sccm或更少之流速引入該程序中之O2，及其中該第一PECVD程序使用具有大於100kHz之一頻率之一射頻(RF)信號來產生一電漿。
  2. 如請求項1之方法，其中，O2係以100sccm或更少之流速引至該程序中。
  3. 如請求項2之方法，其中，O2係以10sccm或更少之流速引至該程序中。
  4. 如請求項1至3中任一項之方法，其中，該半導體基材係矽。
  5. 如請求項1至3中任一項之方法，其中，該介電層係一含矽材料。
  6. 如請求項5之方法，其中，該介電層係氮化矽、氧化矽，或碳化矽。
  7. 如請求項1至3中任一項之方法，其中，該第一RF信號係具有少於400kHz之頻率。
  8. 如請求項1至3中任一項之方法，其中，該 第一PECVD程序係於包含H2之一氣體環境中實施。
  9. 如請求項8之方法，其中，H2係以範圍500至1200sccm之流速引至該第一PECVD程序中。
  10. 如請求項1至3中任一項之方法，其中，該二氧化矽黏著層具有1000nm以下之厚度。
  11. 如請求項1至3中任一項之方法，其中，該黏著層具有至少0.3%之CHx：SiO比例，該比例係藉由比較與CHx及SiO吸收相關之以FTIR獲得之波峰面積來計算，其中x係1至3。
  12. 如請求項1至3中任一項之方法，其中，該第一PECVD程序係於範圍3.0至4.0托耳之壓力下實施。
  13. 如請求項1至3中任一項之方法，其中，該第一PECVD程序係於範圍100至200℃之溫度下實施。
  14. 一種結構，其包含一半導體基材、一介電層，及一二氧化矽黏著層，其係形成於該半導體基材與該介電層之間，其中，該結構係藉由如請求項1至13中任一項之方法製造。
  15. 一種結構，其包含一半導體基材、一介電層，及一二氧化矽黏著層，其係形成於該半導體基材與該介電層之間，其中，該黏著層具有至少0.3%之CHx：SiO比例，該比例係藉由比較與CHx及SiO吸收相關之以FTIR獲得之波峰面積來計算，其中x係1至3，該結構係藉由如請求項1至13中任一項之方法製造。
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Families Citing this family (6)

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GB201806865D0 (en) * 2018-04-26 2018-06-13 Spts Technologies Ltd Method of depositing a SiN film
CN110942974B (zh) * 2018-09-25 2023-06-09 长鑫存储技术有限公司 半导体结构的形成方法及在晶圆上形成氧化硅膜的方法
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CN110567896A (zh) * 2019-09-12 2019-12-13 江苏集萃智能传感技术研究所有限公司 一种基于多波段滤光的便携式分析装置
CN110448263A (zh) * 2019-09-12 2019-11-15 江苏集萃智能传感技术研究所有限公司 一种基于多波段滤光图像传感器的胶囊内窥镜
CN112342531A (zh) * 2020-10-19 2021-02-09 绍兴同芯成集成电路有限公司 一种利用低频射频电浆制备ild绝缘层的晶圆制造工艺

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4872947A (en) * 1986-12-19 1989-10-10 Applied Materials, Inc. CVD of silicon oxide using TEOS decomposition and in-situ planarization process
CN1074006C (zh) * 1995-10-13 2001-10-31 陶氏化学公司 涂覆的塑料基材
TW502377B (en) * 2000-06-22 2002-09-11 Texas Instruments Inc Semiconductor device protective overcoat with enhanced adhesion to polymeric materials and method of fabrication
TWI474400B (zh) * 2010-11-29 2015-02-21 Univ Nat Taiwan Science Tech 疏水性二氧化矽層及有機薄膜電晶體的製造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4892753A (en) * 1986-12-19 1990-01-09 Applied Materials, Inc. Process for PECVD of silicon oxide using TEOS decomposition
JP2590240B2 (ja) * 1988-11-16 1997-03-12 株式会社日立製作所 薄膜形成方法
US5426076A (en) 1991-07-16 1995-06-20 Intel Corporation Dielectric deposition and cleaning process for improved gap filling and device planarization
JPH06326026A (ja) * 1993-04-13 1994-11-25 Applied Materials Inc 半導体装置の薄膜形成方法
DE69333722T2 (de) * 1993-05-31 2005-12-08 Stmicroelectronics S.R.L., Agrate Brianza Verfahren zur Verbesserung der Haftung zwischen Dielektrikschichten, an ihrer Grenzfläche, in der Herstellung von Halbleiterbauelementen
JPH08203891A (ja) * 1995-01-27 1996-08-09 Sharp Corp 半導体装置の製造方法
TW389963B (en) * 1997-04-30 2000-05-11 This Inv Is About The Method O Method of depositing uniform dielectric layers
US6143666A (en) 1998-03-30 2000-11-07 Vanguard International Seminconductor Company Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough
US6197705B1 (en) * 1999-03-18 2001-03-06 Chartered Semiconductor Manufacturing Ltd. Method of silicon oxide and silicon glass films deposition
US7547643B2 (en) * 2004-03-31 2009-06-16 Applied Materials, Inc. Techniques promoting adhesion of porous low K film to underlying barrier layer
JP4489618B2 (ja) * 2005-03-14 2010-06-23 株式会社ルネサステクノロジ 半導体装置の製造方法
US7601648B2 (en) * 2006-07-31 2009-10-13 Applied Materials, Inc. Method for fabricating an integrated gate dielectric layer for field effect transistors
DE102009046259B4 (de) * 2009-10-30 2019-10-10 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Stärkere Haftung eines PECVD-Kohlenstoffs auf dielektrischen Materialien durch Vorsehen einer Haftungsgrenzfläche
GB0922647D0 (en) * 2009-12-24 2010-02-10 Aviza Technologies Ltd Methods of depositing SiO² films
US8541053B2 (en) * 2010-07-08 2013-09-24 Molecular Imprints, Inc. Enhanced densification of silicon oxide layers
CN102169288A (zh) * 2010-12-02 2011-08-31 南京大学扬州光电研究院 一种在蓝宝石基板上进行光刻的方法
CN103377886B (zh) * 2012-04-13 2016-06-29 中芯国际集成电路制造(上海)有限公司 硬掩膜层结构及其制造方法和半导体器件制造方法
GB201207448D0 (en) * 2012-04-26 2012-06-13 Spts Technologies Ltd Method of depositing silicon dioxide films
US20140000686A1 (en) * 2012-06-29 2014-01-02 Applied Materials, Inc. Film stack and process design for back passivated solar cells and laser opening of contact
CN104716055B (zh) 2013-12-11 2017-09-29 中芯国际集成电路制造(上海)有限公司 晶圆级封装方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4872947A (en) * 1986-12-19 1989-10-10 Applied Materials, Inc. CVD of silicon oxide using TEOS decomposition and in-situ planarization process
CN1074006C (zh) * 1995-10-13 2001-10-31 陶氏化学公司 涂覆的塑料基材
TW502377B (en) * 2000-06-22 2002-09-11 Texas Instruments Inc Semiconductor device protective overcoat with enhanced adhesion to polymeric materials and method of fabrication
TWI474400B (zh) * 2010-11-29 2015-02-21 Univ Nat Taiwan Science Tech 疏水性二氧化矽層及有機薄膜電晶體的製造方法

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