CN107039267B - 改善粘附性的方法 - Google Patents

改善粘附性的方法 Download PDF

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CN107039267B
CN107039267B CN201611191831.7A CN201611191831A CN107039267B CN 107039267 B CN107039267 B CN 107039267B CN 201611191831 A CN201611191831 A CN 201611191831A CN 107039267 B CN107039267 B CN 107039267B
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adhesion layer
dielectric layer
silicon
silicon dioxide
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凯瑟琳·克鲁克
斯蒂芬·R·伯吉斯
安德鲁·普赖斯
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Abstract

根据本发明，提供了一种改善半导体衬底与介电层之间的粘附性的方法，包括以下步骤：通过第一等离子体增强化学气相沉积(PECVD)工艺在所述半导体衬底上沉积二氧化硅粘附层；和通过第二PECVD工艺将所述介电层沉积到所述粘附层上；其中，在没有O2或者以250sccm或更低的流速将O2引入所述工艺的情况下，在包含原硅酸四乙酯(TEOS)的气体气氛中进行所述第一PECVD工艺。

Description

改善粘附性的方法
技术领域
本发明涉及一种改善半导体衬底与介电层之间的粘附性的方法。该方法还涉及一种包括半导体衬底、介电层和二氧化硅粘附层的结构。
背景技术
有许多具有商业意义的工艺、结构和器件涉及在半导体衬底的表面上沉积介电层。一个实例是制造CIS(CMOS图像传感器)产品。在这些制造工艺中，对于TSV(穿透硅通孔)绝缘和通孔露出应用中的中介层钝化，需要通过等离子体增强化学气相沉积(PECVD)来沉积介电层。低温、高蚀刻速率的硅蚀刻工艺产生大量不需要的聚合副产物。这在TSV和通孔露出应用中尤其明显。在沉积任何绝缘层之前，需要除去聚合副产物。其中一个原因是聚合副产物的存在损害随后沉积的介电层的粘附性。去除副产物需要多个清洁步骤，包括O2灰化和EKC聚合物剥离。这些工艺本身会导致其它残余物残留在硅表面上。这些残余物还会导致介电层的粘附性变差。
通常，在硅的薄化和蚀刻之前，将300mm的硅衬底粘合到玻璃载体衬底。用于粘合的胶粘剂具有不稳定的真空性能，需要在CVD沉积之前进行除气。然而，排气副产物可能会污染硅表面。这些方法污染硅表面是不期望的。污染的一个后果是随后沉积的介电层的粘附性受损。因此，可以看出，作为商业制造工艺的一部分，确保介电层充分粘附到半导体结构是具有挑战性的。
应当理解，除了上述的具体问题之外，无论半导体表面是否被污染，都存在改善介电层粘附到半导体衬底(诸如硅)的一般需求和需要。本发明至少在其一些实施方式中解决了这些问题、需求和需要。
发明内容
根据本发明的第一方面，提供了一种改善半导体衬底与介电层之间的粘附性的方法，包括以下步骤：
通过第一等离子体增强化学气相沉积(PECVD)工艺在所述半导体衬底上沉积二氧化硅粘附层；和
通过第二PECVD工艺将所述介电层沉积到所述粘附层上；
其中，在没有O2或者以250sccm或更低的流速将O2引入所述工艺的情况下，在包含原硅酸四乙酯(TEOS)的气体气氛中进行所述第一PECVD工艺。
可以以100sccm或更小的流速，优选10sccm或更小的流速将O2引入所述工艺中。最优选地，没有将O2引入所述工艺中。
所述半导体衬底可以是硅。
所述粘附层沉积到其上的半导体衬底可以包括额外的非半导体特征件(feature)。所述非半导体特征件可以是金属特征件。例如，所述半导体衬底可以是具有铜或钨特征件在其上的部分金属化的硅衬底。通常，所述非半导体特征件仅构成小部分可用表面积。通常，所述非半导体特征件构成小于10％的所述半导体衬底的可用表面积。
所述半导体衬底可以包括所述粘附层沉积到其上的污染表面。
所述半导体衬底可以包括所述粘附层沉积到其上的表面，其中，所述表面是疏水的。
沉积到所述粘附层上的介电层可以是含硅材料。所述介电层可以是氮化硅、氧化硅或碳化硅。在所述介电层是氧化硅的情况下，所述介电层可以是使用合适的前体(诸如TEOS或硅烷)沉积的二氧化硅。
沉积到所述粘附层上的介电层可以是亲水的。
第一PECVD工艺可以使用RF信号来产生等离子体。RF信号可以具有小于400kHz的频率。通常，RF信号具有大于100kHz的频率。使用这些频率下的单个RF信号来产生等离子体已经获得了特别有利的结果。
还可以使用双RF信号来产生等离子体，其中，RF信号中的一个具有相对低的频率，而另一个RF信号具有相对高的频率。RF功率能被施加到喷头，或喷头与压板组件。因此，所述第一PECVD工艺可以额外使用第二RF信号来产生等离子体。所述第二RF信号可以具有大于400kHz的频率。优选地，所述第二RF信号具有13.56MHz的频率。
所述第一PECVD工艺可以在包含TEOS、可选的O2和一种或多种其它组分的气体气氛中进行。
所述第一PECVD工艺可以在包含H2的气体气氛中进行。可以以500sccm～1200sccm的流速将H2引入所述第一PECVD工艺中。H2流速可以为800sccm～1100sccm。
所述第一PECVD工艺可以用1.3ccm～1.6ccm的流速将TEOS引入到所述工艺中进行。
所述二氧化硅粘附层可以具有1000nm或更小的厚度，优选200nm或更小的厚度。较厚的粘附层在本发明的范围之内。然而，在二氧化硅粘附层是比沉积到其上的介电层更差的电介质的实施方式中，使用相对薄的粘附层(这种粘附层具有200nm或更小的厚度)可能是有益的。
所述粘附层可以具有至少0.3％的CHx:SiO比。CHx:SiO比可以为至少3％。本文描述的CHx:SiO比通过比较由与CHx吸收和SiO吸收相关的傅立叶变换红外光谱(FTIR)获得的峰面积进行计算。X可以是1～3。所述CHx:SiO比可以是以百分比表示的在约2900～3000cm-1处的CHx峰的积分面积与在约1800cm-1处的SiO峰的积分面积之比。
所述第一PECVD工艺可以在2.0Torr～4.0Torr的压力下进行。所述压力可以为2.0Torr～3.5Torr。所述压力可以为2.0Torr～3.0Torr。
所述第一PECVD工艺可在100℃～200℃的温度下进行。
根据本发明的第二方面，提供了半导体衬底、介电层和在所述半导体衬底与所述介电层之间形成的二氧化硅粘附层，所述结构根据本发明的第一方面的方法进行制造。
根据本发明的第三方面，提供了一种包括半导体衬底、介电层和在所述半导体衬底与所述介电层之间形成的二氧化硅粘附层的结构，其中，所述粘附层具有至少0.3％的CHx:SiO比，所述CHx:SiO比是通过比较与CHx和SiO吸收相关的由FTIR获得的峰面积而算出的，其中x为1～3。所述粘附层可以具有至少3％的CHx:SiO比。
虽然本发明已被描述如上，但是它延伸至在上文中或者下面的说明书、附图或权利要求书中提出的特征的任何发明组合。
附图说明
现将参照附图描述根据本发明的方法和结构的实施方式，其中：
图1示出了三种粘附层的I-V曲线；
图2示出了在沉积后直接获得的和在五天后获得的I-V曲线；
图3示出了使用常规的基于TEOS的PECVD工艺和使用没有O2的基于TEOS的PECVD工艺获得的二氧化硅层的FTIR光谱；和
图4是本发明结构的示意图。
具体实施方式
图4是本发明包括半导体衬底42、粘附层44和介电层46的结构40的示意图。本发明利用粘附层44来改善半导体衬底42与介电层46之间的粘附性。粘附层44是在利用低氧气流或根本没利用氧气流的PECVD工艺中沉积到半导体衬底42上的二氧化硅层。介电层46通过PECVD而被沉积到粘附层44上。本发明的实施例和比较例如下所示。
半导体衬底
为了复制污染的硅表面，直接对裸露的硅表面产生低温(50℃～200℃)原位聚合物剥离等离子体(in-situ polymer strip plasma)。典型的工艺条件如表1所示。
工艺参数 典型值
时间(s) 30
温度(℃) 125
压力(Torr) 3.1
气体流量(sccm) 2300O<sub>2</sub>,1000H<sub>2</sub>
RF功率(W) 945HF,420LF
表1：聚合物剥离工艺(HF＝高频RF＝13.56MHz，LF＝低频RF＝380kHz)。
污染的硅表面被认为代表了在器件晶片上通常出现的污染表面。
在污染的硅表面上进行了许多PECVD沉积。沉积层的粘附性通过使用标准带拉伸试验进行量化。在拉伸试验中，在硅衬底中用金刚石以10×10的1mm栅格划断膜。将胶带涂覆到膜的表面并垂直于硅表面将胶带拉开。引用粘附合格百分比，它是指在栅格中有多少膜保持粘附到硅上。
粘附层
在PECVD工艺中很少使用或没有使用氧气流的TEOS PECVD工艺中，沉积二氧化硅粘附层。表2示出了PECVD工艺参数的典型范围和优选(尽管非限制性)值。所用的低RF频率为380kHz，而所使用的高RF频率为13.56MHz。也可以使用其他频率。通常，低RF频率可被认为是小于400kHz的频率，而高RF频率可被认为是400kHz或更大的频率。
参数 范围 优选
温度(℃) 100～200 125
压力(torr) 2.5～4.0 3
氧(sccm) 0～500 0
氢(sccm) 500～1200 1000
TEOS(ccm) 1.35～1.55 1.45
功率(高频RF)(W) 0～600 0
功率(低频RF)(W) 350～600 420
表2：粘附层的工艺参数。
对不同条件下沉积的二氧化硅粘附层进行粘附性试验。结果示于表3。
沉积条件 粘附性试验结果
低频RF，500sccm氧气流 90％合格
高频RF，无氧气流 100％合格
低频RF，无氧气流 100％合格
低频RF，无氧气流，低压力 100％合格
表3：二氧化硅粘附层的粘附试验(低压＝2.5Torr，而其它方法是在4.0Torr的压力下)。
表3中描述的没用氧气流沉积的膜进行了进一步试验以研究它们的电学特性。图1示出了高RF频率实施方式的I-V曲线10、低RF频率实施方式的I-V曲线12以及低RF频率且低压力实施方式的I-V曲线14。表4示出了泄漏电流和击穿电压。
Figure BDA0001187212170000061
表4：各种膜的击穿电压下的泄露电流。
可以看出，使用低RF频率沉积的二氧化硅膜的电流特性优于使用高RF频率沉积的二氧化硅膜的电流特性。工艺压力的降低进一步改善了电学特性。对于介电膜，期望以固定电势(诸如2MV/cm)使击穿电压最大化并使泄漏电流最小化。
膜稳定性通过在沉积之后直接测量电性能并且在使膜在环境条件下暴露五天之后测量电性能来进行研究。图2示出了相关的I-V曲线。曲线20和曲线22分别对应于在沉积之后直接测量的低RF频率沉积以及在五天之后测量的低RF频率沉积。曲线24和曲线26分别对应于在沉积之后直接测量的低RF频率且低压力沉积以及在五天之后测量的低RF频率且低压力沉积。表5示出了在沉积之后直接测量的泄漏电流以及在五天后测量的泄漏电流。使用低RF频率获得的膜在五天内仅示出微小增加。使用低RF频率且低压沉积获得的膜示出了泄漏电流没有增大，这表明了最小的再吸收。
Figure BDA0001187212170000071
表5：在沉积时的以及在五天之后的击穿电压下的泄露电流。
在此期间也获得了FTIR光谱。表6示出了与3400cm-1和950cm-1-OH吸收对应的归一化的FTIR峰面积。而且，使用低RF频率且低沉积压力沉积的粘附层示出了与其它膜相比更低的水分含量。对于用较高工艺压力条件获得的膜，低RF频率粘附层示出了与高RF频率粘附层相比显著更低的水分含量。
Figure BDA0001187212170000072
表6：各种膜的FTIR光谱的归一化的-OH峰面积比。
对二氧化硅粘附层的碳含量进行测量并且与使用常规TEOS PECVD工艺沉积的二氧化硅层进行比较。结果示于表7。可以看出，本发明的二氧化硅粘附层具有与常规获得的二氧化硅膜相比更高的CHx含量。CHx含量以CHx:SiO比表示。该比例通过比较FTIR光谱中的与CHx和SiO吸收对应的峰面积而获得。
图3示出了本发明的二氧化硅粘附层和使用常规TEOS PECVD工艺沉积的二氧化硅层的FTIR光谱。在约1080cm-1处的大峰是SiO伸缩吸收。在约2900cm-1～3000cm-1处的峰与CHx吸收有关。通过计算2900cm-1～3000cm-1峰的积分面积与1080cm-1峰的积分面积之比而获得下面示出的CHx:SiO峰面积比。
CHx基团使二氧化硅粘附层略微疏水，从而与硅衬底的疏水性污染表面相容。请注意，使用基于硅烷的PECVD沉积的二氧化硅层没有碳键并且本质上也是亲水性的。
Figure BDA0001187212170000081
表7：基于TEOS的SiO2沉积的CHx:SiO比。
介电层的沉积
沉积一系列介电膜，包括通过基于TEOS的PECVD和基于硅烷的PECVD沉积的氮化硅和二氧化硅膜。膜的沉积厚度范围为500nm～3μm，而温度为50℃～400℃。将膜直接沉积到污染的硅表面上，或沉积到二氧化硅粘附层上。典型性沉积条件示于表8。
Figure BDA0001187212170000082
表8：用于样品制备的沉积条件(HF＝高频RF＝13.56MHz，LF＝低频RF＝380kHz)。
沉积介电层的性质
对使用直接沉积到污染的硅表面上的介电膜进行粘附测试。实验还通过将100nm二氧化硅粘附层沉积到硅表面上并随后通过PECVD将介电层沉积到粘附层上来进行。使用上述低RF频率、低压PECVD工艺沉积粘附层。对于基于TEOS的二氧化硅、基于硅烷的二氧化硅和氮化硅膜，沉积的介电层的厚度分别为3μm、600nm和500nm。粘附性试验的结果示于表9。
电介质 粘附性试验结果
比较例1 二氧化硅(基于TEOS的PECVD) 0％
比较例2 二氧化硅(基于硅烷的PECVD) 10％合格
比较例3 氮化硅 5％合格
实施例1 二氧化硅(基于TEOS的PECVD)/二氧化硅粘附层 100％合格
实施例2 二氧化硅(基于硅烷的PECVD)/二氧化硅粘附层 100％合格
实施例3 氮化硅/二氧化硅粘附层 100％合格
表9：对沉积到具有和没有中间粘附层的污染的硅表面上的介电层的粘附性试验。
不希望受到任何特定理论或推测的限制，二氧化硅粘附层被视为污染的硅的疏水性表面与轻微亲水性介电层之间的粘合层。同样不希望受到任何特定理论或推测的限制，据信，通过使用本发明中使用的低氧气流或无氧气流来产生二氧化硅粘附层，该工艺基本上或甚至完全依赖于由TEOS释放的氧形成二氧化硅层。
本发明能被用于通过PECVD在粘附层上沉积宽范围的介电层。在沉积的介电层也是二氧化硅时特别方便。然后，通过使粘附层的“种子”沉积物进入主二氧化硅介电层而不中断沉积，使粘合的强度最大化。这在膜之间产生连续过渡，从而有益于复合层的优异粘附性。

Claims (19)

1.一种提高半导体衬底与介电层之间的粘附性的方法，包括以下步骤：
通过第一等离子体增强化学气相沉积(PECVD)工艺在所述半导体衬底上沉积二氧化硅粘附层；和
通过第二PECVD工艺将所述介电层沉积到所述粘附层上；
其中，在没有O2或者以250sccm或更低的流速将O2引入所述工艺的情况下，在包含原硅酸四乙酯(TEOS)的气体气氛中进行所述第一PECVD工艺。
2.根据权利要求1所述的方法，其中，以100sccm或更低的流速将O2引入所述工艺中。
3.根据权利要求2所述的方法，其中，以10sccm或更低的流速将O2引入所述工艺中。
4.根据权利要求1至3中任一项所述的方法，其中，所述半导体衬底是硅。
5.根据权利要求1至3中任一项所述的方法，其中，所述介电层是含硅材料。
6.根据权利要求5所述的方法，其中，所述介电层是氮化硅、氧化硅或碳化硅。
7.根据权利要求1至3中任一项所述的方法，其中，所述第一PECVD工艺首先使用第一RF信号来产生等离子体，其中，所述第一RF信号具有小于400kHz的频率。
8.根据权利要求1至3中任一项所述的方法，其中，在包含H2的气体气氛中进行所述第一PECVD工艺。
9.根据权利要求8所述的方法，其中，以500sccm～1200sccm的流速将H2引入所述第一PECVD工艺中。
10.根据权利要求1至3中任一项所述的方法，其中，所述二氧化硅粘附层具有1000nm或更小的厚度。
11.根据权利要求10所述的方法，其中，所述二氧化硅粘附层具有200nm或更小的厚度。
12.根据权利要求1至3中任一项所述的方法，其中，所述粘附层具有至少0.3％的CHx:SiO比，所述CHx:SiO比是通过比较与CHx和SiO吸收相关的由FTIR获得的峰面积而算出的，其中x为1～3。
13.根据权利要求12所述的方法，其中，所述粘附层具有至少3％的CHx:SiO比。
14.根据权利要求1至3中任一项所述的方法，其中，在3.0Torr～4.0Torr的压力下进行所述第一PECVD工艺。
15.根据权利要求14所述的方法，其中，在2.5Torr～3.5Torr的压力下进行所述第一PECVD工艺。
16.根据权利要求1至3中任一项所述的方法，其中，在100℃～200℃的温度下进行所述第一PECVD工艺。
17.一种包括半导体衬底、介电层和在所述半导体衬底与所述介电层之间形成的二氧化硅粘附层的结构，所述结构通过权利要求1至16中任一项所述的方法进行制造。
18.一种包括半导体衬底、介电层和在所述半导体衬底与所述介电层之间形成的二氧化硅粘附层的结构，其中，所述粘附层具有至少0.3％的CHx:SiO比，所述CHx:SiO比是通过比较与CHx和SiO吸收相关的由FTIR获得的峰面积而算出的，其中x为1～3。
19.根据权利要求18所述的结构，其中，所述粘附层具有至少3％的CHx:SiO比。
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