TWI733941B - 導線架及其製造方法暨製造電子構件裝置之方法 - Google Patents
導線架及其製造方法暨製造電子構件裝置之方法 Download PDFInfo
- Publication number
- TWI733941B TWI733941B TW106139334A TW106139334A TWI733941B TW I733941 B TWI733941 B TW I733941B TW 106139334 A TW106139334 A TW 106139334A TW 106139334 A TW106139334 A TW 106139334A TW I733941 B TWI733941 B TW I733941B
- Authority
- TW
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- Prior art keywords
- electrode
- lead frame
- plating layer
- metal plating
- coupling portion
- Prior art date
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/411—Chip-supporting parts, e.g. die pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/04—Manufacture or treatment of leadframes
- H10W70/041—Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/04—Manufacture or treatment of leadframes
- H10W70/042—Etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/421—Shapes or dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/456—Materials
- H10W70/457—Materials of metallic layers on leadframes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/464—Additional interconnections in combination with leadframes
- H10W70/465—Bumps or wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/464—Additional interconnections in combination with leadframes
- H10W70/467—Multilayered additional interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/811—Multiple chips on leadframes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016-222098 | 2016-11-15 | ||
| JP2016222098A JP6761738B2 (ja) | 2016-11-15 | 2016-11-15 | リードフレーム及びその製造方法、電子部品装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201830626A TW201830626A (zh) | 2018-08-16 |
| TWI733941B true TWI733941B (zh) | 2021-07-21 |
Family
ID=62106703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW106139334A TWI733941B (zh) | 2016-11-15 | 2017-11-14 | 導線架及其製造方法暨製造電子構件裝置之方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20180138107A1 (https=) |
| JP (1) | JP6761738B2 (https=) |
| CN (1) | CN108074903B (https=) |
| TW (1) | TWI733941B (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20200035614A1 (en) * | 2018-07-30 | 2020-01-30 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
| JP7319808B2 (ja) | 2019-03-29 | 2023-08-02 | ローム株式会社 | 半導体装置および半導体パッケージ |
| US11562948B2 (en) | 2019-11-04 | 2023-01-24 | Mediatek Inc. | Semiconductor package having step cut sawn into molding compound along perimeter of the semiconductor package |
| JP2022041152A (ja) * | 2020-08-31 | 2022-03-11 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置の製造方法、半導体装置、および電子機器 |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060097366A1 (en) * | 2003-07-19 | 2006-05-11 | Ns Electronics Bangkok (1993) Ltd. | Semiconductor package including leadframe roughened with chemical etchant to prevent separation between leadframe and molding compound |
| WO2006115267A1 (ja) * | 2005-04-26 | 2006-11-02 | Dai Nippon Printing Co., Ltd. | 回路部材、回路部材の製造方法、半導体装置、及び回路部材表面の積層構造 |
| WO2007061112A1 (ja) * | 2005-11-28 | 2007-05-31 | Dai Nippon Printing Co., Ltd. | 回路部材、回路部材の製造方法、及び、回路部材を含む半導体装置 |
| US20090230525A1 (en) * | 2008-03-14 | 2009-09-17 | Pao-Huei Chang Chien | Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof |
| US20100258920A1 (en) * | 2009-04-10 | 2010-10-14 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
| JP2011029335A (ja) * | 2009-07-23 | 2011-02-10 | Mitsui High Tec Inc | リードフレーム及びリードフレームの製造方法とこれを用いた半導体装置の製造方法 |
| US20120074548A1 (en) * | 2010-09-24 | 2012-03-29 | Zigmund Ramirez Camacho | Integrated circuit packaging system with interlock and method of manufacture thereof |
| WO2016031482A1 (ja) * | 2014-08-26 | 2016-03-03 | Shマテリアル株式会社 | リードフレーム及びその製造方法 |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6342730B1 (en) * | 2000-01-28 | 2002-01-29 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
| KR100373460B1 (ko) * | 2001-02-08 | 2003-02-25 | 신무환 | 고효율 SiC 소자제작을 위한 건식식각 공정 |
| TW574753B (en) * | 2001-04-13 | 2004-02-01 | Sony Corp | Manufacturing method of thin film apparatus and semiconductor device |
| US7060535B1 (en) * | 2003-10-29 | 2006-06-13 | Ns Electronics Bangkok (1993) Ltd. | Flat no-lead semiconductor die package including stud terminals |
| US7807498B2 (en) * | 2007-07-31 | 2010-10-05 | Seiko Epson Corporation | Substrate, substrate fabrication, semiconductor device, and semiconductor device fabrication |
| WO2009084597A1 (ja) * | 2007-12-28 | 2009-07-09 | Mitsui High-Tec, Inc. | 半導体装置の製造方法及び半導体装置、半導体装置の中間製品の製造方法及び半導体装置の中間製品、並びにリードフレーム |
| WO2010036051A2 (en) * | 2008-09-25 | 2010-04-01 | Lg Innotek Co., Ltd. | Structure and manufacture method for multi-row lead frame and semiconductor package |
| WO2010052973A1 (ja) * | 2008-11-05 | 2010-05-14 | 株式会社三井ハイテック | 半導体装置及びその製造方法 |
| JP5195647B2 (ja) * | 2009-06-01 | 2013-05-08 | セイコーエプソン株式会社 | リードフレームの製造方法及び半導体装置の製造方法 |
| JP2011096882A (ja) * | 2009-10-30 | 2011-05-12 | Seiko Epson Corp | 半導体装置の製造方法及び半導体装置のアレイ |
| US8643166B2 (en) * | 2011-12-15 | 2014-02-04 | Stats Chippac Ltd. | Integrated circuit packaging system with leads and method of manufacturing thereof |
| JP2013168474A (ja) * | 2012-02-15 | 2013-08-29 | Toshiba Corp | 多結晶シリコンのエッチング方法、半導体装置の製造方法およびプログラム |
| US9312194B2 (en) * | 2012-03-20 | 2016-04-12 | Stats Chippac Ltd. | Integrated circuit packaging system with terminals and method of manufacture thereof |
| JP6555927B2 (ja) * | 2015-05-18 | 2019-08-07 | 大口マテリアル株式会社 | 半導体素子搭載用リードフレーム及び半導体装置の製造方法 |
| JP6770853B2 (ja) * | 2016-08-31 | 2020-10-21 | 新光電気工業株式会社 | リードフレーム及び電子部品装置とそれらの製造方法 |
-
2016
- 2016-11-15 JP JP2016222098A patent/JP6761738B2/ja active Active
-
2017
- 2017-11-13 US US15/810,261 patent/US20180138107A1/en not_active Abandoned
- 2017-11-14 TW TW106139334A patent/TWI733941B/zh active
- 2017-11-15 CN CN201711130270.4A patent/CN108074903B/zh active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060097366A1 (en) * | 2003-07-19 | 2006-05-11 | Ns Electronics Bangkok (1993) Ltd. | Semiconductor package including leadframe roughened with chemical etchant to prevent separation between leadframe and molding compound |
| WO2006115267A1 (ja) * | 2005-04-26 | 2006-11-02 | Dai Nippon Printing Co., Ltd. | 回路部材、回路部材の製造方法、半導体装置、及び回路部材表面の積層構造 |
| WO2007061112A1 (ja) * | 2005-11-28 | 2007-05-31 | Dai Nippon Printing Co., Ltd. | 回路部材、回路部材の製造方法、及び、回路部材を含む半導体装置 |
| US20090230525A1 (en) * | 2008-03-14 | 2009-09-17 | Pao-Huei Chang Chien | Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof |
| US20100258920A1 (en) * | 2009-04-10 | 2010-10-14 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
| TW201037776A (en) * | 2009-04-10 | 2010-10-16 | Advanced Semiconductor Eng | Advanced quad flat non-leaded package structure and manufacturing method thereof |
| JP2011029335A (ja) * | 2009-07-23 | 2011-02-10 | Mitsui High Tec Inc | リードフレーム及びリードフレームの製造方法とこれを用いた半導体装置の製造方法 |
| US20120074548A1 (en) * | 2010-09-24 | 2012-03-29 | Zigmund Ramirez Camacho | Integrated circuit packaging system with interlock and method of manufacture thereof |
| WO2016031482A1 (ja) * | 2014-08-26 | 2016-03-03 | Shマテリアル株式会社 | リードフレーム及びその製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201830626A (zh) | 2018-08-16 |
| JP6761738B2 (ja) | 2020-09-30 |
| US20180138107A1 (en) | 2018-05-17 |
| CN108074903B (zh) | 2022-07-01 |
| JP2018081979A (ja) | 2018-05-24 |
| CN108074903A (zh) | 2018-05-25 |
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