TWI695421B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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Publication number
TWI695421B
TWI695421B TW104143856A TW104143856A TWI695421B TW I695421 B TWI695421 B TW I695421B TW 104143856 A TW104143856 A TW 104143856A TW 104143856 A TW104143856 A TW 104143856A TW I695421 B TWI695421 B TW I695421B
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TW
Taiwan
Prior art keywords
adhesive sheet
semiconductor
semiconductor wafer
adhesive
sheet
Prior art date
Application number
TW104143856A
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English (en)
Chinese (zh)
Other versions
TW201635361A (zh
Inventor
岡本直也
佐藤明徳
藤本泰史
毛受利彰
山田忠知
河崎仁彦
Original Assignee
日商琳得科股份有限公司
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Application filed by 日商琳得科股份有限公司 filed Critical 日商琳得科股份有限公司
Publication of TW201635361A publication Critical patent/TW201635361A/zh
Application granted granted Critical
Publication of TWI695421B publication Critical patent/TWI695421B/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates

Landscapes

  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
TW104143856A 2014-12-26 2015-12-25 半導體裝置之製造方法 TWI695421B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-266140 2014-12-26
JP2014266140A JP6482866B2 (ja) 2014-12-26 2014-12-26 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW201635361A TW201635361A (zh) 2016-10-01
TWI695421B true TWI695421B (zh) 2020-06-01

Family

ID=56359712

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104143856A TWI695421B (zh) 2014-12-26 2015-12-25 半導體裝置之製造方法

Country Status (2)

Country Link
JP (1) JP6482866B2 (enExample)
TW (1) TWI695421B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6960459B2 (ja) * 2017-08-04 2021-11-05 リンテック株式会社 半導体装置の製造方法
JP7093630B2 (ja) * 2017-12-27 2022-06-30 リンテック株式会社 離間装置および離間方法
JP7267990B2 (ja) * 2018-03-07 2023-05-02 リンテック株式会社 エキスパンド方法、半導体装置の製造方法、及び粘着シート
JP7250468B6 (ja) * 2018-10-12 2023-04-25 三井化学株式会社 電子装置の製造方法および粘着性フィルム
JP7334063B2 (ja) * 2019-05-24 2023-08-28 株式会社ディスコ モールドチップの製造方法
JP2021034398A (ja) * 2019-08-14 2021-03-01 株式会社ジャパンディスプレイ 素子移載装置、素子移載方法
KR102351045B1 (ko) * 2019-12-19 2022-01-14 한국기계연구원 마이크로 소자의 간격 조절 전사방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005243910A (ja) * 2004-02-26 2005-09-08 Lintec Corp 半導体チップの製造方法
JP2010199565A (ja) * 2009-01-27 2010-09-09 Citizen Electronics Co Ltd 発光ダイオードの製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006203079A (ja) * 2005-01-21 2006-08-03 Sharp Corp 半導体装置および半導体装置の製造方法
WO2014002535A1 (ja) * 2012-06-29 2014-01-03 シャープ株式会社 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005243910A (ja) * 2004-02-26 2005-09-08 Lintec Corp 半導体チップの製造方法
JP2010199565A (ja) * 2009-01-27 2010-09-09 Citizen Electronics Co Ltd 発光ダイオードの製造方法

Also Published As

Publication number Publication date
JP2016127116A (ja) 2016-07-11
JP6482866B2 (ja) 2019-03-13
TW201635361A (zh) 2016-10-01

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