TWI695421B - Manufacturing method of semiconductor device - Google Patents

Abstract

The present invention is a method for manufacturing a semiconductor device, wherein the first surface (W1) of a semiconductor wafer is provided with a process of forming a trench (W5) having a shallower cutting depth than the thickness of the semiconductor wafer (W), and The first surface (W1) of the groove (W5) is formed, the first adhesive sheet (10) is pasted, and the second surface (W6) of the semiconductor wafer (W) is ground to thin the semiconductor wafer ( The thickness of W), the process of dividing into a plurality of semiconductor wafers (CP), and the third side (W3) that emerges from the grinding of the second side (W6), the process of attaching the second adhesive sheet, and the peeling of the first adhesive The process of the sheet (10), and a method of manufacturing a semiconductor device that stretches the second adhesive sheet and expands the interval between a plurality of semiconductor wafers (CP).

Description

Manufacturing method of semiconductor device

The present invention relates to a method of manufacturing a semiconductor device.

In recent years, progress has been made in miniaturization, lightening, and high performance of electronic devices. The semiconductor devices mounted on electronic devices are also required to be smaller, thinner, and denser. A method of thinning a semiconductor wafer used in a semiconductor device has been developed.

For example, Document 1 (Japanese Patent Laid-Open No. 5-335411) describes the process of forming a bottomed groove by dividing a predetermined boundary line according to the grains on the surface side of a silicon substrate, and grinding the back side of the substrate to this The bottom of the trench is opened and the process of producing granules until the granules are formed. According to Document 1, it is described that the thickness of the silicon substrate after the back grinding is thin, which can prevent the substrate from being broken. The manufacturing method described in Document 1 may be called "first cutting method" or "DBG (Dicing Before Grinding) treatment".

Semiconductor chips are packaged in packages close to this size. Such a package is also called a semiconductor chip scale package (Chip Scale Package; CSP). As one of the processes for manufacturing CSP, it can be Cite semiconductor wafer level packaging (Wafer Level Package; WLP). In WLP, before dicing the package by dicing, external electrodes and the like are formed on the wafer circuit forming surface, and finally the package containing the wafer is diced for dicing. As the WLP, a fan-in type and a fan-out type can be mentioned. In the fan-out type WLP (hereinafter, abbreviated as FO-WLP), the semiconductor wafer is covered with a sealing member in a larger range than the semiconductor wafer size to form a semiconductor wafer enclosure, which will be The wiring layer or external electrode is formed not only on the circuit surface of the semiconductor wafer but also on the surface area of the closing member.

For example, Document 2 (International Publication No. 2010/058646) describes a plurality of semiconductor wafers that are sliced from a semiconductor wafer, the circuit forming surface remains, and a mold member is used to surround the periphery to form an expansion A semiconductor wafer is a method of manufacturing a semiconductor package formed by extending a redistribution pattern outside the semiconductor wafer. In the manufacturing method described in Document 2, the semiconductor wafer mounting tape for expansion is reapplied before the plural semiconductor wafers that are divided into pieces are molded with a mold member, and the semiconductor wafer mounting tape is extended and expanded The distance between multiple semiconductor wafers. In addition, the document 2 series also describes an embodiment in which DBG processing is applied.

In the manufacturing method described in Document 2, the method of singulating semiconductor wafers by dicing is used, and there is a possibility that the arrangement state of a plurality of silicon semiconductor wafers may be disordered. In addition, in the manufacturing method of Document 2, when the DBG treatment is applied, a tape material having both surface protection characteristics during back grinding and expandability during expansion is necessary. But for text Offer 2, for tape materials with such characteristics, there is no specific disclosure. Moreover, in general, the tape for protecting the circuit surface of the semiconductor wafer during back grinding is of the same size as the outer shape of the semiconductor wafer, and it is difficult to stretch the tape. Therefore, in the method using the DBG process described in Document 2, it is also difficult to increase the interval between the plural semiconductor wafers.

Summary of invention

An object of the present invention is to provide a method of manufacturing a semiconductor device that prevents the disorder of the arrangement state in the process of dividing a plurality of semiconductor wafers and can enlarge the interval between the plurality of semiconductor wafers.

According to one aspect of the present invention, there is provided: a process provided on the first surface of the semiconductor wafer to form a groove having a cutting depth shallower than the thickness of the semiconductor wafer, and the first on which the groove is formed Surface, the process of attaching the first adhesive sheet, and grinding and attaching the second surface opposite to the first surface of the first adhesive sheet, thinning the thickness of the semiconductor wafer, and converting the semiconductor wafer The process of dividing into a plurality of semiconductor wafers, and the third side that emerges from the grinding of the second side, the process of attaching the second adhesive sheet, and the process of peeling the first adhesive sheet, and the stretching of the second adhesive sheet and A method of manufacturing a semiconductor device that expands the distance between the plural semiconductor wafers.

According to one aspect of the present invention, the semiconductor wafer is divided into a plurality of semiconductor wafers by a so-called first dicing method. Chaos in the arrangement of semiconductor wafers. Moreover, according to one aspect of the present invention, a plurality of semiconductor wafers that have been sliced by the first dicing method are attached to a second adhesive sheet, and the second adhesive sheet is stretched to expand the plurality of semiconductor wafers to each other The spacer.

In the first aspect of the present invention, before forming the groove on the first surface, the method further includes attaching a third adhesive sheet to the first surface, and cutting the third adhesive sheet to form the groove on the first surface On one side, the first adhesive sheet is preferably attached to the third adhesive sheet that is cut.

According to such a form, the groove is formed in a state where the first surface is protected by the third adhesive sheet, thereby preventing contamination or breakage of the first surface through the cutting chips.

In one aspect of the present invention, it is preferable that a plurality of circuits are formed on the first surface, and it is preferable that the groove is formed by dividing the plurality of circuits.

According to such a form, the semiconductor wafer can be divided into plural semiconductor wafer units.

In one aspect of the present invention, the tensile elastic modulus of the second adhesive sheet is preferably smaller than that of the first adhesive sheet.

According to this form, in the expansion process of stretching the second adhesive sheet, it becomes easy to expand the interval between the plural semiconductor wafers.

In one aspect of the present invention, after expanding the interval between the plurality of semiconductor wafers, it is preferable to further include an engineering that retains the first surface and covers the plurality of semiconductor wafers with a sealing member.

According to this aspect, after the arrangement of the plurality of semiconductor wafers is not disturbed and the interval between the plurality of semiconductor wafers is enlarged, the plurality of semiconductor wafers can be covered by the sealing member. In addition, according to this form, it is possible to singulate the semiconductor wafers without using one from each of the first adhesive sheets, arrange them in other adhesive sheets or supports through picking and placing, and cover them with a sealing member. Therefore, according to this aspect, the manufacturing process of WLP can be simplified.

1‧‧‧Semiconductor packaging

3‧‧‧Closed

5A‧‧‧External electrode gasket

7‧‧‧External terminal electrode

10‧‧‧The first adhesive sheet

11‧‧‧ First substrate film

12‧‧‧The first adhesive layer

20‧‧‧Second adhesive sheet

21‧‧‧Second substrate film

22‧‧‧Second adhesive layer

30‧‧‧Protection sheet

31‧‧‧The third substrate film

32‧‧‧The third adhesive layer

40‧‧‧Surface protection sheet

41‧‧‧Fourth base film

42‧‧‧The fourth adhesive layer

50‧‧‧Grinding machine

60‧‧‧Closed component

61‧‧‧First insulation layer

62‧‧‧Second insulation layer

W‧‧‧Semiconductor wafer

CP‧‧‧Semiconductor chip

W1‧‧‧circuit side

W2‧‧‧circuit

(UV)‧‧‧Ultraviolet

(EB)‧‧‧Electronic wire

FIG. 1 (FIG. 1A, FIG. 1B, FIG. 1C, and FIG. 1D) is a cross-sectional view illustrating the manufacturing method of the first embodiment.

FIG. 2 (FIG. 2A, FIG. 2B, and FIG. 2C) is a cross-sectional view following the FIG. 1 to explain the manufacturing method of the first embodiment.

FIG. 3 (FIG. 3A and FIG. 3B) is a cross-sectional view illustrating the manufacturing method of the first embodiment following FIG. 2. FIG.

FIG. 4 (FIG. 4A, FIG. 4B, and FIG. 4C) is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 3.

FIG. 5 (FIG. 5A, FIG. 5B, and FIG. 5C) is a cross-sectional view following the FIG. 4 to explain the manufacturing method of the first embodiment.

FIG. 6 (FIG. 6A, FIG. 6B, and FIG. 6C) is a cross-sectional view illustrating the manufacturing method of the second embodiment.

[First embodiment]

Hereinafter, a method of manufacturing the semiconductor device according to this embodiment will be described.

1A, it is shown to be attached to the semiconductor wafer W as the protective sheet 30 of the third adhesive sheet. The semiconductor wafer W has a circuit surface W1 as a first surface. A circuit W2 is formed on the circuit surface W1. The protective sheet 30 is attached to the circuit surface W1 of the semiconductor wafer W. The protective sheet 30 protects the circuit surface W1 and the circuit W2.

Semiconductor wafer W series, for example, can also be a silicon semiconductor wafer, but also can be gallium. Arsenic and other compound semiconductor wafers. As a method of forming the circuit W2 on the circuit surface W1, a commonly used method can be mentioned, and for example, an etching method, a peeling method, etc. can be mentioned.

The protective sheet 30 has a third base film 31 and a third adhesive layer 32. The third adhesive layer 32 is laminated on the third base film 31.

The material of the third base film 31 is not particularly limited. Examples of the material of the third base film 31 include polyvinyl chloride resin, polyester resin (polyethylene glycol terephthalate, etc.), acrylic resin, polycarbonate resin, polyethylene resin, and poly Acrylic resin, acrylonitrile. Butadiene. Styrene resin, polyimide resin, polyurethane resin, and polystyrene resin.

The adhesive contained in the third adhesive layer 32 is not particularly limited, and various types of adhesives can be applied to the third adhesive layer 32. Examples of the adhesives contained in the third adhesive layer 32 include rubber-based adhesives, acrylic-based adhesives, polysiloxane-based adhesives, polyester-based adhesives, and urethane-based adhesives. However, the type of adhesive is considered for use Or choose the type of quilt attached.

In the case where the energy ray polymerizable compound is added to the third adhesive layer 32, the energy ray polymerizable compound is hardened by irradiating the energy ray to the third adhesive layer 32 from the third base film 31 side. When the energy ray polymerizable compound is hardened, the cohesive force of the third adhesive layer 32 increases, and the adhesive force between the third adhesive layer 32 and the semiconductor wafer W decreases or disappears. Examples of the energy ray system include ultraviolet rays (UV) and electron beams (EB), and ultraviolet rays are preferred.

[Ditch formation project]

FIG. 1B is a diagram illustrating a process of forming a trench of a specific depth from the circuit surface W1 side of the semiconductor wafer W (sometimes referred to as a trench forming process).

In the trench forming process, the semiconductor wafer is cut using a dicing blade of a dicing device or the like from the protective sheet 30 side. At this time, the protective sheet 30 is completely cut, and cutting is performed from the circuit surface W1 of the semiconductor wafer W to a depth shallower than the thickness of the semiconductor wafer W, thereby forming the groove W5. The groove W5 is formed so as to separate the plurality of circuits W2 formed on the circuit surface W1 of the semiconductor wafer W. The depth of the groove W5 is not particularly limited as long as it is slightly thicker than the intended semiconductor wafer thickness. When the trench W5 is formed, cutting chips from the semiconductor wafer W are generated. In the present embodiment, the circuit surface W1 is protected by the protective sheet 30 and the groove W5 is formed, thereby preventing contamination or damage of the circuit surface W1 or the circuit W2 through the cutting chips.

[Grinding Engineering]

1C, a diagram illustrating a process of grinding the back surface W6 that is the second surface of the semiconductor wafer W after forming the trench W5 (sometimes referred to as a grinding process) is illustrated.

In this embodiment, before grinding, the first adhesive sheet 10 is attached to the protective sheet 30 side. After the first adhesive sheet 10 is attached, the semiconductor wafer W is ground from the back W6 side using a grinder 50. Through grinding, the thickness of the semiconductor wafer W becomes thinner, and finally, the semiconductor wafer W is divided into a plurality of semiconductor chips CP. Until the bottom of the trench W5 is removed, grinding is performed from the back surface W6 side, and the individualized semiconductor wafer W is each circuit W2. After that, if necessary, back surface grinding is performed to obtain a semiconductor wafer CP with a specific thickness. In this embodiment, grinding is performed until the back surface W3 as the third surface is exposed.

As shown in FIG. 1D, the divided plural semiconductor wafers CP are held in the state of the protective sheet 30 and the first adhesive sheet 10.

The first adhesive sheet 10 has a first base film 11 and a first adhesive layer 12. The first adhesive layer 12 is laminated on the first base film 11.

The material of the first base film 11 is not particularly limited. As the material of the first base film 11, for example, the same materials as those exemplified for the third base film 31 can be exemplified.

The adhesive contained in the first adhesive layer 12 is not particularly limited, and various types of adhesives can be applied to the first adhesive layer 12. As The adhesive contained in the first adhesive layer 12 is, for example, the same adhesive as described for the third adhesive layer 32. However, the type of adhesive is selected in consideration of the use or the type of attached body. For the first adhesive layer 12, an energy ray polymerizable compound is also added.

The first adhesive sheet 10 is formed in the same shape as the semiconductor wafer W, and may be cut in advance. In addition, a first adhesive sheet 10 that is larger than the semiconductor wafer W is prepared and attached to the semiconductor wafer W , The semiconductor wafer W may be cut into the same shape.

In the present embodiment, the first adhesive layer 12 is a subsequent process, and the cut protective sheet 30 may be peeled together. It is better to include an adhesive with strong adhesion. The first base film 11 is not stretched during peeling, and preferably has polyethylene glycol terephthalate, specifically, having high rigidity.

[Attachment Project (Second Adhesive Sheet)]

FIG. 2A is a diagram illustrating a process of attaching a plurality of semiconductor wafers CP to a second adhesive sheet 20 after a grinding process (sometimes referred to as a sticking process).

The second adhesive sheet 20 is attached to the back surface W3 of the semiconductor wafer CP. The second adhesive sheet 20 has a second base film 21 and a second adhesive layer 22.

The material of the second base film 21 is not particularly limited. The material of the second base film 21 is, for example, thinner than that of the third base film. The material exemplified in the film 31 is the same material.

The second adhesive layer 22 is laminated on the second base film 21. The adhesive contained in the second adhesive layer 22 is not particularly limited, and various types of adhesives can be applied to the second adhesive layer 22. Examples of the adhesive contained in the second adhesive layer 22 include the same adhesives as those described for the third adhesive layer 32. However, the type of adhesive is selected in consideration of the use or the type of attached body. For the second adhesive layer 22, an energy ray polymerizable compound may also be added.

The tensile elastic modulus of the second adhesive sheet 20 is preferably smaller than that of the first adhesive sheet 10. The tensile elastic modulus of the second adhesive sheet 20 is preferably 10 MPa or more and 2000 MPa or less. It is also preferable that the breaking elongation of the second adhesive sheet 20 is 50% or more. However, the tensile modulus and the elongation at break in this specification are measured using a tensile test device based on JIS K7161 and JIS K7127.

In this embodiment, the adhesive force for the semiconductor wafer W of the second adhesive layer 22 is better than the adhesive force for the semiconductor wafer W of the third adhesive layer 32. If the adhesive force of the second adhesive layer 22 is large, it becomes easy to peel off the first adhesive sheet 10 and the protective sheet 30.

The second adhesive sheet 20 may be attached to a plurality of semiconductor chips CP and the first ring frame. When the first ring-shaped frame is used, the first ring-shaped frame is placed on the second adhesive layer 22 of the second adhesive sheet 20, and this is gently pressed to fix it. After that, in the ring shape of the first ring frame The second adhesive layer 22 exposed on the inner side is pressed against the back surface W3 of the semiconductor wafer CP to fix a plurality of semiconductor wafers CP on the second adhesive sheet 20.

[Peeling Process (First Adhesive Sheet)]

FIG. 2B is a diagram illustrating a process of peeling the first adhesive sheet 10 and the protective sheet 30 after attaching the second adhesive sheet 20 (sometimes referred to as a peeling process).

In this embodiment, as described above, the first adhesive sheet 10 is attached to the protective sheet 30. When the first adhesive sheet 10 is peeled off, the cut protective sheet 30 is also peeled off together. When the protective sheet 30 is peeled off, the circuit surface W1 of the plurality of semiconductor wafers CP is exposed. In this embodiment, as shown in FIG. 2B, the distance between the semiconductor wafers CP divided by the dicing method is referred to as D1. The distance D1 is, for example, preferably 15 μm or more and 110 μm or less.

[Expansion Project]

FIG. 2C is a diagram illustrating a process of stretching and holding the second adhesive sheet 20 of a plurality of semiconductor wafers CP (sometimes referred to as an expansion process).

In the expansion project, the interval between the plural semiconductor wafers CP is further expanded. In the expansion process, the method of stretching the second adhesive sheet 20 is not particularly limited. As a method of stretching the second adhesive sheet 20, for example, a method of pressing a ring-shaped or circular dilator against the second adhesive sheet 20 to stretch the second adhesive sheet 20, or using a holding member, etc. The method of grasping the outer periphery of the second adhesive sheet 20 and extending it.

In this embodiment, as shown in FIG. 2C, the distance between the semiconductor wafers CP after the expansion process is D2. The distance D2 is larger than the distance D1. The distance D2 is, for example, preferably 200 μm or more and 5000 μm or less.

[Closed project]

FIG. 3 is a diagram illustrating a process of closing a plurality of semiconductor wafers CP using a closing member 60 (sometimes referred to as a closing process).

FIG. 3A shows an engineering drawing of attaching the surface protection sheet 40 as the fourth adhesive sheet to a plurality of semiconductor wafers CP after the expansion process.

After the second adhesive sheet 20 is stretched to increase the distance between the plurality of semiconductor wafers CP to a distance D2, the surface protection sheet 40 is attached to the circuit surface W1 of the semiconductor wafer CP. The surface protection sheet 40 has a fourth base film 41 and a fourth adhesive layer 42. The surface protection sheet 40 is preferably such that the fourth adhesive layer 42 covers the circuit surface W1 and is attached.

The material of the surface protection sheet 40 is not particularly limited. As the material of the fourth base film 41, for example, the same materials as those exemplified for the third base film 31 can be mentioned.

The fourth adhesive layer 42 is laminated on the fourth base film 41. The adhesive contained in the fourth adhesive layer 42 is not particularly limited, and various types of adhesives can be applied to the fourth adhesive layer 42. As contained in section The adhesive of the four-adhesive layer 42 is, for example, the same as the adhesive described for the third adhesive layer 32. However, the type of adhesive is selected in consideration of the use or the type of attached body. For the fourth adhesive layer 42, energy-ray polymerizable compounds may also be added.

The adhesion force for the semiconductor wafer W of the fourth adhesive layer 42 is better than the adhesion force for the semiconductor wafer W of the second adhesive layer 22. If the adhesive force of the fourth adhesive layer 42 is large, after transferring a plurality of semiconductor wafers CP on the surface protection sheet 40, it becomes easy to peel off the second adhesive sheet 20.

The surface protection sheet 40 preferably has heat resistance. The sealing member described later is the case of a thermosetting resin. For example, the curing temperature is about 120°C to 180°C, and the heating time is about 30 minutes to 2 hours. The surface protection sheet 40 preferably has heat resistance such as wrinkles when the closing member is thermally hardened. In addition, it is preferable that the surface protection sheet 40 is made of a material that can be peeled off from the semiconductor wafer CP after thermosetting treatment.

The surface protection sheet 40 may be attached to a plurality of semiconductor chips CP and the second ring frame. When the second ring-shaped frame is used, the second ring-shaped frame is placed on the fourth adhesive layer 42 of the surface protection sheet 40, and this is pressed lightly to fix it. After that, the fourth adhesive layer 42 exposed inside the ring shape of the second ring frame is pressed against the circuit surface W1 of the semiconductor wafer CP to be fixed.

After attaching the surface protection sheet 40, the second adhesive sheet 20 is peeled off At this time, the back surface W3 of the plurality of semiconductor wafers CP is exposed. After peeling off the second adhesive sheet 20, the distance D2 between the plurality of semiconductor wafers CP expanded in the expansion process is preferably maintained. For the case where an energy ray polymerizable compound is added to the second adhesive layer 22, the second adhesive layer 22 is irradiated with energy rays from the side of the second base film 21 to harden the energy ray polymerizable compound, and then the first It is better to stick the thin sheet 20.

FIG. 3B is a diagram illustrating a process of closing a plurality of semiconductor wafers CP held by the surface protection sheet 40.

When a plurality of semiconductor wafers CP are covered via the closing member 60 via the remaining circuit surface W1, the closing body 3 is formed. The plurality of semiconductor wafers CP are also filled with the closing member 60. In this embodiment, since the circuit surface W1 and the circuit W2 are covered with the surface protection sheet 40, it is possible to prevent the circuit surface W1 from being covered with the sealing member 60.

Through the closing process, a plurality of semiconductor wafers CP separated by a specific distance are embedded in the closing body 3 of the closing member. In the closing process, it is preferable that the plurality of semiconductor wafers CP are covered with the closing member 60 while maintaining the distance D2.

The method of covering a plurality of semiconductor wafers CP with the closing member 60 is not particularly limited. For example, a method in which the circuit surface W1 is covered with the surface protection sheet 40, a plurality of semiconductor wafers CP is housed in a metal mold, and then a fluid resin material is injected into the metal mold to harden the resin material may be used. In addition, the use of multiple semiconductors On the back surface W3 of the wafer CP, a sheet-shaped sealing resin is placed, and by heating the sealing resin, a plurality of semiconductor wafers CP may be embedded in the sealing resin. Examples of the material of the closing member 60 include epoxy resin. The epoxy resin used as the sealing member 60 may include, for example, a phenol resin, an elastomer, an inorganic filler, and a hardening accelerator.

After the surface protection sheet 40 is peeled off after the closing process, the circuit surface W1 of the semiconductor wafer CP and the surface 3S in contact with the surface protection sheet 40 of the enclosure 3 are exposed.

[Manufacturing Engineering of Semiconductor Packaging]

4 and 5 are diagrams illustrating the manufacturing process of the semiconductor package using plural semiconductor wafers CP. This embodiment is preferably a manufacturing process including such a semiconductor package.

[Rewiring layer formation project]

FIG. 4A is a cross-sectional view of the closing body 3 after the surface protection sheet 40 is peeled off. In the present embodiment, it is more preferable to include the closed body 3 after the surface protection sheet 40 is peeled off, and a rewiring layer forming process for forming a rewiring layer. In the redistribution layer forming process, the rewiring connected to the circuit W2 of the plurality of exposed semiconductor wafers CP is formed on the circuit surface W1 and the surface 3S of the enclosure 3. For the formation of rewiring, first, an insulating layer is formed on the closing body 3.

FIG. 4B shows the circuit explained on the semiconductor chip CP The surface W1 and the surface 3S of the closed body 3 form a cross-sectional view of the process of forming the first insulating layer 61. The first insulating layer 61 containing an insulating resin is formed on the circuit surface W1 and the surface 3S to expose the circuit W2 or the internal terminal electrode W4 of the circuit W2. Examples of the insulating resin include polyimide resin, polybenzoxazole fiber resin, and polysiloxane resin. The material of the internal terminal electrode W4 is not limited if it is a conductive material, and examples thereof include metals such as gold, silver, copper, and aluminum, and alloys.

FIG. 4C is a cross-sectional view showing the process of forming the redistribution 5. The rewiring 5 is electrically connected to the semiconductor wafer CP enclosed in the enclosure 3. In the present embodiment, the rewiring 5 is formed following the formation of the first insulating layer 61. The material of the rewiring 5 is not limited as long as it is a conductive material, and examples thereof include metals such as gold, silver, copper, and aluminum, and alloys. The rewiring 5 system can be formed by a known method.

FIG. 5A is a cross-sectional view illustrating the process of forming the second insulating layer 62 of the covered redistribution 5. The redistribution 5 has an external electrode pad 5A for external terminal electrodes. The second insulating layer 62 is provided with an opening or the like to expose the external electrode pad 5A for the external terminal electrode. In the present embodiment, the external electrode pad 5A is exposed within the range of the semiconductor wafer CP of the enclosure 3 (the range of the circuit surface W1) and outside the range (corresponding to the range of the surface 3S on the closure member 60) . In addition, the redistribution 5 series external electrode pads 5A are arranged in an array and formed on the surface 3S of the closed body 3. In the manufacturing process of this embodiment, external electrode pads are formed outside the range of the semiconductor wafer CP of the enclosure 3 Because of the exposed structure of the sheet 5A, a fan-out WLP can be obtained.

[Connection project with external terminal electrode]

FIG. 5B is a cross-sectional view illustrating the process of connecting the external terminal electrode 5A to the external electrode pad 5A of the enclosure 3 and connecting the external terminal electrodes. In the external electrode pad 5A exposed from the opening or the like provided in the second insulating layer 62, the external terminal electrode 7 such as a solder ball is placed, and the external terminal electrode 7 and the external electrode pad 5A are electrically connected by solder bonding or the like connection. The material of the solder ball is not particularly limited, and examples include lead-containing solder and lead-free solder.

[Second Cutting Project]

For the 5C system, a cross-sectional view illustrating a process (also referred to as a second cutting process) of the closed body 3 in which the external terminal electrode 7 is connected in pieces is shown. In the second dicing process, the closed body 3 is sliced in units of semiconductor wafer CP. The method of individualizing the closed body 3 is not particularly limited. For example, the same method as the method of cutting the aforementioned semiconductor wafer W may be used to individualize the enclosed body 3. The process of individualizing the closed body 3 is implemented by attaching the closed body paste 3 to an adhesive sheet such as a cutting sheet.

The semiconductor package 1 of the semiconductor wafer CP unit is manufactured from the individualized closed bodies 3. As described above, the semiconductor package 1 that connects the external terminal electrode 7 to the external electrode pad 5A that makes the fan out of the semiconductor chip CP is used as a fan-out wafer-level package (FO-WLP). manufacture.

[Installation work]

In the present embodiment, it is also preferable to include a process of mounting the individual semiconductor packages 1 into a printed wiring board or the like.

According to the present embodiment, the semiconductor wafer W is divided into a plurality of semiconductor wafers CP by a so-called dicing method, so that the disorder of the arrangement state of the semiconductor wafers CP during dicing can be prevented. Furthermore, as in this embodiment, a plurality of semiconductor wafers CP divided into pieces by the first dicing method is attached to the second adhesive sheet 20, and the plurality of semiconductor wafers CP can be expanded by stretching the second adhesive sheet 20 Separated from each other. In the expansion process, it is possible to prevent the disorder of the arrangement state of the plural semiconductor wafers CP.

The method according to this embodiment is excellent in the suitability for the process of manufacturing the FO-WLP type semiconductor package 1. Specifically, according to this embodiment, it is possible to improve the uniformity and accuracy of the wafer spacing in the FO-WLP type semiconductor package 1.

[Second Embodiment]

The second embodiment is different from the first embodiment in the processing from the process of peeling the first adhesive sheet 10 in the first embodiment to the process of forming a redistribution layer. The second embodiment is the same as the first embodiment in other points, and the description is omitted or simplified.

FIG. 6A is a diagram illustrating the process of peeling off the first adhesive sheet 10 in this embodiment.

In this embodiment, the second adhesive sheet 20 is attached to the After the back surface W3 of the conductor wafer CP, only the process of peeling the first adhesive sheet 10 is performed. That is, in the first embodiment, when the first adhesive sheet 10 is peeled off, the protective sheet 30 that has been cut is also peeled off together, and in this embodiment, the protective sheet 30 is kept remaining on the semiconductor wafer CP The first adhesive sheet 10 on the circuit surface W1.

In the case where the energy ray polymerizable compound is added to the first adhesive layer 12, the energy ray polymerizable compound is hardened by irradiating the energy ray to the first adhesive layer 12 from the first base film 11 side. When the energy ray polymerizable compound is hardened, the cohesive force of the first adhesive layer increases, and the adhesive force between the first adhesive layer 12 and the protective sheet 30 decreases or disappears. At this time, it is preferable that the adhesive force of the third adhesive layer 32 of the protective sheet 30 decreases or disappears, and it is preferable to irradiate energy rays. Examples of the energy ray system include ultraviolet rays (UV) and electron beams (EB), and ultraviolet rays are preferred.

In the present embodiment, the adhesive force for the semiconductor wafer W of the second adhesive layer 22 is better than the adhesive force for the third substrate film 31 of the first adhesive layer 12. Furthermore, the adhesive force for the third substrate film 31 of the first adhesive layer 12 is preferably smaller than the adhesive force for the semiconductor wafer W of the third adhesive layer 32. In this embodiment, the first adhesive sheet 10, the second adhesive sheet 20, and the protective sheet 30 are attached to the semiconductor wafer CP, and only the first adhesive sheet 10 is peeled in advance. Therefore, when the adhesive force of the first adhesive layer 12 is low, the divided protective sheet 30 remains on the semiconductor wafer CP and is easily peeled off.

FIG. 6B is a diagram illustrating the expansion process of stretching the second adhesive sheet 20 after peeling the first adhesive sheet 10.

For the second adhesive sheet 20, a plurality of holding circuit surfaces W1 are applied to cover the semiconductor wafer CP of the protective sheet 30. In the expansion process of this embodiment, the second adhesive sheet 20 is stretched in such a state, and the plurality of semiconductor wafers CP are expanded to a distance D2.

FIG. 6C is a diagram illustrating a process of closing a plurality of semiconductor wafers CP after the expansion process is implemented.

In the first embodiment, when the surface protection sheet 40 is attached to the circuit surface W1, the second adhesive sheet 20 is peeled off, and the semiconductor wafer CP is closed using the closing member 60, in this embodiment, the Since the protective sheet 30 is attached to the circuit surface W1, even if the surface protective sheet 40 is not attached, it can be held on the back surface W3 of the semiconductor wafer CP, and the second adhesive sheet 20 is attached and closed. When a plurality of semiconductor wafers CP are covered via the closing member 60 via the remaining circuit surface W1, a closing body 3A is formed. The surface 3S of the closing body 3A and the circuit surface W1 of the semiconductor wafer CP are preferably the same surface.

In the present embodiment, as shown in FIG. 6C, a sealing member 60 is filled between or around a plurality of semiconductor wafers CP. In this embodiment, since the circuit surface W1 and the circuit W2 are covered by the protective sheet 30, the circuit surface W1 may be covered by the sealing member 60. In the closing process, the second adhesive sheet 20 is attached to the back surface W3 of the semiconductor wafer CP. Therefore, the back surface W3 of the semiconductor wafer CP is not covered by the closing member 60, and the thickness of the closing body 3A can be thinned By.

Through the closing process of the present embodiment, a closed body 3A in which a plurality of semiconductor wafers CP isolated at specific distances are embedded in the closing member 60 can be obtained. In the closing process, it is preferable that the plurality of semiconductor wafers CP are covered with the closing member 60 while maintaining the distance D2.

After the closing process, the protective sheet 30 and the second adhesive sheet 20 are peeled off. The order of peeling these is not specifically limited. When the protective sheet 30 is peeled off, for example, an adhesive tape is preferably used. An adhesive tape may be attached to the surface of the third base film 31 of the protective sheet 30, and the protective sheet 30 may be peeled off using the adhesive tape as a base point. Then the tape system can also be adhesive tape or heat sealing tape. When the second adhesive sheet 20 is peeled off, the back surface W3 of the semiconductor wafer CP is exposed.

The closed body 3A can be used, and the semiconductor package or semiconductor device can be manufactured through the same process as the first embodiment.

According to the manufacturing method of this embodiment, as in the first embodiment, it is possible to prevent the disorder of the arrangement state of the plurality of semiconductor wafers CP. The method of this embodiment is also excellent in the suitability for the processing of manufacturing FO-WLP type semiconductor packages, and it is also possible to manufacture thin semiconductor packages.

[Third Embodiment]

The third embodiment relates to the process up to the second expansion project in the first embodiment, and is the same as the first embodiment. Therefore, for Similar points are omitted or simplified. In the following, the differences from the first embodiment in the third embodiment will be described.

In the third embodiment, the expansion process is carried out, and after the interval between the plurality of semiconductor wafers CP is enlarged, the closing process is not performed, and the plurality of semiconductor wafers CP are picked up. The pickup system can use the pickup device used in the past. In this embodiment, it is also preferable to include the engineer who mounts the picked semiconductor wafer CP on each of the printed wiring board and the like. The semiconductor wafer CP after mounting is encapsulated by, for example, a sealing member or the like.

According to this embodiment, while preventing the disorder of the arrangement state of the semiconductor wafers CP, and after increasing the interval between the plural semiconductor wafers CP, the semiconductor wafer CPs can be picked up. Therefore, it becomes possible to easily prevent the semiconductor wafer CP held by the pickup device from coming into contact with other semiconductor wafers and the pickup device from coming into contact with other semiconductor wafers during pickup.

[Variation of embodiment]

The present invention is not limited to the above-mentioned embodiments. The present invention is within the scope of achieving the object of the present invention, and the forms of the above embodiments are modified.

For example, the semiconductor wafer or the circuit of the semiconductor wafer is not limited to the arrangement or shape shown in the figure. The connection structure to the external terminal electrode in the semiconductor package and the like are not limited to those described in the foregoing embodiments. In the foregoing embodiment, FO-WLP has been manufactured Type of semiconductor package, but the present invention is also applicable to the manufacture of fan-in type WLP and other semiconductor packages.

For example, in the foregoing embodiment, the embodiment in which the protective sheet 30 is attached to the circuit surface W1 of the semiconductor wafer W and the trench formation process is performed, but the present invention is not limited to such an embodiment. For example, the protective sheet 30 is not attached to the circuit surface W1, but the circuit surface W1 is kept exposed to perform the trench formation process, and after the trench is formed, the first adhesive sheet 10 is attached to the circuit surface W1 to perform the grinding process , Also included in the invention. In addition, before the trench formation process, a protective film covering the circuit surface W1 may be formed. The protective film preferably has a shape that exposes the internal terminal electrode W4 of the circuit W2. The protective film system is preferably formed using, for example, silicon nitride, an oxide system, or polyimide.

For example, in the foregoing embodiment, an example in which the interval between the plurality of semiconductor wafers CP is expanded by stretching the second adhesive sheet 20 is exemplified, but it may be implemented by adding an expansion process. In the case where the expansion project is carried out a plurality of times, the plurality of semiconductor wafers CP held in the second adhesive sheet 20 can be maintained and maintained at the enlarged interval, and transferred to another expansion sheet, and the expansion sheet can be expanded to expand the plural The semiconductor wafers CP are separated from each other. For example, in the first embodiment, after the surface protection sheet 40 is attached, the surface protection sheet 40 is stretched to further increase the interval between the plural semiconductor wafers CP.

For example, in the foregoing embodiment, a method of manufacturing a semiconductor device including a process of forming a trench having a shallower cutting depth than the thickness of a semiconductor wafer has been exemplified, but a semiconductor crystal in which the trench is formed in advance may also be used round.

10‧‧‧The first adhesive sheet

11‧‧‧ First substrate film

12‧‧‧The first adhesive layer

30‧‧‧Protection sheet

31‧‧‧The third substrate film

32‧‧‧The third adhesive layer

50‧‧‧Grinding machine

W‧‧‧Semiconductor wafer

CP‧‧‧Semiconductor chip

W1‧‧‧circuit side

W2‧‧‧circuit

W3‧‧‧Back

W5‧‧‧Ditch

W6‧‧‧Back

Claims (3)

A method of manufacturing a semiconductor device, comprising: a process of attaching a third adhesive sheet on the first surface of a semiconductor wafer, and cutting the third adhesive sheet on the first surface The process of forming a trench with a shallow cutting depth of the semiconductor wafer, and the third adhesive sheet on which the first surface on which the trench is formed is cut, the process of attaching the first adhesive sheet, and grinding and The process of pasting the second surface opposite to the first surface of the first adhesive sheet to thin the thickness of the semiconductor wafer, dividing the semiconductor wafer into a plurality of semiconductor wafers, and The third surface of the plurality of semiconductor wafers appearing on both sides, the process of attaching the second adhesive sheet, and leaving the third adhesive sheet on the first surface, peeling off the first adhesive sheet After extending the second adhesive sheet to expand the interval between the plurality of semiconductor wafers, and expanding the interval between the plurality of semiconductor wafers, the second surface is pasted on the third surface, An engineer who sticks the first surface of the third adhesive sheet and coats the plurality of semiconductor chips with a sealing member. A method for manufacturing a semiconductor device as described in item 1 of the patent application range, wherein a plurality of circuits are formed on the first surface, and the groove is formed to separate the plurality of circuits. According to the method of manufacturing a semiconductor device described in item 1 or item 2 of the patent application, the second adhesive sheet has a tensile modulus of elasticity smaller than that of the first adhesive sheet.

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