TWI685024B - 半導體元件製造方法 - Google Patents

半導體元件製造方法 Download PDF

Info

Publication number
TWI685024B
TWI685024B TW105103802A TW105103802A TWI685024B TW I685024 B TWI685024 B TW I685024B TW 105103802 A TW105103802 A TW 105103802A TW 105103802 A TW105103802 A TW 105103802A TW I685024 B TWI685024 B TW I685024B
Authority
TW
Taiwan
Prior art keywords
metal gate
layer
dielectric layer
interlayer dielectric
mechanical polishing
Prior art date
Application number
TW105103802A
Other languages
English (en)
Other versions
TW201705232A (zh
Inventor
巫柏奇
張家瑋
李榮瑞
張雅嵐
趙益承
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201705232A publication Critical patent/TW201705232A/zh
Application granted granted Critical
Publication of TWI685024B publication Critical patent/TWI685024B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Plasma & Fusion (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一種製造半導體元件的方法，包含：形成層間介電層(ILD)於基板上、形成溝槽於層間介電層中、形成金屬閘極於溝槽中、移除金屬閘極從層間介電層突出之部分、使還原氣體與金屬閘極進行反應、以及移除金屬閘極之上部。

Description

半導體元件製造方法
本發明關於一種半導體製造方法。
從過往至如今，半導體積體電路(IC)產業經歷了指數級的成長。積體電路材料及設計的技術發展促使各代積體電路產生；而新一代擁有比先前一代更小和更複雜的電路。小型化的尺寸特徵為使用多閘極裝置，例如使用鰭式場效電晶體(fin field effect transistor,FinFET)裝置。鰭式場效電晶體裝置之閘極形成並圍繞於延伸自基板的「鰭片」(fin)，因此稱之為鰭式場效電晶體。當該名詞使用於本揭露時，鰭式場效電晶體裝置為任一基於鰭式之多閘極電晶體。鰭式場效電晶體裝置之閘極位於包含有通道區的鰭片之側及/或上方，可使裝置之閘極寬度得以縮小。在某些積體電路的設計中，另一技術節點微縮的進程為置換一般多晶矽電極成金屬電極，以改善特徵尺寸小型化後的裝置效能。在形成金屬電極的方法中，金屬的偽閘極取代典型為多晶矽的偽閘極，並以後閘極(gate last)法或置換型閘極(replacement gate)法而形成。在上述方法中，因為金屬閘極為在製程後段提供，可在製程中避免功函數穩定度的問題。
根據本揭露之部份實施方式中，一種製造半導體元件的方法，包含：形成層間介電層(interlayer dielectric,ILD)於基板上、形成溝槽於層間介電層中、形成金屬閘極於溝槽中、移除金屬閘極從層間介電層突出之部分、使還原氣體與金屬閘極進行反應、以及移除金屬閘極之上部。
根據本揭露之部份實施方式中，一種製造鰭式場效電晶體(fin field effect transistor,FinFET)裝置的方法，包含：形成層間介電層於基板上；形成溝槽於層間介電層中；形成功函數金屬層及金屬閘極於溝槽中，其中功函數金屬層位在溝槽及金屬閘極之間；形成汲極區及源極區於金屬閘極之相對側；藉由化學機械研磨製程，移除金屬閘極及功函數金屬層從層間介電層突出之部分；使還原氣體與金屬閘極進行反應；移除金屬閘極之上部以及功函數金屬層之上部；以及形成介電層於金屬閘極以及功函數金屬層之上。
根據本揭露之部份實施方式中，一種半導體元件，包含：層間介電層，具有溝槽；金屬閘極，形成於溝槽中；功函數金屬層，形成於金屬閘極與溝槽之間，其中金屬閘極的高度大於功函數金屬層的高度；以及介電層，形成於金屬閘極以及功函數金屬層之上。
100‧‧‧鰭狀場效電晶體裝置
102‧‧‧基板
104,106‧‧‧鰭狀結構
108‧‧‧淺構槽隔離結構
110‧‧‧閘極結構
112‧‧‧通道區
114‧‧‧源極區
116‧‧‧汲極區
200‧‧‧基板
202‧‧‧鰭狀結構
204‧‧‧絕緣層
206‧‧‧介面層
208‧‧‧偽閘極材料層
210‧‧‧圖案化遮罩層
212‧‧‧堆疊結構
214‧‧‧間隔物
216‧‧‧接觸蝕刻停止層
218‧‧‧層間介電層
220‧‧‧溝槽
222‧‧‧介面層
224‧‧‧高介電常數介電層
236‧‧‧複合金屬層
240‧‧‧阻障層
242‧‧‧功函數金屬層
244‧‧‧金屬閘極
250‧‧‧還原氣體
260‧‧‧介電層
從以下結合所附圖式所做的詳細描述，可對本揭 露之態樣有更佳的了解。需注意的是，根據業界實務的標準做法，各種特徵不是按比例繪製。實際上，為了清楚討論起見，各種特徵的尺寸可任意放大或縮小。
第1圖為根據本揭露之部份範例性的實施方式之鰭式場效電晶體裝置之態樣的立體視圖。
第2A圖至第2J圖為根據本揭露部份範例性的實施方式繪示鰭式場效電晶體裝置形成方法的多個步驟，其中第2A圖至第2E圖為立體視圖，第2F圖至第2J圖為剖面圖。
以下的揭露提供了許多不同實施方式或範例，以實施所提供之標的之不同特徵。以下所描述之構件與安排的特定範例係用以簡化本揭露。當然這些僅為範例，並非用以做為限制。舉例而言，於描述中，第一特徵形成於第二特徵上方或上，可能包含第一特徵與第二特徵以直接接觸的方式形成的實施方式，亦可能包含額外特徵可能形成在第一特徵與第二特徵之間的實施方式，如此第一特徵與第二特徵可能不會直接接觸。此外，本揭露可能會在各範例中重複參考數字及/或文字。這樣的重複係基於簡化與清楚之目的，以其本身而言並非用以指定所討論之各實施方式及/或配置之間的關係。
在此說明中可能會使用空間相對用語，例如「下方(beneath)」、「下方(below)」、「較低(lower)」、「上方(above)」、「較高(upper)」等等，以方便說明如圖式所繪示之一元件或一特徵與另一(另一些)元件或特徵之關係。除了 在圖中所繪示之方向外，這些空間相對用詞意欲含括元件在使用或操作中的不同方位。設備可能以不同方式定位(旋轉90度或在其他方位上)，因此可利用同樣的方式來解釋在此所使用之空間相對描述符號。
本揭露主要關於半導體元件，例如鰭式場效電晶體(fin field effect transistor,FinFET)裝置，以及製造鰭式場效電晶體裝置或部分裝置的方法。在特徵尺寸持續縮小下，意欲將閘極氧化物及多晶閘極電極置換為高介電閘極介電質及金屬閘極電極，以改善裝置效能。後閘極(或置換型閘極)法之實施為考量到金屬材料製程所用的高溫。然而，在如金屬閘極鰭式場效電晶體裝置中，挑戰性在於提供合適的應力及/或閘極電阻。舉例而言，閘極之低應力及/或高閘極電阻可能導致裝置效能的衰減。因此，在如金屬閘極鰭式場效電晶體裝置中，需要平衡應力及/或閘極電阻，從而改善閘極漏電及/或功函數。
第1圖為根據本揭露部份範例性的實施方式之鰭式場效電晶體裝置之立體視圖。鰭式場效電晶體裝置100包含基板102。於部份實施方式中，基板102包含體矽基板。基板102可為矽之晶態結構。在其它實施方式中，基板102可包含其它元素半導體，例如鍺，或包含化合物半導體，例如碳化矽、砷化鎵、砷化銦、及磷化銦。於部份其它實施方式中，基板102包含絕緣層覆矽(silicon-on-insulator,SOI)基板。絕緣層覆矽基板之製造可使用氧離子植入矽晶隔離法(separation by implantation of oxygen,SIMOX)、晶圓貼合法及/或其它適 合的方法。
鰭式場效電晶體裝置100更包含延伸自基板102之鰭狀結構104、106(例如，矽鰭片)。於部份實施方式中，鰭狀結構104、106可選擇性地包含鍺。鰭狀結構104、106可藉由利用適合的製程，例如，顯影或蝕刻製造而成。於部份實施方式中，自基板102蝕刻鰭狀結構104、106是利用乾式蝕刻或電漿製程。圍繞鰭狀結構104、106的是淺溝槽隔離(shallow trench isolation,STI)結構108。淺溝槽隔離結構108可包含任何合適的絕緣材料。應了解，儘管繪示為兩個鰭狀結構，仍可用類似方式形成其它平行鰭片。
鰭式場效電晶體裝置100更包含一閘極結構110。閘極結構110形成於位在鰭狀結構104、106之中央部分。於部份實施方式中，形成多閘極結構於鰭狀結構之上。閘極結構110包含閘極介電層及閘極電極。應了解，許多其它層亦可並存，例如，覆蓋層、介面層、間隔物、及/或其它適合的特徵。於部份實施方式中，閘極介電層可更包含其它介電材料，例如，矽氮化物、矽氮氧化物、具有高介電常數(high-k)之介電質、及/或上述之組合。高介電常數之介電材料包含：鉿氧化物、鋯氧化物、鋁氧化物、二氧化鉿-鋁氧化物合金、鉿矽氧化物、鉿矽氮氧化物、鉿鉭氧化物、鉿鈦氧化物、鋯鉿氧化物、及/或上述之組合。閘極電極可包含多晶矽、及/或包含如鈦氮化物、鉭氮化物、鎳矽化物、鈷矽化物、鉬、銅、鎢、鋁、鈷及/或其它適合的導電材料之金屬化合物的金屬。閘極電極可在後閘極製程(或置換型閘極製程)之中形成，其將於後說 明。
鰭狀結構104、106包含以閘極結構110圍繞之通道區112。可摻雜鰭狀結構104、106以提供適合用於N型鰭式場效電晶體裝置(NMOS device)或P型鰭式場效電晶體裝置(PMOS device)的通道。摻雜鰭狀結構104、106可利用如離子植入、擴散、退火、及/或其它適合的製程。鰭狀結構104、106包含源極區114、及汲極區116，相連於鰭式場效電晶體裝置100。源極區114、及汲極區116可包含用於N型場效電晶體裝置之磊晶(epi)矽或磊晶碳化矽(SiC)，或用於P型場效電晶體裝置之磊晶鍺化矽(SiGe)或磊晶鍺(Ge)。上述鰭式場效電晶體裝置100可被包含於微處理器、儲存單元(例如SRAM)，及/或其它積體電路中。
第2A圖至第2J圖為根據本揭露部份範例性的實施方式繪示鰭式場效電晶體裝置形成方法的多個步驟，其中第2A圖至第2E圖為立體視圖，第2F圖至第2J圖為剖面圖。第2A圖為半導體基板。半導體基板可為具有在第一方向延伸之多鰭狀結構202的含矽基板200。而後，形成絕緣層204以填滿在鰭狀結構202之間較低的溝中，如淺溝槽隔離。絕緣體層204的材料可為矽氧化物，然而並不以此為限。形成絕緣體層204的方法包含設置絕緣材料層於覆有鰭狀結構202的基板200上，選擇性地執行平坦化製程以使絕緣層204平坦化，而後執行回蝕刻製程直到露出鰭狀結構202的上部。鰭狀結構202可包含源極區、汲極區、以及連接源極區與汲極區的通道區。
參考第2B圖，共形地形成介面層206於覆有鰭狀 結構202的基板200上。介面層206的材料包含矽氧化物、矽氮化物、或矽氮氧化物。介面層206為藉由沉積製程而形成，舉例而言，藉由原子層沉積(atomic layer deposition,ALD)製程、化學氣相沉積(chemical vapor deposition,CVD)製程、物理氣相沉積(physical vapor deposition,PVD)製程、或濺射沉積(sputter deposition)製程。需注意的是形成介面層206是藉由沉積製程，而非熱氧化處理。因此不會產生由熱氧化處理所造成的矽消耗，故鰭片102不會在形成介面層206之步驟期間變形。如第2B圖所繪示，介面層206為共形地依每一鰭片202的表面而形成。在本範例性實施方式中，因為形成介面層206為藉由沉積製程而不會消耗矽，鰭狀結構202的形狀得以在形成介面層206後保持完好。
而後，依序形成偽閘極材料層208及遮罩層210於介面層206上。偽閘極材料層208的材料包含多晶矽材料。遮罩層210材料包含矽氧化物、矽氮化物、矽氮氧化物、或上述之組合。偽閘極材料層208及遮罩層210可分別藉由沉積製程形成，舉例而言，藉由原子層沉積製程、化學氣相沉積製程、物理氣相沉積製程、或濺鍍沉積製程。在第2B圖中，範例性繪示單一遮罩層210，然而並不以此為限。在另一範例性實施方式中，遮罩層210可為多層結構，舉例而言，遮罩層210可為包含下矽氮化物層、及上矽氧化物層的多層結構。
參考第2C圖，圖案化遮罩層210、偽閘極材料層208及介面層206以形成堆疊結構212，堆疊結構212包含依序形成於基板200上的介面層206、偽閘極材料層208、及遮罩層 210。堆疊結構212橫跨鰭狀結構202，以不同於第一方向的第二方向延伸。在部分範例性實施方式中，第二方向為垂直第一方向。圖案化的步驟包含執行微影製程及蝕刻製程。
參考第2D圖，形成間隔物214於堆疊結構212旁。形成間隔物214的方法包含形成矽氧化物層於基板上，而後執行非等向性蝕刻製程以移除部分矽氧化物層。而後形成源極區及汲極區(參考第1圖)於間隔物214旁之基板。之後，依序形成接觸蝕刻停止層(contact etch stop layer,CESL)216及層間介電層(interlayer dielectric,ILD)218於基板200上以覆蓋堆疊結構212。接觸蝕刻停止層216包含矽氮化物。層間介電層218的材料包含矽氧化物、矽氮化物、矽氮氧化物、矽碳化物、低介電常數介電材料、或上述之組合。接觸蝕刻停止層216及層間介電層218可分別藉由沉積製程形成，舉例而言，藉由原子層沉積製程、化學氣相沉積製程、物理氣相沉積製程、或濺鍍沉積製程。其後，移除部分接觸蝕刻停止層216及部分層間介電層218，以露出堆疊結構212的上部。前述移除步驟包含執行化學機械研磨製程。
參考第2E圖，移除堆疊結構以形成溝槽220於層間介電層218中。前述移除步驟包含執行回蝕刻製程。需要注意的是，因為在移除堆疊結構的步驟之間移除了介面層206，故可視介面層206為犧牲層。
參考第2F圖，依序形成另一介面層222及高介電常數介電層224於溝槽之至少一面上。介面層222的材料包含矽氧化物、矽氮化物、或矽氮氧化物。介面層222可藉由沉積 製程形成，舉例而言，藉由原子層沉積製程、化學氣相沉積製程、物理氣相沉積製程、或濺鍍沉積製程。需注意的是，形成介面層222是藉由沉積製程，而非熱氧化處理。因此不會產生由熱氧化處理所造成的矽消耗，故鰭片102(參考第2A圖)不會在形成介面層222之步驟期間變形。介面層222為共形地依每一鰭片202的表面而形成。在部分範例性實施方式中，因為形成介面層222為藉由沉積製程而不會消耗矽，鰭狀結構202的形狀得以在形成介面層222後保持完好。
高介電常數介電層224包含具有高介電常數的介電材料。高介電常數材料可為金屬氧化物，例如稀土金屬氧化物。高介電常數材料可選自下方所組成的群組：鉿氧化物(HfO2)、鉿矽氧化物(HfSiO4)、鉿矽氮氧化物(HfSiON)、鋁氧化物(Al2O3)、鑭氧化物(La2O3)、鉭氧化物(Ta2O5)、釔氧化物(Y2O3)、鋯氧化物(ZrO2)、鈦酸鍶氧化物(SrTiO3)、鋯矽氧化物(ZrSiO4)、鉭酸鍶鉍(SrBi2Ta2O9,SBT)、鋯鈦酸鉛(PbZrxTi1-xO3,PZT)、及鈦酸鋇鍶(BaxSr1-xTiO3,BST)，其中x介於0至1。高介電常數介電層224可藉由沉積製程形成，舉例而言，藉由原子層沉積製程、化學氣相沉積製程、物理氣相沉積程、或濺鍍沉積製程。
其後，形成複合金屬層236於基板200上，以至少填滿溝槽220(參考第2E圖)，作為堆疊金屬閘極。複合金屬層236填補溝槽220。複合金屬層236由下至上包含：阻障層240、功函數金屬層242、及金屬閘極244。
形成阻障層240覆蓋於高介電常數介電層224 上。阻障層240可為金屬層，舉例而言，如鈦氮化物(TiN)層。可藉由沉積製程形成阻障層240，舉例而言，藉由原子層沉積製程、化學氣相沉積製程、物理氣相沉積製程、或濺鍍沉積製程。亦可藉由氮化製程形成阻障層240，例如使用熱化學蒸鍍反應氨(NH3)及四氯化鈦(TiCl4)。在部分範例性實施方式中，阻障層240的表面可進一步以氮化製程處理，例如使用氨氣處理。另外，在部分範例性實施方式中，可用後金屬退火(post metal anneal,PMA)製程以改善高介電常數介電層224及阻障層240的密度及品質。
形成功函數金屬層242於阻障層240上。在部分範例性實施方式中，鰭式場效電晶體裝置可為N型金氧半導體裝置(NMOS)，功函數金屬層242之材料，舉例而言，可為鈦、銀、鋁、鈦鋁鉬、鉭、鉭氮化物、鈦鋁碳化物、鈦鋁氮化物、鉭碳化物、鉭碳氮化物、鉭矽氮化物、錳、鋯、或上述之組合。另外，鰭式場效電晶體裝置可為P型金氧半導體裝置(PMOS)，功函數金屬層242之材料，舉例而言，可為鈦氮化物、鎢、鉭、鎳、鉑、釕、鉬、鋁、鎢氮化物、或上述之組合。可藉由沉積製程形成功函數金屬層242，舉例而言，藉由原子層沉積製程、化學氣相沉積製程、物理氣相沉積製程、或濺鍍沉積製程。
形成金屬閘極244於功函數金屬層242上。藉由原子層沉積製程、物理氣相沉積製程、化學氣相沉積製程、或其它製程沉積金屬閘極244於功函數金屬層242上。金屬閘極244的材料，舉例而言，為鋁、鎢、鈷、銅。
在第2F圖中，移除自層間介電層218突出之介面層222、高介電常數介電層224及複合金屬層236(舉例而言，突出於溝槽220外之部分)。從而得到鰭式場效電晶體裝置，其中高介電常數介電層224作為閘極介電層，複合金屬層236作為金屬閘極電極。可藉由化學機械研磨執行移除步驟。
在平坦化鰭式場效電晶體裝置的表面後，為了在裝置的表面上形成介電覆蓋層，需移除部分上方之介面層222、高介電常數介電層224、及金屬閘極244。介電覆蓋層之作用為間隔金屬閘極244與其上方之導線。移除步驟包含使用回蝕刻製程。
然而，化學機械研磨漿為包含懸浮物的水溶液，例如包含矽、鋁、鈰化物研磨劑、氧化劑、聚合物、pH值穩定劑、分散劑、及表面活性劑。懸浮物可能會在化學機械研磨製程期間擴散至金屬閘極244。金屬閘極244受到擴散影響的部分可能會發生回蝕刻失效，從而會影響自動對準接觸窗(SAC window)及良率。
本揭露更包括處理金屬閘極244的方法，從而可防止因擴散物造成的回蝕刻失效。參考第2G圖至第2J圖之根據本揭露部份範例性的實施方式繪示之半導體元件之部分剖面圖，處理方法包含對金屬閘極244使用還原氣體。
在第2G圖中，引入還原氣體250至反應腔。還原氣體250與金屬閘極244接觸。還原氣體250包含還原性氣體，還原性氣體可與金屬閘極244中的擴散懸浮物作反應。還原氣體250具有還原擴散懸浮物的能力(使擴散懸浮物得電子)。還 原氣體250具有還原性或能使它物還原的性質。還原氣體250轉移電子至擴散懸浮物，因此還原氣體250本身為氧化。同時，擴散懸浮物具有氧化性或能使它物氧化的性質，可視為氧化劑。即，擴散懸浮物自還原氣體250得到電子，因此擴散懸浮物本身被還原。
在部分範例性實施方式中，擴散懸浮物可能為有機化合物，或可能包含氯化物。因此，還原氣體250具有還原碳或氯的能力。還原能力涉及物質的電極電位(亦稱作還原電位，或氧化/還原電動勢)。電極電位(還原電位)即物質得到電子而還原之傾向的測量值。電極電位之測量是以伏特(V)或毫伏(mV)表示。每個物質皆具有其本質上之電極電位；電位越大，表示物質的電子親和力越大而傾向還原。
然而，構成金屬閘極244之材料亦為會氧化之材料。因此，需考量還原氣體250的電極電位能使擴散物還原的同時，不能高於金屬閘極244的還原電位而使金屬閘極244氧化。在部分範例性實施方式中，金屬閘極244之材料，舉例而言，可為鋁、鎢、鈷、或銅。還原氣體250的電極電位為大於碳或氯化合物及不大於鋁、鎢、鈷、或銅。
在部分範例性實施方式中，還原氣體250為包含氫氣的氣體，且具有稀釋氣體，如氮、氬、氦之惰性氣體。還原氣體250可包含二亞胺(H2N2)。還原氣體250可包含在使用氫氣中使用的催化劑。上述催化劑的催化還原反應主要用於碳碳鍵的還原。
進一步加熱反應腔及基板200。在部分範例性實 施方式中，可藉由使用光學技術(鎢絲燈或雷射)、熱輻射技術、或使用接收器及射頻(RF)感應加熱法。在反應腔中的還原氣體250亦受熱成高溫還原氣體250，溫度在大約200℃至大約400℃的範圍。氫氣包含氫原子及氫離子，可穿入金屬閘極244。氫氣具有還原擴散物的能力，例如碳及/或氯化物，使得從化學機械研磨漿的擴散物不致影響之後用於金屬閘極244的製程。在部分範例性實施方式中，可在還原製程之後，於金屬閘極244中觀測到碳化合物的還原物，例如有機化合物，及/或氯化物(例如，化學式如Al(Cl)x或W(Cl)y的氯化物)的還原物。
參考第2H圖，移除金屬閘極244的上部。移除步驟包含執行回蝕刻製程。在部分範例性實施方式中，移除步驟包含引入蝕刻劑至反應腔，使蝕刻劑與金屬閘極244反應，其中蝕刻劑對金屬閘極244及功函數金屬層242之間具有高度選擇性。可根據蝕刻劑化學組成、欲達到之蝕刻速率、及其它材料並製程參數，而選擇溫度。在部分範例性實施方式中，用於回蝕刻製程的蝕刻劑為氟系蝕刻劑，例如三氟化氮(NF)、氟氣(F2)、四氟化碳(CF4)、四氟乙烯(C2F4)、六氟乙烷(C2F6)、八氟丙烷(C3F8)、六氟化硫(SF)、及其它氟系蝕刻劑。在部分範例性實施方式中，當使用氟系蝕刻劑時，加熱基板至300℃至400℃的範圍。其它溫度範圍可視蝕刻劑種類變化而使用。可從遠程電漿源引入蝕刻劑至反應腔，以提供激發物質(包含自由基、離子及/或高能分子)。蝕刻劑的流速一般取決於反應腔的尺寸、蝕刻速率、蝕刻均均度、及其它參數。
參考第2I圖，在回蝕刻金屬閘極244之上部之後，移除功函數金屬層242之上部。移除功函數金屬層242上部之蝕刻製程可使用與蝕刻金屬閘極244不同的蝕刻劑。用於移除功函數金屬層242的蝕刻劑亦對功函數金屬層242及金屬閘極244之間有高度選擇性。在部分範例性實施方式中，蝕刻劑可為氯系蝕刻劑，例如氯(Cl2)、三氯甲烷(CHCl3)、四氯化碳(CF4)、及/或三氯化硼(BCl3)，含溴氣體，例如溴化氫(HBr)、及/或三溴甲烷(CHBr3)，含碘氣體，其它適合的氣體及/或電漿，及/或上述之組合。
金屬閘極244及功函數金屬層242為兩步驟蝕刻以獲得高度蝕刻選擇性。金屬閘極244從功函數金屬層242隆起。即金屬閘極244的高度大於功函數金屬層242。在部分範例性實施方式中，金屬閘極244的上平面與功函數金屬層242之間的距離範圍大約為1nm至5nm。
參考第2J圖，形成介電層260覆蓋於金屬閘極244及功函數金屬層242。介電層260填於溝槽220。介電層260之材料包含矽氧化物、矽氮化物、矽氮氧化物、矽碳化物、低介電常數介電材料、或上述之組合。介電層260可藉由沉積製程形成，例如原子層沉積製程、化學氣相沉積製程、物理氣相沉積製程、或濺鍍沉積製程。其後，移除從溝槽(繪示於第2E圖)隆起之部分介電層260。移除步驟包含執行化學機械研磨製程。介電層260、層間介電層218、及接觸蝕刻停止層216之上平面實質位於同一水平，使得半導體元件，如鰭式場效電晶體裝置，可提供平坦化之上平面以在半導體元件上形成電路，而 介電層260則用於隔離電路及金屬閘極244。
藉由引入還原氣體至反應腔，可還原在金屬閘極中的擴散物，使得於金屬閘極之回蝕刻製程可順利執行。
上述已概述數個實施方式的特徵，因此熟習此技藝者可更了解本揭露之態樣。熟悉此技藝者應了解到，其可輕易地利用本揭露做為基礎，來設計或潤飾其他製程與結構，以實現與在此所介紹之實施方式相同之目的及/或達到相同的優點。熟悉此技藝者也應了解到，這類對等架構並未脫離本揭露之精神和範圍，且熟悉此技藝者可在不脫離本揭露之精神和範圍下，進行各種之更動、取代與潤飾。
100‧‧‧鰭狀場效電晶體裝置
102‧‧‧基板
104,106‧‧‧鰭狀結構
108‧‧‧淺構槽隔離結構(STI)
110‧‧‧閘極結構
112‧‧‧通道區
114‧‧‧源極區
116‧‧‧汲極區

Claims (7)

  1. 一種製造半導體元件的方法，包含：依序形成一接觸蝕刻停止層與一層間介電層於一基板上，其中該層間介電層位於該接觸蝕刻停止層上；移除部分該接觸蝕刻停止層及部分該層間介電層，其中該接觸蝕刻停止層之上平面及該層間介電層之上平面實質位於同一水平；形成一溝槽於該層間介電層中；形成一金屬閘極於該溝槽中；執行一化學機械研磨製程以移除該金屬閘極從該層間介電層突出之一部分，其中在該化學機械研磨製程的期間，一化學機械研磨漿中之一懸浮物擴散至該金屬閘極；使一還原氣體與該金屬閘極進行反應，還原擴散至該金屬閘極中的該化學機械研磨漿中之該懸浮物，其中該還原氣體的電極電位不大於該金屬閘極的電極電位且大於該化學機械研磨漿中的該懸浮物的電極電位；以及移除該金屬閘極之一上部。
  2. 如申請專利範圍第1項所述之方法，其中該化學機械研磨漿中的該懸浮物為碳化合物、氯化合物或其組合。
  3. 如申請專利範圍第1項所述之方法，其中，該還原氣體包含氫氣、或二亞胺(H2N2)。
  4. 如申請專利範圍第1項所述之方法，更包含：當該還原氣體與該金屬閘極反應時，加熱該基板。
  5. 如申請專利範圍第1項所述之方法，其中移除該金屬閘極之該部分包含：回蝕刻該金屬閘極。
  6. 一種製造鰭式場效電晶體裝置的方法，包含：依序形成一接觸蝕刻停止層與一層間介電層於一基板上，其中該層間介電層位於該接觸蝕刻停止層上；移除部分該接觸蝕刻停止層及部分該層間介電層，其中該接觸蝕刻停止層之上平面及該層間介電層之上平面實質位於同一水平；形成一溝槽於該層間介電層中；形成一功函數金屬層及一金屬閘極於該溝槽中，其中該功函數金屬層位在該溝槽及該金屬閘極之間；形成一汲極區及一源極區於該金屬閘極之相對側；藉由一化學機械研磨製程，移除該金屬閘極及該功函數金屬層從該層間介電層突出之一部分，其中在該化學機械研磨製程的期間，一化學機械研磨漿中之一懸浮物擴散至該金屬閘極；使一還原氣體與該金屬閘極進行反應，還原擴散至該金屬閘極中的該化學機械研磨漿中之該懸浮物，其中該還原氣體的電極電位不大於該金屬閘極的電極電位且大於該化學機械研磨漿中的該懸浮物的電極電位；移除該金屬閘極之一上部以及該功函數金屬層之一上 部；以及形成一介電層於該金屬閘極以及該功函數金屬層之上。
  7. 如申請專利範圍第6項所述之方法，其中該還原氣體包含氫氣、或二亞胺(H2N2)。
TW105103802A 2015-07-20 2016-02-04 半導體元件製造方法 TWI685024B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562194736P 2015-07-20 2015-07-20
US62/194,736 2015-07-20
US14/831,409 US10090396B2 (en) 2015-07-20 2015-08-20 Method for fabricating metal gate devices and resulting structures
US14/831,409 2015-08-20

Publications (2)

Publication Number Publication Date
TW201705232A TW201705232A (zh) 2017-02-01
TWI685024B true TWI685024B (zh) 2020-02-11

Family

ID=57582940

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105103802A TWI685024B (zh) 2015-07-20 2016-02-04 半導體元件製造方法

Country Status (5)

Country Link
US (4) US10090396B2 (zh)
KR (1) KR101770476B1 (zh)
CN (1) CN106373875B (zh)
DE (1) DE102015114644B3 (zh)
TW (1) TWI685024B (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10090396B2 (en) * 2015-07-20 2018-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating metal gate devices and resulting structures
US10269982B2 (en) * 2016-07-08 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Metallic channel device and manufacturing method thereof
TWI700799B (zh) * 2016-10-04 2020-08-01 聯華電子股份有限公司 導電結構、包含導電結構之佈局結構以及導電結構之製作方法
US10546785B2 (en) * 2017-03-09 2020-01-28 International Business Machines Corporation Method to recess cobalt for gate metal application
CN108630807B (zh) * 2017-03-23 2022-01-28 中芯国际集成电路制造(上海)有限公司 半导体器件、制造方法以及存储器
WO2018195417A1 (en) * 2017-04-20 2018-10-25 Micromaterials Llc Self-aligned contact and gate process flow
US10283417B1 (en) 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Self-protective layer formed on high-k dielectric layers with different materials
US10236220B1 (en) 2017-08-31 2019-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method
KR102394925B1 (ko) 2017-11-16 2022-05-04 삼성전자주식회사 반도체 장치 및 이의 제조 방법
CN108847393B (zh) * 2018-05-24 2021-04-30 上海集成电路研发中心有限公司 鳍式场效应晶体管结构的形成方法
CN109148302B (zh) * 2018-07-23 2021-07-20 上海集成电路研发中心有限公司 一种全包围栅极鳍式场效应晶体管的制作方法
CN109216200B (zh) * 2018-07-27 2021-05-18 上海集成电路研发中心有限公司 一种基于体硅全包围栅极SOI FinFET的制作方法
US11257923B2 (en) * 2018-10-12 2022-02-22 Taiwan Semiconductor Manufacturing Co., Ltd. Tuning threshold voltage in field-effect transistors
CN111223769A (zh) * 2018-11-27 2020-06-02 长鑫存储技术有限公司 半导体结构及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030114000A1 (en) * 2001-12-18 2003-06-19 Hitachi, Ltd. Method for manufacturing semiconductor integrated circuit device
US20130187203A1 (en) * 2012-01-19 2013-07-25 International Business Machines Corporation Formation of the dielectric cap layer for a replacement gate structure
TW201503264A (zh) * 2013-07-12 2015-01-16 United Microelectronics Corp 具有金屬閘極之半導體元件及其製作方法
TW201519410A (zh) * 2013-11-01 2015-05-16 Globalfoundries Us Inc 形成具有多重功函數閘極結構之方法及所產生之產品
US20150200089A1 (en) * 2014-01-10 2015-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method For Metal Gate Surface Clean

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4057803B2 (ja) 2001-09-11 2008-03-05 株式会社東芝 半導体装置の製造方法
JP2003142579A (ja) * 2001-11-07 2003-05-16 Hitachi Ltd 半導体装置の製造方法および半導体装置
US6830998B1 (en) 2003-06-17 2004-12-14 Advanced Micro Devices, Inc. Gate dielectric quality for replacement metal gate transistors
US7144783B2 (en) 2004-04-30 2006-12-05 Intel Corporation Reducing gate dielectric material to form a metal gate electrode extension
US10037905B2 (en) * 2009-11-12 2018-07-31 Novellus Systems, Inc. UV and reducing treatment for K recovery and surface clean in semiconductor processing
JP2011124472A (ja) 2009-12-14 2011-06-23 Toshiba Corp 半導体装置の製造方法
US8436404B2 (en) * 2009-12-30 2013-05-07 Intel Corporation Self-aligned contacts
TWI536451B (zh) 2010-04-26 2016-06-01 應用材料股份有限公司 使用具金屬系前驅物之化學氣相沉積與原子層沉積製程之ｎ型金氧半導體金屬閘極材料、製造方法及設備
CN102983097B (zh) * 2011-09-05 2015-02-18 中芯国际集成电路制造(上海)有限公司 制作金属栅极的金属塞方法
WO2013054652A1 (ja) * 2011-10-11 2013-04-18 株式会社日立国際電気 基板処理装置、基板処理方法、半導体装置の製造方法、および記録媒体
US9111904B2 (en) * 2011-11-29 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate breakdown voltage improvement for group III-nitride on a silicon substrate
US20130187236A1 (en) * 2012-01-20 2013-07-25 Globalfoundries Inc. Methods of Forming Replacement Gate Structures for Semiconductor Devices
US9130023B2 (en) * 2012-06-05 2015-09-08 Kabushiki Kaisha Toshiba Isolated insulating gate structure
CN103632976B (zh) 2012-08-29 2016-06-29 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
US8896030B2 (en) * 2012-09-07 2014-11-25 Intel Corporation Integrated circuits with selective gate electrode recess
CN103794505B (zh) 2012-10-30 2016-04-20 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
US20150024584A1 (en) * 2013-07-17 2015-01-22 Global Foundries, Inc. Methods for forming integrated circuits with reduced replacement metal gate height variability
US9257348B2 (en) 2013-08-06 2016-02-09 Globalfoundries Inc. Methods of forming replacement gate structures for transistors and the resulting devices
US9384985B2 (en) * 2014-07-18 2016-07-05 United Microelectronics Corp. Semiconductor structure including silicon and oxygen-containing metal layer and process thereof
US9583485B2 (en) * 2015-05-15 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor (FinFET) device structure with uneven gate structure and method for forming the same
US10090396B2 (en) * 2015-07-20 2018-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating metal gate devices and resulting structures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030114000A1 (en) * 2001-12-18 2003-06-19 Hitachi, Ltd. Method for manufacturing semiconductor integrated circuit device
US20130187203A1 (en) * 2012-01-19 2013-07-25 International Business Machines Corporation Formation of the dielectric cap layer for a replacement gate structure
TW201503264A (zh) * 2013-07-12 2015-01-16 United Microelectronics Corp 具有金屬閘極之半導體元件及其製作方法
TW201519410A (zh) * 2013-11-01 2015-05-16 Globalfoundries Us Inc 形成具有多重功函數閘極結構之方法及所產生之產品
US20150200089A1 (en) * 2014-01-10 2015-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method For Metal Gate Surface Clean

Also Published As

Publication number Publication date
CN106373875A (zh) 2017-02-01
TW201705232A (zh) 2017-02-01
US11764280B2 (en) 2023-09-19
US20170025514A1 (en) 2017-01-26
US20200343357A1 (en) 2020-10-29
US20180337246A1 (en) 2018-11-22
DE102015114644B3 (de) 2017-01-05
US10090396B2 (en) 2018-10-02
CN106373875B (zh) 2020-01-14
KR101770476B1 (ko) 2017-08-22
US20230395689A1 (en) 2023-12-07
US10714587B2 (en) 2020-07-14
KR20170010706A (ko) 2017-02-01

Similar Documents

Publication Publication Date Title
TWI685024B (zh) 半導體元件製造方法
TWI783439B (zh) 半導體裝置及其形成方法
US10002756B2 (en) Fin-FET device and fabrication method thereof
US11855214B2 (en) Inner spacers for gate-all-around semiconductor devices
TW201830497A (zh) 半導體裝置及其製造方法
US8765556B2 (en) Method of fabricating strained structure in semiconductor device
TW201705476A (zh) 用於鰭場效電晶體元件的方法和結構
TWI768834B (zh) 半導體裝置及其製造方法
US10186579B2 (en) Semiconductor devices
US11088262B2 (en) Radical etching in gate formation
TW202211327A (zh) 半導體裝置及其形成方法
US12057486B2 (en) Metal gate cap
US10741672B2 (en) Gate structure for semiconductor device
TW201816896A (zh) 製造用於n7/n5及超出的鰭式電晶體之空氣空隙間隔壁的方法
TW201824358A (zh) 半導體裝置的製造方法
US11575047B2 (en) Semiconductor device active region profile and method of forming the same
TW202207468A (zh) 半導體裝置及方法
US12080597B2 (en) Semiconductor devices and methods of manufacture
US20220102494A1 (en) Gate Oxide of Nanostructure Transistor with Increased Corner Thickness
TW201921455A (zh) 製造用於水平環繞式閘極元件的接面及間隔物之方法