TW201816896A - 製造用於n7/n5及超出的鰭式電晶體之空氣空隙間隔壁的方法 - Google Patents
製造用於n7/n5及超出的鰭式電晶體之空氣空隙間隔壁的方法 Download PDFInfo
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- TW201816896A TW201816896A TW106137018A TW106137018A TW201816896A TW 201816896 A TW201816896 A TW 201816896A TW 106137018 A TW106137018 A TW 106137018A TW 106137018 A TW106137018 A TW 106137018A TW 201816896 A TW201816896 A TW 201816896A
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- Prior art keywords
- insulating layer
- sacrificial spacer
- fin structure
- spacer layer
- layer
- Prior art date
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- 125000006850 spacer group Chemical group 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title description 3
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 15
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 42
- 230000008569 process Effects 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 18
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 15
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- 238000005192 partition Methods 0.000 claims description 13
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 10
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 10
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 8
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- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 6
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- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
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- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
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Classifications
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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Abstract
於此揭露的實施例相關於具有減低的寄生電容的改良電晶體。在一個實施例中,電晶體裝置包含:三維鰭式結構,該三維鰭式結構自基板的表面突出,該三維鰭式結構包括頂部表面及兩個相對側壁;第一絕緣層,該第一絕緣層在該三維鰭式結構的該兩個相對側壁上形成;犧牲間隔壁層,該犧牲間隔壁層在該第一絕緣層上保形地形成,其中該犧牲間隔壁層包括氧化鋁基材料或氮化鈦基材料;及第二絕緣層,該第二絕緣層在該犧牲間隔壁層上保形地形成。
Description
於此揭露的實施例相關於具有減低的寄生電容的改良電晶體及製造該電晶體的方法。
半導體工業現正自2D電晶體(通常為平面)轉換成具有三維閘極結構的3D電晶體。在3D閘極結構中,通道、源極、及汲極從基板升高且閘極電極接著在三個側面(表面)上將通道包覆。目的在於:限制電流至升高的通道,及取消電子可經其逸漏的任何路徑。此外,閘極電極更有效地控制通道,因為閘極電極延伸覆於通道的多於一個側面。已知一個這種3D電晶體為FinFET(鰭式場效電晶體),其中連接源極及汲極的通道為凸出基板的薄「鰭」。此導致電流被限制前往通道,因而防止電子逸漏。
針對包含複數個半導體鰭(多鰭FinFET)的FinFET電晶體,源極/汲極區域及閘極電極之間固有生成的寄生電容相較於傳統平面FET顯著增加。寄生電容不利地影響積體電路的效能,限制裝置的頻率響應。因此,本領域中具有針對形成具有減低寄生電容的改良多鰭FinFET電晶體之方法的需求。
於此揭露的實施例相關於具有減低的寄生電容的改良電晶體及製造該電晶體的方法。在一個實施例中,提供一種電晶體裝置。電晶體裝置包含:三維鰭式結構,該三維鰭式結構自基板的表面突出,該三維鰭式結構包括頂部表面及兩個相對側壁;第一絕緣層,該第一絕緣層在該三維鰭式結構的該兩個相對側壁上形成;保形的犧牲間隔壁層,該犧牲間隔壁層在該第一絕緣層上形成,其中該犧牲間隔壁層包括氧化鋁基材料或氮化鈦基材料;及保形的第二絕緣層,該第二絕緣層在該犧牲間隔壁層上形成。
在另一實作中,提供一種形成電晶體裝置的方法。該方法包含以下步驟:在基板上形成三維鰭式結構,該三維鰭式結構包括頂部表面及兩個相對側壁,在該三維鰭式結構的該頂部表面及該兩個相對側壁上保形地形成第一絕緣層,在該第一絕緣層上保形地形成犧牲間隔壁層,其中該犧牲間隔壁層包括氧化鋁基材料或氮化鈦基材料;使該犧牲間隔壁層經受一方向性蝕刻處理,以在該三維鰭式結構的該頂部表面處曝露該第一絕緣層;及在該第一絕緣層上該三維鰭式結構的該頂部表面處及該三維鰭式結構的該兩個相對側壁上的該犧牲間隔壁層保形地形成第二絕緣層。
而在另一實作中,該方法包含以下步驟:在基板上形成三維鰭式結構,該三維鰭式結構包括頂部表面及兩個相對側壁;在該第一絕緣層及第二絕緣層之間形成犧牲間隔壁層,其中在該三維鰭式結構的該頂部表面以及該兩個相對側壁上保形地形成該第一絕緣層,其中該犧牲間隔壁層包括氧化鋁基材料或氮化鈦基材料,且空氣空隙間隔壁具有約4 nm或更多的一厚度;及藉由使用感應性耦合電漿來選擇性地移除該犧牲間隔壁層,在該三維鰭式結構的該頂部表面處曝露該第一絕緣層,其中選擇性地移除該犧牲間隔壁層係由以下方式來執行:以第一容量流速率流動氬(Ar)進入電漿腔室及以第二容量流速率流動氯化硼(BCl3
)進入該電漿腔室,其中該第一容量流速率對該第二容量流速率的比率為約1:10或更多;應用約0.028 W/cm2
至約0.056 W/cm2
的偏壓功率至基板支撐,該基板設置於該基板支撐上;及藉由將該基板沉浸在水溶液中來移除該犧牲間隔壁層,以產生該第一絕緣層及該第二絕緣層之間的空氣空隙間隔壁,由混和容積比約4:1的硫酸及過氧化氫溶液來獲得該水溶液。
第1圖為用於形成多鰭FinFET電晶體的示範性處理序列100。第2A至2H圖根據第1圖的處理序列圖示製造的某些階段期間簡化的多鰭FinFET電晶體的透視視圖。雖然在圖式中圖示且於此描述多種步驟,並未暗示有關該等步驟的順序或介入步驟的呈現或未呈現之限制。除非明白規定,僅為了說明的目的將所描繪或所描述步驟採取為序列,不排除個別步驟實際上若非完全地則至少部分地以同時或重疊方式來執行的可能性。
本揭示案的處理序列100起於方塊102:在基板200中形成一個或更多個溝槽204。溝槽204的形成導致基板200具有兩個或更多個鰭結構202,如第2A圖中所展示。鰭結構202自基板200的表面向外突出成為三維結構。鰭結構202可服務如同用於電晶體的底部電極。鰭結構202可具有一般為矩形的橫截面或具有一些其他形狀的橫截面,例如加長的脊形主體,如所展示。雖然將四個鰭結構204展示為範例,思量可蝕刻基板以提供更多或更少的鰭結構,取決於應用。溝槽204可具有高的長寬比。溝槽高度對溝槽寬度的比例(亦即,長寬比)可為例如約20至1、18至1、16至1、14至1、12至1、10至1、9至1、8至1、7至1、6至1、5至1、4至1、3至1、或2至1。在一個範例中,溝槽204具有10:1的長寬比。溝槽204沿著溝槽長度的至少一部分可具有一般恆定的橫截面剖面。在多種實作中,兩個當下相鄰的溝槽204之間的距離可為約3 nm至約20 nm,例如約5 nm至約7 nm。
於此使用的用語「基板」意圖廣義地覆蓋可在處理腔室中處理的任何物體。例如,基板200可為能夠具有沉積於基板上的材料的任何基板,例如矽基板,例如矽(摻雜或未摻雜)、結晶矽(例如,Si <100>或Si <111>)、氧化矽、應變矽、摻雜或未摻雜多晶矽等、鍺、III-V複合基板、鍺化矽(SiGe)基板、碳鍺化矽(SiGeC)基板、氧鍺化矽(SiGeO)基板、氮氧鍺化矽(SiGeON)基板、碳化矽(SiC)基板、氮碳化矽(SiCN)基板、氧碳化矽(SiCO)、epi基板、矽基絕緣體(SOI)基板、摻碳氧化物、氮化矽、顯示器基板如液晶顯示器(LCD)、電漿顯示器、電致發光(EL)燈具顯示器、太陽能陣列、太陽能面板、發光二極體(LED)基板、圖案化或未圖案化半導體晶圓、玻璃、藍寶石、或任何其他材料如金屬、金屬合金、及其他傳導性材料。在一個示範性實作中,基板200為以每立方公分1x1016
個原子的密度摻雜硼的300 mm單晶矽含矽基板。
在方塊104處,使用絕緣體材料208填充溝槽204。鰭結構202被絕緣體材料208的區段彼此分隔,使得鰭結構202在絕緣體材料208的區段之間交錯。絕緣體材料208可為任何適於淺溝槽絕緣(STI)的氧化物。例如,絕緣體材料208可為氧化矽(SiO)、二氧化矽(SiO2
)、氮化矽(SiN)、氮碳化矽(SiCN)、氮氧化矽(SiON)、氧化鋁、或其他合適的介電材料或高k介電材料。可使用任何合適的沉積處理來沉積絕緣體材料208,例如化學氣相沉積(CVD)處理、或電漿增強化學氣相沉積(PECVD)處理。接著使用選擇性氧化物凹陷蝕刻將絕緣體材料208蝕刻回去,以達到溝槽201內所需深度,如第2A圖中所展示。針對亞於10 nm節點的FinFET,溝槽204的深度可為約30 nm及約400 nm之間(自溝槽204的頂部表面218量測至鰭結構202的頂部表面220)。
在方塊106處,在鰭結構202及絕緣體材料208的曝露表面上保形地形成內絕緣層222,如第2B中所展示。內絕緣層222可包含但不限於氮化矽(Si3
N4
)、二氧化矽(SiO2
)、氮氧化矽(SiON)、氧化鋁(Al2
O3
)、氧化鉭(Ta2
O5
)、或具有相似絕緣性及結構屬性的其他材料。在一個實作中,內絕緣層222為Si3
N4
。可使用任何合適的沉積處理來沉積內絕緣層222,例如原子層沉積(ALD)處理、化學氣相沉積(CVD)處理、低壓化學氣相沉積(LPCVD)處理、或電漿增強化學氣相沉積(PECVD)處理。
在一個範例中,使用ALD來沉積內絕緣層222。可使用的示範性沉積系統為OlympiaTM
ALD系統,可自位於加州Santa Clara的應用材料公司取得。內絕緣層222可具有約1 nm至約10 nm的厚度,例如約2 nm至約5 nm。在一個範例中,所沉積的內絕緣層222具有1 nm的厚度。在另一範例中,所沉積的內絕緣層222具有2 nm的厚度。
在方塊108處,在內絕緣層222上保形地沉積犧牲間隔壁層224,如第2C中所展示。在一個實作中,犧牲間隔壁層224包含氧化鋁基材料,例如氧化鋁(Al2
O3
)或氮氧化鋁(AlON)。在另一實作中,犧牲間隔壁層224包含氮化鈦基材料,例如氮化鈦(TiN)。氧化鋁基材料及氮化鈦基材料為具有優勢的,因為曝露以乾蝕刻電漿時,該等材料對氮化矽(Si3
N4
)、二氧化矽(SiO2
)、及多矽(a-Si)具有高的選擇性(大於10:1),該等材料為使用於內絕緣層222(方塊106)、絕緣體材料208(方塊104)、及閘極材料228(方塊116)的示範性材料。可使用任何合適的沉積處理來沉積犧牲間隔壁層224,例如原子層沉積(ALD)處理或化學氣相沉積(CVD)處理。在一個範例中,使用ALD來沉積犧牲間隔壁層224。可在OlympiaTM
ALD系統中沉積犧牲間隔壁層224(可自位於加州Santa Clara的應用材料公司取得)。犧牲間隔壁層224可具有約3 nm至約12 nm的厚度,例如約4 nm至約8 nm,例如約5 nm。在一個範例中,所沉積的犧牲間隔壁層224具有約7 nm的厚度。犧牲間隔壁層224的厚度界定了後續階段中移除犧牲間隔壁層224之後的空氣空隙間隔。本發明人決定:形成5 nm或更多的空氣空隙間隔同時減低Si3
N4
側壁厚度自2 nm至1 nm為具優勢的,因為最大化針對多鰭FinFET電晶體的電容減低,而無後續的寬度減低(即使在高溫退火之後)。
在方塊110處,犧牲間隔壁層224經受方向性蝕刻處理以曝露位於鰭結構202頂部及絕緣體材料208上方的下方內絕緣層222,如第2D圖中所展示。在方向性蝕刻處理之後,鰭結構202的側壁上的犧牲間隔壁層224保持完整。可使用氬(Ar)及氯化硼(BCl3
)在感應性耦合電漿腔室中執行方向性蝕刻處理。將氯化硼(BCl3
)以第一容量流速率導入電漿腔室,且將氬(Ar)以第二容量流速率導入電漿腔室。第一容量流速率對第二容量流速率的比例可為約1:6至約1:15,例如約1:8至約1:10。本揭示案的發明人已觀察到:較低的氣體流動比例及低功率為達成對氮化矽(Si3
N4
)高蝕刻選擇性的關鍵。例如,將第一容量流速率對第二容量流速率的比例決定為約1:10或更多可具有低蝕刻速率(例如,每分鐘60Å),擁有對氮化矽10:1或更多的高選擇性,例如13:1或更多。於此描述的高選擇性意味以高於絕緣層222的速率來蝕刻犧牲間隔壁層224(例如,大於5x)。結果,犧牲間隔壁層224被蝕刻掉,同時保留絕緣層222實質完整。
在一些實施例中,可增加蝕刻處理時間以過度蝕刻犧牲間隔壁層224,因而增強對氮化矽(Si3
N4
)的蝕刻選擇性。在一個範例中,藉由50%或更多的過度蝕刻(例如,75%的過度蝕刻)來蝕刻犧牲間隔壁層224至犧牲間隔壁層224的蝕刻端點。在一些範例中,藉由150%或更多的過度蝕刻(例如,200%的過度蝕刻)來蝕刻犧牲間隔壁層224至犧牲間隔壁層224的蝕刻端點。第3(a)至3(c)圖描繪鰭結構202的側壁上的犧牲間隔壁層的多種TEM影像,分別為乾蝕刻之前、78%過度蝕刻之後、及250%過度蝕刻之後攝取。如可見,第3(b)圖展示78%間隔壁過度蝕刻之後無角落侵蝕發生,而第3(c)圖展示對Si3
N4
非常好的蝕刻選擇性(即使在250%間隔壁過度蝕刻之後)。第3(b)至3(c)圖展示鰭結構202的側壁上的犧牲間隔壁層224沿著鰭結構202的高度方向仍具有均勻覆蓋,而在方向性蝕刻處理之後在鰭結構202的頂部及側壁上沒有實質對內絕緣層222蝕刻。
針對300 mm的基板,可使用以下處理參數。基板支撐的溫度可自約攝氏50度至約攝氏200度,例如約攝氏75度至約攝氏100度,例如約攝氏90度。腔室壓力可為約1 mTorr至約80 mTorr,例如約3 mTorr至約20 mTorr,例如約5 mTorr。BCl3
的流速率可為自約20 sccm至約150 sccm,例如約35 sccm至約80 sccm,例如約50 sccm。氬的流速率可為約150 sccm至約350 sccm,例如約200 sccm至約300 sccm,例如約250 sccm。至線圈的來源功率可為約100 W至約1000 W,例如約250 W至約600 W,例如約400 W。至基板支撐的偏壓功率可為約10 W至約80 W,例如約20 W至約40 W,例如約25 W。蝕刻處理時間可為約5秒至約600秒之間,例如約30秒至約360秒,例如約120 秒。蝕刻處理時間可隨著所需蝕刻剖面而變化。可使用的示範性蝕刻腔室為Centura®
AdvantEdgeTM
MesaTM
蝕刻腔室,可自位於加州Santa Clara的應用材料公司取得。
在方塊112處,在曝露的內絕緣層222及犧牲間隔壁層224上保形地形成外絕緣層226,如第2E中所展示。沉積內絕緣層222及外絕緣層226以防止Al2
O3
沉積及後續階段中的蝕刻處理期間對高k材料的損壞。外絕緣層226可使用與內絕緣層222相同的材料,例如氮化矽(Si3
N4
)、二氧化矽(SiO2
)、氮氧化矽(SiON)、氧化鋁(Al2
O3
)、氧化鉭(Ta2
O5
)、或具有相似絕緣性及結構屬性的其他材料。在一個實作中,外絕緣層226為Si3
N4
。可使用任何合適的沉積處理來沉積外絕緣層226,例如原子層沉積(ALD)處理、化學氣相沉積(CVD)處理、低壓化學氣相沉積(LPCVD)處理、或電漿增強化學氣相沉積(PECVD)處理。在一個範例中,使用ALD來沉積外絕緣層226。可使用的示範性沉積系統為OlympiaTM
ALD系統,可自位於加州Santa Clara的應用材料公司取得。外絕緣層226可具有約1 nm至約10 nm的厚度,例如約2 nm至約5 nm。在一個範例中,所沉積的外絕緣層226具有約1 nm的厚度。在另一範例中,所沉積的外絕緣層226具有約2 nm的厚度。
在方塊114處,可執行可選的蝕刻處理以選擇性地曝露鰭結構202的側壁上的犧牲間隔壁層224的頂部部分224a,如第2F圖中所展示。可使用任何合適的乾蝕刻或濕蝕刻處理來進行蝕刻。在一個範例中,可選的蝕刻處理為使用感應性耦合電漿來源的乾蝕刻處理。電漿可由先驅氣體形成,包含例如氬、氮、氫、一氧化碳、氨、或氦。選擇地,可使用鹵基先驅物以形成電漿。可在Centura®
AdvantEdgeTM
MesaTM
蝕刻腔室中執行蝕刻處理,可自位於加州Santa Clara的應用材料公司取得。
在方塊116處,使用閘極材料228填充溝槽204。閘極材料228可由非晶矽(a-Si)或多晶矽(poly-Si)組成,無論摻雜或未摻雜。閘極材料228可包含傳導性材料,例如金屬。在一個實作中,閘極材料228為poly-Si。選擇地,可在溝槽204內沉積非晶薄膜形式的閘極材料228,接著經受高溫處理以轉換非晶薄膜至多晶狀態。可使用任何合適的沉積處理來沉積閘極材料228,例如化學氣相沉積(CVD)處理、低壓CVD (LPCVD)處理、或物理氣相沉積(PVD)處理。可沉積閘極材料228至所需厚度,例如約100 nm。接著使用化學機械研磨(CMP)來研磨閘極材料228以曝露鰭結構202的頂部表面220及鰭結構202側壁上的犧牲間隔壁層224的頂部部分224a,如第2G圖中所展示。
在方塊118處,選擇性地移除犧牲間隔壁層224,如第2H圖中所展示。移除犧牲間隔壁層224導致在剩餘的內絕緣層222及剩餘的外絕緣層226之間的區域中形成空氣空隙230。因為空氣具有任何材料最低的介電常數,沿著鰭結構202的高度方向(亦即,沿著鰭結構202的側壁)包容空氣空隙230減低了多鰭FinFET電晶體的整體介電常數。多鰭FinFET電晶體因而在移除犧牲間隔壁層224完成之後具有空氣空隙所形成的側壁間隔壁。已觀察到:相較於由其他傳統材料(例如,SiN、SiO2
、或poly-Si)形成的側壁間隔壁,使用沿著鰭結構側壁的空氣空隙組成的間隔壁可減低側壁間隔壁電容超過70%。結果,減低了相鄰部件(例如,閘極電極及靠近鰭結構形成的源極/汲極區域)之間的寄生電容。
可藉由濕蝕刻或乾蝕刻處理來移除犧牲間隔壁層224。蝕刻處理應使用對Si3
O4
、SiO2
、及poly-Si具有好的選擇性的蝕刻劑。在使用濕蝕刻處理的一個示範性實施例中,藉由將基板200沉浸在水溶液形式的SPM化學溶液中來移除犧牲間隔壁層224,以容積比約4:1混和硫酸(97%)及過氧化氫溶液來獲得該溶液。可執行濕蝕刻處理約3秒至約30秒,例如約5秒至約15秒。在沉浸之後,基板200可被純水沖洗約5分鐘至約10分鐘且以空氣或氮吹來烘乾。雖然論述的是SPM化學溶液,思量也可使用其他濕蝕刻溶液,例如鹽酸/過氧化氫混和物(HPM)、過氧化氫銨混和物(APM)、稀釋的氫氟酸(DHF)、FPM(氫氟酸、過氧化氫水、及純水的混和溶液)等等。
已觀察到:在3秒的SPM之後,可看見30 nm深的空氣空隙,且在5秒的SPM之後,犧牲間隔壁層224被完全移除。第4(a)至4(b)圖描繪TEM影像,展示移除犧牲間隔壁層224之前及之後的結果。第4(a)圖展示第2G圖中的基板狀態(亦即,在poly-Si沉積及poly-Si CMP之後)。第4(b)圖展示第2H圖中的基板狀態(亦即,在移除犧牲間隔壁層之後但在空氣空隙間隔壁密封之前)。
雖然將犧牲間隔壁層224描述為在接點金屬化之前移除,在一些實作中,在接點金屬化之後移除犧牲間隔壁層224。這是因為SPM濕蝕刻僅可在接點金屬化之前使用。在該情況下,可藉由電漿來移除犧牲間隔壁層224,該電漿由氯化硼(BCl3
)或溴化氫(HBr)之任一者形成。
在方塊120處,自內絕緣層222及外絕緣層226之間的區域移除犧牲間隔壁層224之後,在基板200上沉積封蓋層232以密封空氣空隙230的頂部開口,如第2H圖中所展示。封蓋層232可包含但不限於氮化矽(Si3
N4
)、氮氧化矽(SiON)、氮碳化矽(SiCN)、或其他適於密封空氣空隙230的頂部開口的材料。在一個實作中,封蓋層232為Si3
N4
。可使用任何合適的沉積處理來沉積封蓋層232,例如化學氣相沉積(CVD)處理、原子層沉積(ALD)處理、化學氣相沉積(CVD)處理、低壓化學氣相沉積(LPCVD)處理、或電漿增強化學氣相沉積(PECVD)處理。在一個範例中,使用相對低溫(例如,大約攝氏250度至攝氏350度)的PECVD處理來沉積封蓋層232。封蓋層232可具有約5 nm至約30 nm的厚度,例如約10 nm至約20 nm。在一個範例中,所沉積的封蓋層232具有約15 nm的厚度。第4(c)圖展示第2H圖中的基板狀態(亦即,在使用150Å的PECVD Si3
H4
密封空氣空隙間隔壁之後)。如可見,在使用Si3
H4
密封之後未觀察到空氣空隙窄化。第4(c)圖也確認使用本揭示案的實作而形成的空氣空隙間隔壁為無殘留且高均勻性的。
在方塊120之後,基板200可經受完成電晶體所需的額外處理。例如,磊晶薄膜可成長超過每一鰭結構202的側壁以形成用於多鰭FinFET電晶體的源極及汲極區域。思量一些可能的結構修改。例如,在方塊104及方塊106之間,可形成犧牲閘極結構覆於一個或更多個鰭結構202。可在跨界一個或更多個鰭結構202的位置處形成犧牲閘極結構。犧牲閘極結構可自基板200突出,成為第二鰭而覆蓋一個或更多個鰭結構202。可形成溝槽進入犧牲閘極結構且使用FinFET電晶體可需要的金屬、閘極介電材料或高k閘極介電材料來充填。第二鰭可經配置以控制一個或更多個鰭結構內設置的通道區域內的電荷載子的流動。
前述提出幾個實作的綱要特徵,使得熟習該項技術者可更佳地理解本揭示案的態樣。使得熟習該項技術者應了解可易於使用本揭示案為基礎以修改其它處理及結構,以達成所需電晶體。思量本揭示案的實作可應用至FinFET整合處理流程技術及未來的環繞式閘極(gate-all-around)電晶體。
本揭示案的益處包含使用氧化鋁基材料或氮化鈦基材料為犧牲材料以形成空氣空隙間隔壁。所選擇的材料展示對Si3
N4
、SiO2
、及poly-Si優異的蝕刻選擇性,且可成功移除而不發生角落侵蝕,即使在78%間隔壁過度蝕刻之後。在使用Si3
N4
密封及後續高溫退火處理之後,未觀察到後續空氣空隙窄化。已證實本揭示案的方式能夠產生4 nm或更多的一致性及沿著鰭結構具有10:1長寬比而無殘留的均勻空氣空隙間隔壁。已觀察到:相較於由其他傳統材料(例如,SiN、SiO2
、或poly-Si)形成的側壁間隔壁,閘極對源極/汲極接點插頭寄生電容減少了70%。
前述係本揭示案的實施例,可修改本揭示案的其他及進一步的實施例而不遠離其基本範圍。
100‧‧‧處理序列
102‧‧‧方塊
104‧‧‧方塊
106‧‧‧方塊
108‧‧‧方塊
110‧‧‧方塊
112‧‧‧方塊
114‧‧‧方塊
116‧‧‧方塊
118‧‧‧方塊
120‧‧‧方塊
200‧‧‧基板
202‧‧‧鰭結構
204‧‧‧溝槽
208‧‧‧絕緣體材料
218‧‧‧頂部表面
220‧‧‧頂部表面
222‧‧‧內絕緣層
224‧‧‧犧牲間隔壁層
224a‧‧‧頂部部分
226‧‧‧外絕緣層
228‧‧‧閘極材料
230‧‧‧空氣空隙
232‧‧‧封蓋層
可藉由參考描繪於所附圖式中的揭露的圖示性實施例而理解本揭示案的實施例(簡短總結如上且下方將更詳細論述)。然而,注意所附圖式僅圖示本揭示案典型的實施例,因此不考慮限制其範圍,因為本揭示案可允許其他等效實施例。
第1圖為用於形成多鰭FinFET電晶體的示範性處理序列。
第2A至2H圖根據第1圖的處理序列圖示製造的某些階段期間簡化的多鰭FinFET電晶體的透視視圖。
為了便於理解,儘可能使用相同元件符號,以標示圖式中共用的相同元件。圖式未依比例繪製且可為了清晰而簡化。思量一個實施例的元件及特徵可有利地併入其他實施例,而無須進一步敘述。
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Claims (20)
- 一種電晶體裝置,包括: 一三維鰭式結構,該三維鰭式結構自一基板的一表面突出,該三維鰭式結構包括一頂部表面及兩個相對側壁,且該三維鰭式結構的一部分被在該基板上形成的一介電層環繞;一第一絕緣層,該第一絕緣層在該介電層及該三維鰭式結構的該兩個相對側壁上形成;一犧牲間隔壁層,該犧牲間隔壁層在該第一絕緣層上形成,其中該犧牲間隔壁層包括一氧化鋁基材料或一氮化鈦基材料;及一第二絕緣層,該第二絕緣層在該犧牲間隔壁層上形成。
- 如請求項1所述之電晶體裝置,其中該氧化鋁基材料為氧化鋁(Al2 O3 )或氮氧化鋁(AlON)。
- 如請求項1所述之電晶體裝置,其中該氮化鈦基材料為氮化鈦(TiN)。
- 如請求項1所述之電晶體裝置,其中該犧牲間隔壁層具有約4 nm至約8 nm的一厚度。
- 如請求項1所述之電晶體裝置,其中該第一絕緣層具有約2 nm至約5 nm的一厚度,且該第二絕緣層具有約2 nm至約5 nm的一厚度。
- 如請求項1所述之電晶體裝置,其中該第一絕緣層及該第二絕緣層之每一者包括氮化矽(Si3 N4 )、二氧化矽(SiO2 )、氮氧化矽(SiON)、氧化鋁(Al2 O3 )、或氧化鉭(Ta2 O5 )。
- 如請求項1所述之電晶體裝置,其中該第一絕緣層及該第二絕緣層之每一者包括氮化矽(Si3 N4 )。
- 一種形成一電晶體裝置的方法,包括以下步驟: 在一基板上形成一三維鰭式結構,該三維鰭式結構包括一頂部表面及兩個相對側壁,且該三維鰭式結構的一部分被在該基板上形成的一介電層環繞;在該介電層、該三維鰭式結構的該頂部表面及該兩個相對側壁上形成一第一絕緣層;在該第一絕緣層上形成一犧牲間隔壁層,其中該犧牲間隔壁層包括一氧化鋁基材料或一氮化鈦基材料;使該犧牲間隔壁層經受一方向性蝕刻處理,以在該三維鰭式結構的該頂部表面處曝露該第一絕緣層;及在該第一絕緣層上該三維鰭式結構的該頂部表面處及該三維鰭式結構的該兩個相對側壁上的該犧牲間隔壁層形成一第二絕緣層。
- 如請求項8所述之方法,進一步包括以下步驟: 曝露該三維鰭式結構的該兩個相對側壁上的該犧牲間隔壁層的一頂部部分;及選擇性地移除該犧牲間隔壁層,以產生該第一絕緣層及該第二絕緣層之間的一空氣空隙間隔壁。
- 如請求項9所述之方法,其中選擇性地移除該犧牲間隔壁層之步驟係由以下方式來執行:將該基板沉浸在一水溶液中,由混和容積比約4:1的硫酸及一過氧化氫溶液來獲得該水溶液。
- 如請求項9所述之方法,其中選擇性地移除該犧牲間隔壁層之步驟係由以下方式來執行:將該基板曝露於一電漿,該電漿由氯化硼(BCl3 )或溴化氫(HBr)形成。
- 如請求項8所述之方法,其中使該犧牲間隔壁層經受一方向性蝕刻處理之步驟係由以下方式來執行:以一第一容量流速率流動氬(Ar)進入一電漿腔室及以一第二容量流速率流動氯化硼(BCl3 )進入該電漿腔室,且該第一容量流速率對該第二容量流速率的一比率為約1:10或更多。
- 如請求項8所述之方法,其中使該犧牲間隔壁層經受一方向性蝕刻處理之步驟包括以下步驟: 提供約0.028 W/cm2 至約0.056 W/cm2 的一偏壓功率至一基板支撐。
- 如請求項8所述之方法,其中該氧化鋁基材料為氧化鋁(Al2 O3 )或氮氧化鋁(AlON)。
- 如請求項8所述之方法,其中該氮化鈦基材料為氮化鈦(TiN)。
- 如請求項8所述之方法,其中該犧牲間隔壁層具有約4 nm至約8 nm的一厚度。
- 如請求項8所述之方法,其中該第一絕緣層具有約2 nm至約5 nm的一厚度,且該第二絕緣層具有約2 nm至約5 nm的一厚度。
- 如請求項8所述之方法,其中該第一絕緣層及該第二絕緣層之每一者包括氮化矽(Si3 N4 )、二氧化矽(SiO2 )、氮氧化矽(SiON)、氧化鋁(Al2 O3 )、或氧化鉭(Ta2 O5 )。
- 如請求項8所述之方法,其中該第一絕緣層及該第二絕緣層之每一者包括氮化矽(Si3 N4 )。
- 一種在一處理腔室中形成一電晶體裝置的方法,包括以下步驟: 在一基板上形成一三維鰭式結構,該三維鰭式結構包括一頂部表面及兩個相對側壁,且該三維鰭式結構的一部分被在該基板上形成的一介電層環繞;在該第一絕緣層及一第二絕緣層之間形成一犧牲間隔壁層,其中在該介電層及該三維鰭式結構的該頂部表面以及該兩個相對側壁上形成該第一絕緣層,其中該犧牲間隔壁層包括一氧化鋁基材料或一氮化鈦基材料,且空氣空隙間隔壁具有約4 nm或更多的一厚度;及藉由使用一感應性耦合電漿來選擇性地移除該犧牲間隔壁層,在該三維鰭式結構的該頂部表面處曝露該第一絕緣層,其中選擇性地移除該犧牲間隔壁層係由以下方式來執行:以一第一容量流速率流動氬(Ar)進入一電漿腔室及以一第二容量流速率流動氯化硼(BCl3 )進入該電漿腔室,且該第一容量流速率對該第二容量流速率的一比率為約1:10或更多,及應用約0.028 W/cm2 至約0.056 W/cm2 的一偏壓功率至一基板支撐,該基板設置於該基板支撐上;及藉由將該基板沉浸在一水溶液中來移除該犧牲間隔壁層,以產生該第一絕緣層及該第二絕緣層之間的一空氣空隙間隔壁,由混和容積比約4:1的硫酸及一過氧化氫溶液來獲得該水溶液。
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US15/490,593 US9960275B1 (en) | 2016-10-28 | 2017-04-18 | Method of fabricating air-gap spacer for N7/N5 finFET and beyond |
US15/490,593 | 2017-04-18 |
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US8519481B2 (en) * | 2009-10-14 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Voids in STI regions for forming bulk FinFETs |
US9953885B2 (en) | 2009-10-27 | 2018-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | STI shape near fin bottom of Si fin in bulk FinFET |
US8362572B2 (en) | 2010-02-09 | 2013-01-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Lower parasitic capacitance FinFET |
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US9252233B2 (en) | 2014-03-12 | 2016-02-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Air-gap offset spacer in FinFET structure |
US9391200B2 (en) * | 2014-06-18 | 2016-07-12 | Stmicroelectronics, Inc. | FinFETs having strained channels, and methods of fabricating finFETs having strained channels |
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