TWI609469B - 電力電子模組及其製法 - Google Patents

電力電子模組及其製法 Download PDF

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Publication number
TWI609469B
TWI609469B TW105105695A TW105105695A TWI609469B TW I609469 B TWI609469 B TW I609469B TW 105105695 A TW105105695 A TW 105105695A TW 105105695 A TW105105695 A TW 105105695A TW I609469 B TWI609469 B TW I609469B
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Taiwan
Prior art keywords
layer
carrier
semiconductor component
silver
palladium
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TW105105695A
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TW201644023A (zh
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Frank Kruger
Gerald Freise
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Heraeus Deutschland Gmbh & Co Kg
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    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

電力電子模組及其製法
本發明係有關於一種電力電子模組，其包含至少一半導體元件，特別是電力半導體元件，以及有至少一功能表面用於連接至該半導體元件的載體。本發明也有關於一種用於製造電力電子模組的方法。
在電力電子設備中，對應電力電子模組的需求持續增加。這主要牽涉電力電子模組應可靠地暴露於它的連續使用溫度或尖峰溫度。越來越多藉助於所謂的燒結銀漿(silver sinter paste)來完成使半導體元件，特別是電力半導體，連接至基板及/或導線架及/或DCB。在加高的溫度下，例如高於200℃，銀層對於氧的滲透率會高到基板的基本金屬化物可能發生氧化。基板大部份由銅製成。
由於基本金屬化物的氧化，鍍層從而半導體元件可能脫離基板。
本發明基於以下目標：陳述一種被進一步開發的電力電子模組，其中可能發生鍍層及/或半導體元件的不合 意脫離。此外，本發明基於以下目標：陳述一種用於製造電力電子模組的方法。
根據本發明，關於電力電子模組，是用請求項1的主題解決此目標，以及關於電力電子模組的製法，是用請求項9的主題解決。
本發明基於以下理念：陳述一種電力電子模組，其係包含至少一半導體元件，特別是電力半導體元件。此外，該電力電子模組包含有至少一功能表面用於間接連接至該半導體元件的一載體。
根據本發明，由鈀組成的一阻障層至少部份地直接或間接形成於該載體的功能表面上。該半導體元件用一層燒結銀漿與阻障層背離載體功能表面的側面直接或間接連接。
由於形成由鈀組成的阻障層或中間層，因此可形成銀的氧擴散阻障物。因此，可防止位於下面的載體材料氧化。阻障層或中間層構成氧滲透或氧擴散通過銀至載體之金屬化物的阻障物。結果，燒結銀漿或銀燒結層在載體上的黏性於電力電子模組的老化期間不會減弱。因此，可防止燒結銀漿或銀燒結層的脫離以及半導體元件因而與載體的脫離。
由鈀組成的阻障層可具有0.1微米至1.0微米的層厚，特別是0.3微米至0.7微米，特別是0.4微米至0.6微米。
在本發明的一具體實施例中，至少部份地施加的銀層可形成於、特別是以電鍍方式(galvanically)形成於阻障 層(亦即由鈀組成的阻障層)與該層燒結銀漿之間。
此銀層可具有0.1微米至5.0微米的層厚，特別是0.5微米至2.0微米。該銀層以提及的層厚電鍍沉積於由鈀組成的阻障層上為較佳。由鈀組成的阻障層也直接或間接電鍍沉積於載體的功能表面上為較佳。
在載體的功能表面與阻障層之間，可另外部份地形成一金屬層。該金屬層可具有0.025微米至3.0微米的層厚，特別是0.1微米至2.0微米。
該電力電子模組的載體也可稱為基板。例如，可為所謂的導線架。
該載體例如可由銅及/或銅合金及/或鎳形成。
在本發明的一特別較佳具體實施例中，在使半導體元件連接至載體期間，藉由暴露於壓力及/或暴露於熱形成一擴散層。此擴散層為鈀-銀擴散層。本發明電力電子模組的半導體元件用燒結銀漿直接或間接地施加至阻障層背離載體之功能表面的側面。將半導體元件施加或連接至載體的發生為燒結製程的一部份。由於在燒結製程中暴露於壓力及/或暴露於熱，在電力電子模組中形成鈀-銀擴散層。
特別是，阻障層的鈀擴散進入銀層及/或該層燒結銀漿。
該鈀-銀擴散層可具有5奈米至300奈米的層厚，特別是10奈米至200奈米。
該燒結銀漿為標準燒結銀漿。
此外，本發明基於以下理念：陳明一種用於製造電力電子模組的方法，特別是用於製造本發明電力電子模 組的方法。待製造電力電子模組包含至少一半導體元件，特別是電力半導體元件，以及有至少一功能表面用於連接至該半導體元件的一載體。
本發明方法的特徵在於以下方法步驟：a)將載體的功能表面至少部份地直接或間接鍍上、特別是以電鍍方式鍍上由鈀組成的阻障層；b)至少部份地施加一層燒結銀漿至半導體元件的一側面或直接至載體的阻障層或間接至載體的阻障層；c)用該層燒結銀漿通過暴露於熱，使半導體元件連接至載體。
因此，在第一步驟中，也可稱為基板或導線架的載體可至少部份地鍍上由鈀組成的阻障層。載體或基板或導線架可由，例如銅，所製成。由鈀組成的阻障層至少部份地施加至、特別是以電鍍方式施加至載體。在另一步驟中，一層燒結銀漿至少部份地施加至半導體元件或者是載體。該層燒結銀漿可用模版印刷法或噴塗法或分配法施加至半導體元件或載體。如果該層燒結銀漿施加至半導體元件，則該層燒結銀漿是要施加至半導體元件中隨後將會連接至載體的側面。
如果該層銀膠施加至載體，則該層燒結銀漿是要直接或間接地施加至載體的阻障層。半導體元件及載體必須彼此相對定位成半導體元件可用燒結銀漿層與載體的阻障層直接或間接地連接。半導體元件與載體藉助於燒結銀漿層的連接接著經受暴露於熱。連接也可稱為半導體元件 與載體的連結。
在本發明方法的另一具體實施例中，由鈀組成的阻障層可能在與半導體元件連接之前至少部份地鍍上銀層。用電鍍沉積完成阻障層至少部份地鍍上銀層為較佳。
在步驟a)之前，亦即在由鈀組成的阻障層鍍上、特別是以電鍍方式鍍上載體的功能表面之前，載體的功能表面可至少部份地鍍上鎳層。在載體由銅或銅合金組成時，鎳層主要施加至載體，特別是載體的功能表面。
在步驟c)，亦即在使半導體元件連接至載體期間，可執行暴露於壓力的步驟。
接著是，鈀-銀擴散層的形成係藉由在使半導體元件連接至載體期間暴露於壓力及/或暴露於熱。換言之，由於在使半導體元件連接或連結至載體期間暴露於壓力及/或暴露於熱，在電力電子模組中形成一鈀-銀擴散層。這是在阻障層的鈀擴散進入銀層或燒結銀漿層時發生。
由於此一鈀-銀擴散層，形成用於氧滲透或氧擴散通過銀層或燒結銀漿層至載體之基本金屬化物的有效阻障物。從而防止諸層氧化。銀燒結層從而半導體元件在整個生命週期黏附至載體。
10‧‧‧電力電子模組
11‧‧‧半導體元件
12‧‧‧載體
13‧‧‧功能表面
14‧‧‧鎳層
15‧‧‧阻障層
16‧‧‧側面阻障層
17‧‧‧銀層
18‧‧‧側面銀層
19‧‧‧燒結銀漿層
20‧‧‧側面半導體元件
21‧‧‧鈀-銀擴散層
d1‧‧‧鎳層厚度
d2‧‧‧阻障層厚度
d3‧‧‧銀層厚度
d4‧‧‧鈀-銀擴散層厚度
以下用有參考示意附圖之其他細節的示範具體實施例更詳細地解釋本發明。
其中：圖1圖示根據第一具體實施例的本發明電力電子模 組；以及圖2圖示有成形鈀-銀擴散層的本發明電力電子模組。
以下相同的部件及有相同效果的部件用相同的元件符號表示。
圖1圖示本發明電力電子模組10的構造。
該模組包含半導體元件11。特別是，此半導體元件11可為電力半導體元件。此外，電力電子模組10包含載體12。例如，載體12為由銅材料形成的導線架。載體12包含用來間接連接至半導體元件11的功能表面13。
金屬層(如，鎳層14)施加至載體12的功能表面13。鎳層14的層厚d1例如可為0.05微米至3.0微米。
在鎳層14上至少部份地形成由鈀組成的阻障層15。換言之，由鈀組成的阻障層15間接形成於載體12之功能表面13上。由鈀組成的阻障層15可具有0.1微米至0.5微米的層厚d2。在阻障層15上，亦即阻障層15中之背離載體12之功能表面13的側面16上，所施加的銀層17、特別是以電鍍方式施加的銀層17係至少部份地形成。銀層17可具有0.5微米至2.0微米的層厚d3。
在銀層17背離載體12之功能表面13或阻障層15的側面18上，至少部份地形成燒結銀漿層19。燒結銀漿層19用來使半導體元件11連接至載體12。
圖1圖示半導體11已經連結至載體12的狀態。在連結前，燒結銀漿層19可施加至銀層17的任一側面18使得 半導體元件11用面向載體12的側面20附著至燒結銀漿層19。
替換地，可提供燒結銀漿層19初始施加至半導體元件11的側面20。這接著是使設有燒結銀漿的半導體元件11連結至載體12。
由圖1顯而易見，燒結銀漿層19與阻障層15背離載體12之功能表面13的側面16間接連接。
為了用燒結銀漿層19使半導體元件11連接至載體12，執行燒結製程。這伴隨著暴露於壓力及/或暴露於熱。這意謂，至少在用於使半導體元件黏著在其下面之諸層的輕微壓力在半導體元件11及載體12上或在位於載體材料12與半導體元件11之間的層14、15、17及19上產生時，同時發生暴露於熱。
如圖2所示，阻障層15的鈀擴散進入銀層17的銀藉此形成鈀-銀擴散層21。此鈀-銀擴散層21形成氧滲透或氧擴散通過燒結銀漿層19及銀層17至載體12之金屬的阻障物。從而防止載體金屬化物氧化。結果，銀層17或燒結銀漿層19不會脫離載體12或鎳層14，甚至在電力電子模組10暴露於較高的溫度下。
鈀-銀擴散層21的層厚d4可為5奈米至300奈米，特別是10奈米至200奈米。
例如，測試顯示銀層17或燒結銀漿層19不會脫離阻障層15，甚至在暴露於245℃的溫度超過690小時之後。
在此指出與圖1及2之具體實施例有關的所有上 述元件及組件被宣稱為對於本發明從本身看來或在任何組合下有實質性，特別是圖示於附圖的細節。
10‧‧‧電力電子模組
11‧‧‧半導體元件
12‧‧‧載體
13‧‧‧功能表面
14‧‧‧鎳層
15‧‧‧阻障層
16‧‧‧側面阻障層
17‧‧‧銀層
18‧‧‧側面銀層
19‧‧‧燒結銀漿層
20‧‧‧側面半導體元件
d1‧‧‧鎳層厚度
d2‧‧‧阻障層厚度
d3‧‧‧銀層厚度

Claims (11)

  1. 一種電力電子模組，其係包含至少一半導體元件，特別是電力半導體元件，以及有至少一功能表面用於間接連接至該半導體元件的一載體，其特徵在於：在該載體之該功能表面上至少部份地直接或間接形成有由鈀組成的一阻障層，以及該半導體元件用由一燒結銀漿組成的一燒結銀漿層直接或間接地被連接至該阻障層中之背離該載體之該功能表面的側面，以及一鈀-銀擴散層係藉由在使該半導體元件連接至該載體期間暴露於壓力及/或暴露於熱而形成。
  2. 如請求項1所述之電力電子模組，其特徵在於：該阻障層有0.5微米至1.0微米、特別是0.3微米至0.7微米、特別是0.4微米至0.6微米的層厚。
  3. 如請求項1或2所述之電力電子模組，其特徵在於：在該阻障層與該燒結銀漿層之間所施加的一銀層、特別是以電鍍方式(galvanically)施加的一銀層係至少部份地形成。
  4. 如請求項3所述之電力電子模組，其特徵在於：該銀層有0.1微米至5.0微米、特別是0.5微米至2.0微米的層厚。
  5. 如請求項1或2所述的電力電子模組，其特徵在於：在該載體之該功能表面與該阻障層之間至少部份地形成有一鎳層。
  6. 如請求項5所述之電力電子模組，其特徵在於：該鎳層有 0.05微米至3.0微米、特別是0.1微米至2.0微米的層厚。
  7. 如請求項1或2所述的電力電子模組，其特徵在於：該載體係由銅及/或一銅合金及/或鎳形成。
  8. 如請求項1所述之電力電子模組，其特徵在於：該鈀-銀擴散層有5奈米至300奈米、特別是10奈米至200奈米的層厚。
  9. 一種用於製造電力電子模組的方法，特別是如請求項1至8中之任一項所述的電力電子模組，其係包含至少一半導體元件，特別是電力半導體元件，以及有至少一功能表面用於與該半導體元件間接連接的一載體，其特徵在於以下步驟：a)將該載體之該功能表面至少部份地直接或間接鍍上、特別是以電鍍方式鍍上由鈀組成的一阻障層；b)施加一燒結銀漿層至該半導體元件的一側面、或直接至該載體之該阻障層、或間接地於該載體之該阻障層上；c)用該燒結銀漿層，通過暴露於壓力及/或暴露於熱，來使該半導體元件連接至該載體，以及d)在使該半導體元件連接至該載體期間，藉由暴露於壓力及/或暴露於熱，來形成一鈀-銀擴散層。
  10. 如請求項9所述之方法，其特徵在於：該阻障層在與該半導體元件連接之前係至少部份地鍍上一銀層。
  11. 如請求項9或10所述之方法，其特徵在於：該載體之該功能表面在該步驟a)之前係至少部份地鍍上一鎳層。
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