CN101996897A - 用于制造电路基板组件以及功率电子模块的方法 - Google Patents

用于制造电路基板组件以及功率电子模块的方法 Download PDF

Info

Publication number
CN101996897A
CN101996897A CN2010102853797A CN201010285379A CN101996897A CN 101996897 A CN101996897 A CN 101996897A CN 2010102853797 A CN2010102853797 A CN 2010102853797A CN 201010285379 A CN201010285379 A CN 201010285379A CN 101996897 A CN101996897 A CN 101996897A
Authority
CN
China
Prior art keywords
anchoring structure
metallization layer
pillar
bottom metallization
metal surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010102853797A
Other languages
English (en)
Other versions
CN101996897B (zh
Inventor
O·霍尔费尔德
J·格利希
R·巴耶勒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN101996897A publication Critical patent/CN101996897A/zh
Application granted granted Critical
Publication of CN101996897B publication Critical patent/CN101996897B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203Cooling of mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0058Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4846Connecting portions with multiple bonds on the same bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/8484Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/8485Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/858Bonding techniques
    • H01L2224/8584Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12043Photo diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • H01L2924/13034Silicon Controlled Rectifier [SCR]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13062Junction field-effect transistor [JFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/207Diameter ranges
    • H01L2924/2076Diameter ranges equal to or larger than 100 microns
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0373Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

用于制造电路基板组件以及功率电子模块的方法。本发明涉及通过提供具有金属表面的电路基板和绝缘基板制造功率半导体模块的方法,绝缘基板包括具有被提供有底部金属化层的底部侧的绝缘载体。此外,提供包括多个长方形支柱的锚定结构,每个支柱具有背对绝缘载体的第一端,所述支柱的至少一个子集被分布在整个锚定结构的上方,针对该子集中的每个支柱适用下述:从该支柱的侧壁,没有或最多有三个细长的结合连接板均延伸至另一个支柱的侧壁,在这里所述结合连接板与所述另一个支柱的侧壁结合。锚定结构被定位在绝缘载体和金属表面之间,之后金属表面借助于焊料被焊接到底部金属化层和锚定结构,使用焊料塞满金属表面和底部金属化层之间的所有间隙。

Description

用于制造电路基板组件以及功率电子模块的方法
技术领域
本发明涉及电路基板组件。
背景技术
电路基板组件被广泛用在例如功率电子模块(PEM)中。功率电子模块是用在功率电子电路中的半导体模块。功率电子模块通常用在车辆、铁路和工业应用中,例如用在反相器或整流器中。人们同样发现能量产生和传输形式的应用。包含在功率电子模块中的半导体部件可包括例如半导体芯片,其包括绝缘栅(IGBT)或金属氧化物场效应晶体管(MOSFET)。这些IGBT和MOSFET半导体芯片随着其电压和电流处理能力改变。一些功率电子模块也在半导体组件中包括附加半导体二极管(即续流二极管)用于过电压保护。这种半导体芯片同样可包括闸流晶体管、二极管或任何其他功率部件。
为了安装半导体芯片并将其接成电路,采用在一侧或两侧上被金属化的平面陶瓷基绝缘基板。与在几毫米厚的主要是金属的电路基板上安装半导体芯片相比,将其安装在这种绝缘基板上具有以下优点:由于和金属相比,陶瓷热膨胀系数与半导体芯片热膨胀系数较小不同(近似为2ppm),因此对于温度变化能获得相对良好的稳定性。其他优点包括陶瓷的介电强度以及良好的导热率。
但是,陶瓷的导热率低于金属的导热率。这就是争取相对薄的陶瓷基绝缘基板的原因,但是其机械弯曲负载能力低。由此这种陶瓷基绝缘基板通常安装在坚固耐用的底板(例如铜或铝基金属板)上。
本发明的一个方面是提供一种用于制造包括结合到陶瓷基板的金属底板的电路基板组件的方法,所述陶瓷基板对于温度变化是稳定的。另一个方面是提供一种用于制造包括这种电路基板组件的功率半导体模块的方法。
发明内容
在一种用于制造基板组件的方法中,提供金属化电路基板,绝缘基板和锚定结构。绝缘基板具有具有底部金属化物的绝缘体。该锚定结构具有多个长方形支柱,所述支柱包括背对绝缘体的第一端,这些长方形支柱中的至少一个子集分布在整个锚定结构上方。此外,该长方形支柱子集中的每一个不具有或最多具有三个从侧壁突出的长方形连接板,并且每一个连接板向着另一个长方形支柱的侧壁延伸,在这里所述连接板与所述另一个长方形支柱的侧壁连接。在变得可用之后,锚定结构被定位在绝缘体和金属化物之间,之后借助于焊料将金属表面结合到底部金属化物和锚定结构,使用焊料塞满金属表面和底部金属化物之间的所有间隙。
锚定结构包括分布于锚定结构上的呈规则或不规则间隔的多个细长支柱。该锚定结构集成在电路基板之间的目前为止通常为柔软的焊料层中,并且可在例如绝缘体和电路基板的金属表面之间,然后借助焊料将该金属表面结合到金属化物以及锚定结构。
锚定结构的功能是将机械应力分布在焊料层的整个厚度上方。对于金属化物的几何形状,在所有情况下(半导体组件、电路基板尺寸、底板的形状和材料),优化锚定结构以使机械应力相应地分布和降低。为了避免在锚定结构间隙中的针孔,优选真空焊接。优选地,具有顶部金属化物的基板利用功率半导体构造且然后被焊接到底板。通过将锚定结构构造成与金属化物是一体的,其可以是金属化物的部件或者与其无关,或者其可以是与之后被结合到金属化物的与金属化物无关的元件。
通过对邻接支柱的侧表面不使用隆起部或者最大仅使用三个隆起部,使用在其侧表面之间连接的多个细长支柱,如本发明中采用的锚定结构与从US12/059,188和DE10 2009 002 065中获知的密封结构相比,具有更高的横向柔性,即,当其被施加热机械应力时所述支柱在横向表现出相对支柱纵向的高度柔性。这也特别适用于在将底部基板金属化物焊接到电路基板的金属表面之后。
由于在结合绝缘体到电路基板(例如底板)时在底部金属化物和焊料之间的界面发生机械应力,即,这里热机械应力是最大的,当连接绝缘体的锚定结构的强度高于常规柔软焊料的强度时是有利的。例如通过借助允许形成金属间相的焊料薄层焊接最初与底部基板金属化物无关的锚定结构到底部基板金属化物,可以实现锚定结构至绝缘体的这种高强度结合。另一种可能是借助于低温接合技术(LTJT)结合最初与底部基板金属化物无关的锚定结构到底部基板金属化物。
再一种以高强度将锚定结构结合到绝缘体的可能性是,例如通过压印或蚀刻产生相同材料的一体的锚定结构和底部基板金属化物。
在锚定结构和电路基板金属表面之间的界面处,不需要以高强度结合锚定结构,这是因为该位置不暴露到任何热触发的膨胀差。
使用用于制造功率半导体模块的方法制造一个这种电路基板组件,从而绝缘体在与其底部侧相对的顶部上通过金属化物安装至少一个功率半导体芯片。此外,制造了容纳功率半导体芯片和绝缘体的模块封装,其中电路基板形成用于功率半导体模块的底板。
附图说明
通过参考以下附图和说明可更好地理解本发明。在图中的部件不必按尺寸画出,而是强调描述本发明的原理。而且,在图中,类似的参考数字表示相应部分。在图中:
图1是包括陶瓷基板通过具有多个长方形支柱的锚定结构固定至其的金属板的组件的垂直截面图;
图2是通过图1中所示陶瓷基板的底部金属化物和在将陶瓷基板焊接到金属板上之前固定至其的锚定结构的垂直截面图;
图3是如图2中所示但是锚定结构经历了横断应力的组件的图;
图4是不同于图2中所示的组件的垂直截面图,其中不同之处在于截面图的底部金属化物现在被构型为与锚定结构是一体的;
图5是不同于图4中所示的组件的垂直截面图,其中不同之处在于现在支柱向着其自由端成锥状;
图6是不同于图5中所示的组件的垂直截面图,其中不同之处在于现在陶瓷基板的底部金属化物被构型为与锚定结构是一体的;
图7是图1中所示组件的制造步骤的图示,但是示出了设置在金属化的陶瓷基板和金属板之间的锚定结构,以及设置在锚定结构和金属板之间的预先制造的焊料垫;
图8是图7中所示组件的垂直截面图,但是是在将陶瓷基板焊接到金属板的锚定结构之后;
图9是图8中所示组件的边缘部分的放大细节图;
图10是结合到绝缘体的锚定结构的水平截面图;
图11是图10中所示组件的放大细节图;
图12是结合到绝缘体的另一锚定结构的水平截面图;
图13是图12中所示的组件的放大细节图;
图14是结合到绝缘体的另一锚定结构的水平截面图;
图15是图4中所示提供有锚定结构的陶瓷基板底部侧的自顶向下的图;
图16是提供有具有倾斜拐角的锚定结构的另一陶瓷基板底部侧的自顶向下的图;
图17是如图2中所示提供的再一陶瓷基板底部侧的自顶向下的图,其中现在锚定结构仅沿着陶瓷基板边缘部分布设;
图18是提供有纵向肋状物的陶瓷基板底部侧的自顶向下的图;
图19是包括将结合线部分结合至其以形成锚定结构的金属化物的陶瓷基板的透视图;
图20是如图19中所示陶瓷基板的一部分的垂直截面图;
图21是借助于结合技术制造的锚定结构的替换方面的垂直截面图;
图22是借助于公共前导结构将相互间隔的几个截面结合至其的金属板的透视图;
图23是其中锚定结构包括杆状支柱的组件的一部分的垂直截面图,其中杆状支柱具有设置成嵌套在构造在电路基板中的相应凹穴内的自由端;
图24是提供有锚定结构的一部分绝缘体的透视图,在锚定结构中两个相邻正方形截面支柱借助于连接板(web)接合;
图25是与图24中所示相对应的组件图,除了代替具有正方形截面的支柱,现在其具有圆形截面;
图26是与图24中所示相对应的组件图,除了连接板与支柱的两个边缘间隔开以外;
图27是与图24和26中所示相对应的组件图,除了现在连接板被设置成与背对绝缘体的支柱侧一致;
图28是包括结合了绝缘体的电路基板的功率半导体模块的垂直截面图,其底部金属化物被结合到金属底板上,锚定结构被设置在绝缘体和底板之间;和
图29是与图26中所示功率半导体模块相同的功率半导体模块的垂直截面图,除了现在将锚定结构设置成仅位于功率半导体芯片的下方以外。
在下面的详细描述中,参考附图,这些附图构成了说明书的一部分,在这些图中借助图示示出了可以实施本发明的特定实施例。在这方面,方向性的术语,例如:“顶部”、“底部”、“前”、“后”、“超前”、“拖尾”等等,是参考所描述的图的方向来使用的。由于本发明的实施例的部件可被定位在许多不同的方向上,因此方向性的术语仅用于说明的目的,并且决不是用于限制。应当理解也可以利用其它实施例,并且可以在不脱离本发明的范围的情况下做出结构或逻辑改变。因此,下面的详细描述不是在限制的意义上进行的,并且本发明的范围将由所附权利要求来限定。应当理解,在此描述的各示范性实施例的特征可相互组合,除非另外具体说明。
具体实施方式
现在参考图1,示出了包括借助于锚定结构3焊接到金属电路基板1(诸如金属板或热沉)的绝缘基板2的组件的垂直截面图。为此,金属基板1可包括被构造成平坦或凹入的金属表面1t。当将电路基板构造成用于功率半导体模块的金属底板时,甚至底板很轻微突起的弯曲都用于施加注入的热化合物以将接触压力更均匀地扩展到热沉上,从而最小化当将热沉安装到底板上时的传热阻力。代替单纯的金属基板1,可采用任何其他类型的电路基板,当其包括可焊接表面金属化物时在至少一侧被焊接到绝缘基板2。在将电路基板构造成热沉的情况下,其可具有冷却翼片和/或用于容纳液体冷却剂的冷却通路。可能的冷却方法包括流体冷却,例如利用空气或液体冷却剂,或者蒸发冷却。电路基板1也可由具有良好导热性的材料制成,诸如铜或铝或者具有这些金属中的至少一种的合金或者包括该合金的一种这种金属。
绝缘基板2包括绝缘载体20,其被构造为在其标记为顶部侧20t的一侧由顶部金属化层22作为顶部和在其标记为底部侧20b的相反侧由底部金属化层21作为底部的焊垫。顶部金属化层22被图形化成迹线和/或焊垫,将一个或多个电子部件诸如功率半导体芯片固定至所述迹线和/或焊垫从而固定到绝缘基板2上可应用互连的位置。底部金属化层21被构造为非图形化金属化层,但是适用时也可将其图形化。
金属化层21和22分别稳固地结合到绝缘载体20的底部侧20b和顶部侧20t,绝缘载体20例如为适当的陶瓷材料,诸如氮化铝(AlN)、氧化铝(Al2O3)、氮化硅(Si3N4)、碳化硅(SiC)或者氧化铍(BeO)。金属化层21和22由铜制成。绝缘基板2例如是直接铜结合(DBS)基板或者是活性金属钎焊(AMB)基板。
任选地,金属化层21和/或22和/或锚定结构3可进一步涂敷有材料银、NiAu、NiPd、NiPdAu以制造可焊接表面或者便于以NTV作为芯片顶部。电路基板1的接触表面区域1t可电镀有镍、银、金、钯或铜及其组合中的至少一种材料的另一涂层,从而制造可焊接表面。这些涂层例如可通过电镀、溅射或者汽相沉积形成。如果锚定结构3被单独包括在焊料4中,则底部金属化层21在其背对绝缘载体20的一侧和/或在面对绝缘载体20的锚定结构3的一侧必须具有薄(sheer)铜表面,从而可以在焊接期间在锚定结构3和底部金属化层21之间形成Sn和Cu的合金,以格外坚固地结合锚定结构3和底部金属化层21。该合金必须至少被构造在锚定结构3和底部金属化层21之间整个长度垂直的部分区域中。任选地或者替换地,代替两个表面将被焊接到一起作为薄铜层,一个表面可以是被涂敷以形成Sn-Cu的银,Sn-Cu-Ag和/或SnAg合金也能产生相同效果。
锚定结构3包括构造在多个长方形支柱31之间的间隙5,且在将锚定结构3焊接到电路基板1上之前其不含有固态材料。长方形支柱31和间隙5分布在整个锚定结构3上。
为了焊接绝缘基板2和锚定结构3到电路基板1上,使用在焊接期间熔化从而进入并塞满间隙5的焊料4。为了最小化针孔,使用真空焊接工艺。无针孔焊接与不使用锚定结构的焊接类似,必须确保完全包容热阻。加热焊料4所至的焊接温度范围例如可从240℃至400℃,例如在260℃,330℃或350℃。
在该设置中,所使用的焊料量稍多于完全塞满所有间隙5所需的体积。这避免了在电路基板1的锚定结构3和金属表面1t之间形成间隔,不必很大但仍足以补偿关于被焊接部件的厚度和不规则的容限。使用如参考图7所说明的方法和如在焊接过程中说明的表面质量,单独包括的锚定结构导致焊料通过毛细管作用流动穿过面对锚定结构3的底部金属化层21的底部侧和面对锚定结构3的锚定结构3顶表面之间的孔隙,从而被转换成孔隙区域中薄的合金层。
此外,锚定结构3通过在焊料中的垂直分布用于吸收焊料4中的热机械应力,由此通过与常规焊料结合中一样强的不再聚集在焊料层拐角区域中的界面处的力,防止焊料4特别是在底部金属化层21的底部侧和焊料之间的界面处发生分离。
现在参考图2,示出了从如图1中所示的绝缘基板2的拐角部分和固定到所述底部金属化层21的锚定结构3的垂直截面的放大细节图,也就是在图1中所示的将绝缘基板2焊接到电路基板1上之前。每一个支柱31都在纵向中心线v上与绝缘载体20的底部侧20b成直角延伸(见图中的电路基板1)。在其纵向中心线v上,支柱31长度l31范围例如从200μm至5mm,与锚定结构3的高度h3相同,以及范围例如从350μm至1mm的宽度或直径宽度b31垂直于其纵向中心线v,即平行于绝缘载体20的底部侧20b。支柱31此外还具有在平行于绝缘载体20的底部侧20b的至少一个方向上的重复间隔(周期性)dp,其范围例如从200μm至10mm。在该设置中,由于实现了焊料中机械应力的最佳分配,据此支柱31的间隔仅取决于其关于纵横比的制造限制,因此争取了最大化所述高度和最小化支柱31的直径。在本发明的所有实施例中,锚定结构3可包括至少在底部金属化层21拐角区域中和/或沿着底部金属化层21侧边缘的支柱31。
现在参考图3,示意性示出了当支柱31受到以直角作用在纵向中心线v上的力F时,支柱31怎样向旁边弯曲。
每一个支柱31都包括在纵向中心线v上相互间隔开的两端311和312。当端311是自由端时,端312稳固地结合到底部金属化层21。适合于在锚定结构3和底部金属化层21之间制造结合的结合技术包括例如通过将银焊膏施加到底部金属化层21和/或锚定结构3上,并在温度/压力工艺中将其结合的最大400℃温度下的焊接或者最大230℃的压力烧结。在焊料结合中,完成的焊料层可主要包括至少一个金属间相和完全在锚定结构3和完全由至少一种金属间相构成的底部金属化层21之间延伸的部分。在底部金属化层21和锚定结构3之间,这种焊料层也包括完全为合金部分的绝缘基板,其厚度例如为2μm至30μm。
然后将底部金属化层21和锚定结构3压合到一起。之后可将连接到锚定结构3的绝缘基板2焊接到电路基板1,即首先独立于底部金属化层21来制造锚定结构3。在结合底部金属化层21之前,为了利于控制独立的锚定结构3,通过连接相对于纵向中心线v横向取向的连接板,有利的是互连各长方形支柱31(图1至3中存在但未示出)。优选结合连接板不象支柱31那样高且尽可能将其构造为弹性的,以使接合支柱31之间的机械耦合不会过度。
现在参考图4,示出了替换方面中锚定结构3怎样通过由在其背对绝缘载体20的一侧图形化已经结合到绝缘载体20(如图1中示出)的顶部侧20t的底部金属化层21产生的锚定结构3将被构造成与电路基板的底部金属化层21是一体的。适合于实现该目的的方式例如是掩模蚀刻背对绝缘载体20的底部金属化层21的一侧。
可完成蚀刻制造锚定结构3,例如使得恒定厚度范围例如从400μm至1mm的金属层被施加到绝缘载体20的平坦底部侧20b,之后通过掩模蚀刻凹穴形成锚定结构3,其深度可例如在200μm和700μm之间变化。当结果为该锚定结构3中具有长方形支柱31时,其长度l31与蚀刻深度相同。根据一个实例,被蚀刻之前的金属层具有600μm的恒定厚度,同时支柱31的长度l31通过300μm的蚀刻量获得。由于蚀刻同时影响纵向和横向,在通过蚀刻支柱31之间的间隔制造的锚定结构可超过支柱31长度(蚀刻深度)的两倍。
作为替换方式,其底部金属化层21被构造成与锚定结构3一体的电路基板可被制造成其用于构造绝缘基板2的金属化膜的两个平坦主表面区域中的一个被图形化,且之后该金属化膜通过其未图形化的主表面区域结合至绝缘载体20的底部侧20b。此时金属化膜形成包括锚定结构3的底部金属化层21。最初与绝缘载体20无关的图形化金属化膜例如通过掩模蚀刻和/或压印和/或冲压实现。
现在参考图5,与图4中示出的圆柱形支柱31不同,其示出了锚定结构3的长方形支柱31现在向其自由端311的方向成锥形,即,支柱31的截面区域在自由端311的方向上从端312单一缩小或精确地单一缩小。同时,如图5所示设置中的锚定结构3被构造成与底部金属化层21是一体的,在如图6所示设置中,在制造之后,其被结合到底部金属化层21,如已经参考图1至3说明的。
现在参考图7,示出了使用最初与绝缘基板2无关的锚定结构3制造在绝缘基板2和电路基板1(诸如用于功率半导体模块的金属底板)之间的焊料结合的方法。在该设置中,在焊料4被设置在锚定结构3和金属表面1t之间之后,锚定结构3被设置在绝缘基板2的底部金属化层21和电路基板1的金属表面1t之间。可施加焊料例如作为整个厚度范围从50μm至300μm的焊料焊垫至金属表面1t和/或面对金属表面1t的锚定结构3的底部侧,或者其可位于金属表面1t的顶部作为预先制造的焊料焊垫。通常,该厚度是塞满锚定结构3中的间隙所需的焊料体积的函数。在将绝缘基板2和锚定结构3焊接到电路基板1的金属表面1t时,使用毛细管作用能促使熔化的焊料进入到锚定结构3中从而用焊料完全塞满它。通常,所施加的焊料或者焊料焊垫的厚度被定标成使得有余量地塞满间隙,该余量在焊接期间用掉。由此,绝缘基板2、锚定结构3、焊料4和电路基板1每一个在焊接过程中都被压向另外一个,该焊接过程中焊料4被熔化。该熔化的焊料4从下被推到间隙5中和锚定结构3顶部和绝缘基板2的底部金属化层21之间的细小孔隙(这里完全存在这种孔隙)中将它们完全塞满。一旦焊料4被固化,其与绝缘基板2、锚定结构3和电路基板1一起形成固体复合结构,其不受温度变化影响。可通过将间隙5的宽度选择为小到熔化的焊料4通过毛细管作用渗入到间隙5中从而将焊料塞满在间隙5中。为此,每个间隙5都可包括例如在平行于绝缘载体20的底部侧20b的方向上小于500μm的宽度。
除非锚定结构3未被构造成与绝缘基板2的底部金属化层21一体,否则毛细管作用任何情况下对于面对绝缘载体20的锚定结构3的顶部和面对锚定结构的底部金属化层21的底部之间的孔隙是有效的,这是因为由于将绝缘基板2、锚定结构3和电路基板1压合在一起导致该孔隙非常细小。在焊接期间该非常细小的孔隙可以构造高强度金属间相,由此包括锚定结构3和底部金属化层21之间的非常稳固的结合。
任选地,在制造绝缘基板2和电路基板1之间的焊料结合之前,锚定结构3可例如通过利用焊料进行电镀而被表面化,由此底部金属化层21的厚度可在例如5μm和500μm之间。
以相同的方式,可制造其中在将绝缘基板2焊接到电路基板1上之前,锚定结构3已经稳固结合到底部金属化层21的组件,或者可将锚定结构3构造成与底部金属化层21是一体的。
不管如何构造,在将电路基板1焊接到底部金属化层21上之前,锚定结构3可在超出350℃的温度下回火,以利于补偿由于在底部金属化层21和电路基板1之间的已完成结合层中的机械应力导致的锚定结构3的任何变形。
现在参考图8,示出了在将绝缘基板2焊接到电路基板1之后的组件。于图9中示出了该组件边缘部分的放大细节。
根据本发明的另一方面,锚定结构3的密度、分布和几何形状被设置成使得与绝缘载体20的底部侧20b平行的截面平面E-E’(见图9)中的锚定结构3包括总共为结合到绝缘载体20的底部金属化层21的表面的表面面积的至少10%和/或最大70%的截面面积。
现在参考图10,示出了在对应于图9中所示的E-E’截面平面中,向绝缘载体20的底部侧20b看,结合到绝缘载体20的锚定结构3的水平截面图,同时图11是该组件放大细节图。从图10很明显看出,锚定结构3可在整个底部金属化层21上延伸。
现在再次参考图10和11,其示出了已经说明的结合连接板32怎样被构造在长方形支柱31之间。这些支柱31包括宽度b31,连接板32包括宽度b32,和长度l32,从而各个支柱31的宽度b31可都相同或不同。相应地,各个连接板32的宽度b32可相同或不同和/或其长度l32可相同或不同。该设置中,任选地,结合到底部金属化层21的每个连接板32的宽度b32可小于相应支柱31的宽度b31。
任选地,所有或者至少多个长方形支柱31均可通过确切的四个结合连接板32或者确切的三个结合连接板32或者确切的两个结合连接板32或者确切的单个结合连接板32结合到一个或多个邻接长方形支柱31。将支柱31和结合连接板32结合导致形成便于控制的一体单元(one-part unit)的锚定结构3。当不是在首先将锚定结构3制造出来之前将锚定结构3结合到绝缘基板2的底部金属化层21上时,这是特别有利的。在图10和11中示出的锚定结构3中,长方形支柱31具有正方形截面。如借助于实例示出的,支柱31可设置成行和/或列,从而可交错设置邻接行和/或邻接列。除此之外,结合连接板32可被构造成直的连接板。
现在参考图12,以及示出了放大细节图的图13,其示出该组件中的支柱31如何也可包括例如矩形截面区域。如从该实例中明显看出的,每一个结合连接板32也可包括两个或更多个直部,它们与绝缘载体20的底部侧20b平行且相互以除了0°和180°之外的角度取向。
根据图14中所示的另一结构,支柱31可被形成为圆柱状并且包括圆形截面区域。在该设置中,锚定结构3可包括子结构,其中支柱31与设置在其间的纵向连接板33一起形成带状体。锚定结构3在该设置中通过借助于连接板32结合几个这种带状体而成形。
在所示结构的分离图中,支柱31也可包括除了正方形、矩形或圆形之外的截面区域,例如六边形、椭圆形或三角形。实际上,截面区域可采用任何形状。此外,可采用不同形状的支柱31在锚定结构3中相互组合。
现在参考图15,示出了提供有如图4中所示锚定结构3的绝缘基板2的底部侧20b的自顶向下的图。支柱31在垂直于支柱31的纵向中心线的方向上分布在整个底部金属化层21上,这同样适用于图16中所示的组件,但是其中,绝缘基板2的拐角是倾斜的,其结果是减小了通常在绝缘基板2拐角区域发生的热机械应力。
现在参考图17,示出了绝缘基板2怎样也包括倾斜拐角,其中,其与图10、12、15和16中示出的绝缘基板2不同之处在于锚定结构3不再在底部金属化层21的整个主表面区域上方延伸,而是只沿着底部金属化层21的环形边缘带的侧面外部边缘延伸。在环形边缘带内,绝缘基板2包括通过位于边缘带内部的底部金属化层21的表面部分形成的平坦表面。
现在参考图18,其再次示出了绝缘基板2的底部金属化层21的自顶向下的图。锚定结构3包括多个纵向连接板33,其可通过如上关于底部金属化层21所描述的同样地构造有底部金属化层21或者被结合到该底部金属化层21。这种纵向连接板33可包括例如范围在从300μm至2mm的长度l33,和/或范围在从200μm至500μm范围内的高度(对应于长度l31)。基本上,支柱31也被与这种纵向连接板33组合提供。
现在参考图19,示出了底部为面向上方的底部金属化层21的陶瓷基板2的透视图。将其中支柱31通过结合线部分形成的锚定结构3施加到底部金属化层21,其每一个都在一端312结合到底部金属化层21,同时另一端311自由地远离底部金属化层21。在制造该结构时,首先结合线的该端312被结合到底部金属化层21,之后用结合器的切割工具切割或者用结合器的切割工具形成槽口,然后切割。用作支柱31的结合线部分设置在例如边缘带内部,该边缘带沿着底部金属化层21的侧面边缘延伸,如已经参考图17描述的。现在参考图20,示出了两个邻接的这种支柱31的垂直截面放大图,其高度h31看起来与支柱31的长度l31相同,长度l31已经参考图2、4、5、6描述过了。宽度b31表示结合物外部的结合线的直径。
现在参考图21,示出了在替换方面相同结合线部分31可怎样通过中心间隔d31在相互间隔开的两个位置处被结合到底部金属化层21。在该设置中,结合线部分31被结合到底部金属化层21的两个邻接结合物的中心间隔d31可小于在这两个位置之间形成的该结合线部分的回路的高度h31。而且,在结合物外部的结合线部分31的直径范围可为从模数(module)100μm到1mm。
现在参考图22,借助于实例示出了电路基板1的透视图,示出了从每个锚定结构3被确切分配给一个绝缘基板2的之前描述的实例分离出的部分中,锚定结构3一方面现在被共同提供给相互间隔的几个绝缘基板2之间的所有绝缘基板2,另一方面被提供给电路基板1。一个这种锚定结构3可例如通过如图10、11、12、13、14示出的支柱31和结合连接板32的网来构造,或者被构造成编制网(woven network)。相似地,绝缘基板2的底部金属化层21可通过完全连续的金属化膜的多个部分形成,该完全连续的金属化膜首先例如通过压印在其主表面区域中的一个上被提供有锚定结构3,且通过其另一主表面区域,连接任选地已经具有其顶部金属化层22并且利用一个或多个半导体芯片来构造的绝缘载体20。优选地,如参考图7所述的该方法用在该实例中,其中焊料被设置在锚定结构3和电路基板1之间从而底部向上地流动进入到间隙中,且--锚定结构3还没有结合到底部金属化层21或者被构造成与其一体--向上流入到底部金属化和锚定结构3之间的孔隙中,从而如已经描述的,高强度合金实现。
不管怎样构造锚定结构3,其高度h3都将超出100μm,例如在从300μm到5mm的范围内。
而且,锚定结构3例如由铜制成,不管其怎样构造。任选地,锚定结构3可包括Ag、Ni/Au、Ni/Pd、Ni/Pd/Au涂层,其厚度例如在从2μm到10μm的范围内。
用于制造电路基板1和绝缘基板2之间的结合的合适焊料4例如是具有显著锡百分含量的所有焊料,包括例如SnSb5;SnAg3.5;SnAg3.5Cu0.5;SnAg3.5Cu0.7;SnAg20,J,K或L合金,或者通常是SnxAgy、SnxAgyCuz、SnxCuy。
仍参考图22,明显看出锚定结构3怎样在所有侧面延伸出面对电路基板1的金属表面1t的底部金属化层21的底部,这对于安装在仅一个电路基板上的锚定结构3也是任选可能的。在所有侧面上延伸电路基板或者金属化覆盖层另外优化了在绝缘基板2的边缘和拐角处的机械应力控制。
现在参考图23,示出了如前所述结合技术的又一发展,从而现在电路基板1具有嵌套在支柱31的自由端311的凹穴11,在这里其被焊接到电路基板1。这些凹穴11例如可以包括范围从200μm到3mm的深度t11和/或比支柱31的宽度或直径宽度b31至少大0.1μm的宽度b11。如上所述,这些支柱31可借助于具有长度l32并且在两个邻接支柱31的侧壁之间延伸的结合连接板32被结合。
现在参考图24,示出了提供有锚定结构3的绝缘基板2的一部分的透视图,其中两个正方形截面的邻接支柱31借助于连接板32被结合。该图清楚明白地示出连接板32怎样在两个邻接支柱31的侧壁313之间延伸,虚线也表示出两个或更多个结合连接板32可从支柱31延伸或终止于支柱31。尽可能使得支柱31没有被提供有结合连接板32且仅通过其背对自由端311的端312固定地定位。
现在参考图25,示出了与图24中所示相对应的组件,除了现在支柱31具有代替正方形截面的圆形截面。
在图24和25中示出的锚定结构3中,连接板32设置成与面对绝缘基板2的支柱31的端312平齐。但是在自其分开的部分中,结合连接板32可与背对绝缘基板2的两个端311远离并且远离面对绝缘基板2的支柱31的端312,如例如借助于具有矩形截面的支柱31于图27中所示的。可能相似地,结合连接板32也被设置成与背对锚定结构3的支柱31的端311平齐,如从图28借助于例如具有矩形截面的支柱31可明显看出的。
现在参考图28,示出了功率半导体模块100的垂直截面图,如前所述,其包括绝缘基板2,该绝缘基板2的底部金属化层21使用焊料4借助锚定结构3被焊接到电路基板1。模块100包括在所有侧面上具有电绝缘框架61以及封装罩62的封装6。电路基板1被构造成金属底板,表示模块100的底部封装壁。该底板厚度范围可从0.1mm到20mm。
安装在绝缘基板2的顶部金属化层22上的是借助于例如焊料、导电粘合剂或者银压烧结结合物的结合层81连接至其的几个功率半导体芯片8。功率半导体芯片例如是可选通(gatable)功率半导体,诸如MOSFET、IGBT、晶闸管、JFET或功率二极管。功率半导体芯片8是半导体芯片,其具有例如超过50A或75A的高额定电流和/或超出400V的高额定电压。此外,功率半导体芯片的尺寸可超过5.5乘以5.5mm或者7乘以7mm。
功率半导体芯片8顶部是借助于结合线82实现的顶部金属化层22的多个部分的电路。代替结合线82,也提供例如通过焊接、通过导电粘合剂结合或银压烧结结合而导电连接到芯片顶部和/或顶部金属化层22的金属夹。
为了将功率半导体模块100向外连接到例如电源、负载、控制器等等,提供电端子91、92、93、94,构造其中的电端子91、92例如以制造电源连接和电和/或机械结合到顶部金属化层22的所述多个部分221、222、223、224、225、226。电源端子也可定位在线结合到顶部金属化层22的封装框架中。端子93、94可被构造成选通端子,例如用于一个或多个功率半导体芯片8或者作为输出端子用于输出表示功率半导体模块100的状态信息的信号。
功率半导体芯片8顶部是任选的印刷电路板(PCB)95,用于将内部驱动器端子接成电路。PCB 95也可通过电子器件补偿以选通功率半导体芯片8的可选通芯片。通过选通电子器件完善的功率半导体模块也称作“智能器件”(IPM)。
为了提高介电强度,电路基板1的底部利用任选的密封化合物(pottingcompound)51(例如硅胶)进行密封,所述密封化合物例如从绝缘基板2沿纵向中心线v延伸,至少延伸出功率半导体芯片8或者结合线82,例如远至印刷电路板95。密封化合物51顶部是任选的刚性密封化合物52,例如环氧树脂,以电绝缘电端子91、92、93、94,且92用于另外的机械稳定性。
仍参考图28,示出了锚定结构3可怎样覆盖绝缘基板2的底部金属化层21的整体。但是,基本上,任何其他组件-例如图10、12、5、16、17、18、19中所示的任一组件-都可考虑用于锚定结构3的几何形状。
为了制造功率半导体模块100,在将金属表面1t焊接到底部金属化层21和锚定结构3之前,功率半导体芯片8能稳固地结合到顶部金属化层22。通过焊接金属表面1t到底部金属化层21和锚定结构3形成的复合结构然后可配备有电端子91、92、93、94和被测试的最终模块的正确电功能。当被测试为正的(positive)时,模块被整体插入到框架61中或者模块封装6中,且之后用密封化合物51和52进行密封。当在被插入到框架61或模块封装6之前该模块被提供有电端子时,针对正确的电功能来测试最终模块是有利的。因此,如果模块测试为负的,则在被安装在模块封装6中之前,它可通过正确的功能模块被替换。而且,优点在于当一旦安装模块时不将其暴露到超出400℃的温度下。
现在参考图29,示出了功率半导体模块100中锚定结构3的可能组件的再一实例,其中锚定结构3底部为仅功率半导体芯片8的局部,即在发生最高温度的位置下方。当功率半导体芯片8可以较大距离远离电路基板的边缘时这是有利的,其中组件操作中温度变化幅度小于功率半导体芯片8的区域中的温度变化幅度。此外,当电路基板1由MMC材料(诸如AlSiC)构成时该结构是有利的。因此,电路基板1和绝缘载体20的热膨胀系数可更好地匹配,同时焊料4的热膨胀系数与其他热膨胀系数相距很远,在不存在锚定结构3时其导致与提供有锚定结构3时相比焊料的疲劳度更高。

Claims (25)

1.一种用于制造电路基板布置的方法,包括以下步骤:
提供包括金属表面的电路基板(1);
提供绝缘基板(2),该绝缘基板(2)包括绝缘载体(20),该绝缘载体(20)具有被提供有底部金属化层(21)的底部侧;
提供锚定结构(3),该锚定结构(3)包括多个长方形支柱(31),每一个长方形支柱(31)具有背对绝缘载体(20)的第一端(311),所述多个长方形支柱(31)的至少一个子集分布在整个锚定结构(3)上方,针对该子集中的每一个支柱(31)适用下述:从该支柱的侧壁(313),没有或最多有三个细长的结合连接板(32)均延伸至另一个支柱(31)的侧壁(313),在这里所述结合连接板(32)与所述另一个支柱(31)的侧壁(313)结合;
将锚定结构(3)定位在绝缘载体(20)和金属表面(1t)之间。
随后,借助焊料(4)将金属表面(1t)焊接到底部金属化层(21)和锚定结构(3),利用焊料(4)塞满金属表面(1t)和底部金属化层(21)之间的所有间隙(5)。
2.如权利要求1所述的方法,其中在将金属表面(1t)焊接到底部金属化层(21)之前,锚定结构(3)被构造成与底部金属化层(21)无关的元件。
3.如权利要求2所述的方法,其中在将金属表面(1t)焊接到底部金属化层(21)之前,将锚定结构(3)结合到底部金属化层(21)。
4.如权利要求2所述的方法,其中在将金属表面(1t)焊接到底部金属化层(21)之前,将锚定结构(3)构造成平坦的网或者构造成被穿孔的、蚀刻的或者冲压的金属化膜。
5.如前述权利要求中的任一项所述的方法,其中对于每一个支柱(31),该子集在所有情况下适用下述:从其侧壁(313),
-没有或最多有两个结合连接板(32)延伸;或者
-没有或最多有一个结合连接板(32)延伸;或者
-没有结合连接板(32)延伸。
6.如前述权利要求中的任一项所述的方法,其中锚定结构(3)包括多个结合线部分,该多个结合线部分的每一个通过至少两个结合物被结合到底部金属化层(21),每一个结合线部分形成两个邻接结合物之间的回路。
7.如权利要求6所述的方法,其中两个邻接结合物之间的中心间隔(d31)小于所述结合物之间形成的回路的高度(h31)。
8.如权利要求1所述的方法,其中在将金属表面(1t)结合到绝缘基板(2)之前,锚定结构(3)被构造成与底部金属化层(21)是一体的且由相同材料制成。
9.如权利要求8所述的方法,其中锚定结构(3)被制造成在底部金属化层(21)被结合到绝缘载体(20)之前或之后,该底部金属化层(21)被提供为具有预定膜厚度的金属化膜,以及通过向下蚀刻图形化该金属化膜到预定蚀刻深度来制造所述支柱(31),该预定蚀刻深度小于该预定膜厚度。
10.如权利要求9所述的方法,其中该预定膜厚度范围是从400μm至1mm。
11.如权利要求9或10所述的方法,其中该预定蚀刻深度范围是从200μm至700μm。
12.如权利要求8至11中的任一项所述的方法,其中
在将金属表面(1t)焊接到底部金属化层(21)之前,锚定结构(3)包括多个支柱(31),除了任何结合连接板(32)之外,所述支柱(31)的第一端(311)被构造为自由端(311);
底部金属化层(21)包括被构造成平坦的连续层(211)的部分,该平坦的连续层(211)通过背对第一端(311)的支柱(31)的第二端(312)以内结合的方式被构造成与支柱(31)是一体的。
13.如前述权利要求中的任一项所述的方法,其中在将金属表面(1t)焊接到底部金属化层(21)之后,每一个支柱(31)沿垂直于绝缘载体(20)的底部侧(20b)取向的纵向中心线(v)延伸。
14.如前述权利要求中的任一项所述的方法,其中锚定结构(3)包括一个或多个纵向连接板,所述一个或多个纵向连接板
平行于绝缘载体(20)的底部侧(20b)延伸;
相对于背对绝缘载体(20)的底部金属化层(21)的一侧,包括在从200μm到500μm范围内的高度;以及
包括在从300μm到2mm范围内的长度。
15.如前述权利要求中的任一项所述的方法,其中锚定结构(3)在平行于绝缘载体(20)的底部侧(20b)的剖面E-E’中包括共计为结合到绝缘载体(20)的底部金属化层(21)的顶部侧的表面面积的至少10%的总截面面积。
16.如前述权利要求中的任一项所述的方法,其中锚定结构(3)包括大于100μm的高度h31。
17.如前述权利要求中的任一项所述的方法,其中锚定结构(3)包括垂直于绝缘载体(20)的底部侧(20b)的高度h31,该高度h31的范围是从200μm至5mm。
18.如前述权利要求中的任一项所述的方法,其中锚定结构(3)包括垂直于绝缘载体(20)的底部侧(20b)的高度h31,该高度h31的范围是从300μm至1mm。
19.如前述权利要求中的任一项所述的方法,其中所述绝缘载体由电绝缘陶瓷形成。
20.如前述权利要求中任一项所述的方法,其中在将金属表面(1t)焊接到底部金属化层(21)之前,锚定结构(3)在高于350℃的温度下被回火。
21.如前述权利要求中的任一项所述的方法,其中在将金属表面(1t)焊接到底部金属化层(21)之前,锚定结构(3)的面对金属表面(1t)的端被嵌套到电路基板(1)的一个或多个相应的凹穴(11)中。
22.如前述权利要求中的任一项所述的方法,其中在将金属表面(1t)焊接到底部金属化层(21)之前,支柱(31)的第一端(311)被构造成自由端,所述自由端被嵌套到电路基板(1)的相应凹穴(11)中。
23.如前述权利要求中的任一项所述的方法,其中所述相应凹穴(11)的深度(t11)的范围是从200μm到3mm。
24.一种制造功率半导体模块(100)的方法,包括以下步骤:
如前述权利要求中的任一项所述的制造电路基板组件,其中绝缘基板(2)包括设置在背对底部金属化层(21)的绝缘载体(20)的顶部侧(20t)的顶部金属化层(22),并且在该顶部金属化层(22)上设置至少一个功率半导体芯片(8);
制造模块封装(6),其容纳至少一个功率半导体芯片(8)和绝缘基板(2),电路基板(1)形成该功率半导体模块(100)的底板。
25.如权利要求24所述的方法,其中在将金属表面(1t)焊接到底部金属化层(21)和锚定结构(3)之前,至少一个功率半导体芯片(8)被稳固地结合到顶部金属化层(22)。
CN2010102853797A 2009-08-07 2010-08-06 用于制造电路基板组件以及功率电子模块的方法 Expired - Fee Related CN101996897B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102009028360A DE102009028360B3 (de) 2009-08-07 2009-08-07 Verfahren zur Herstellung einer Schaltungsträgeranordnung und eines Leistungselektronikmoduls mit einer Verankerungsstruktur zur Herstellung einer temperaturwechselstabilen Lötverbindung
DE102009028360.9 2009-08-07

Publications (2)

Publication Number Publication Date
CN101996897A true CN101996897A (zh) 2011-03-30
CN101996897B CN101996897B (zh) 2013-05-08

Family

ID=43049533

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010102853797A Expired - Fee Related CN101996897B (zh) 2009-08-07 2010-08-06 用于制造电路基板组件以及功率电子模块的方法

Country Status (3)

Country Link
US (1) US8298867B2 (zh)
CN (1) CN101996897B (zh)
DE (1) DE102009028360B3 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102437731A (zh) * 2011-09-30 2012-05-02 安徽华东光电技术研究所 基于氧化铍散热结构的电源模块及其制作方法
CN102446880A (zh) * 2010-09-30 2012-05-09 英飞凌科技股份有限公司 包括插件的半导体模块和用于生产包括插件的半导体模块的方法
CN103078491A (zh) * 2011-10-26 2013-05-01 英飞凌科技股份有限公司 功率模块
CN107431056A (zh) * 2015-02-26 2017-12-01 贺利氏(德国)股份两合公司 具有钯‑氧扩散阻挡层的载体和通过烧结与该载体连接的半导体元件的功率电子模块及其制造方法
CN110098153A (zh) * 2018-01-31 2019-08-06 Abb瑞士股份有限公司 电力电子模块及制造电力电子模块的方法
CN113345809A (zh) * 2021-08-05 2021-09-03 度亘激光技术(苏州)有限公司 一种半导体器件和热沉键合的方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8520389B2 (en) * 2009-12-02 2013-08-27 Hamilton Sundstrand Corporation Power semiconductor module for wide temperature applications
DE102010003533B4 (de) * 2010-03-31 2013-12-24 Infineon Technologies Ag Substratanordnung, Verfahren zur Herstellung einer Substratanordnung, Verfahren zur Herstellung eines Leistungshalbleitermoduls und Verfahren zur Herstellung einer Leistungshalbleitermodulanordnung
US8963321B2 (en) * 2011-09-12 2015-02-24 Infineon Technologies Ag Semiconductor device including cladded base plate
US8519532B2 (en) * 2011-09-12 2013-08-27 Infineon Technologies Ag Semiconductor device including cladded base plate
US8563364B2 (en) * 2011-09-29 2013-10-22 Infineon Technologies Ag Method for producing a power semiconductor arrangement
DE102011089886A1 (de) * 2011-12-23 2013-02-07 Continental Automotive Gmbh Schaltungsträger und Verfahren zur Herstellung von einem Schaltungsträger
JP2013201255A (ja) * 2012-03-23 2013-10-03 Toshiba Lighting & Technology Corp 配線基板装置、発光モジュール、照明装置および配線基板装置の製造方法
CN104335472A (zh) * 2012-05-28 2015-02-04 三菱电机株式会社 半导体装置
JP6139331B2 (ja) * 2013-08-26 2017-05-31 三菱電機株式会社 パワーモジュール
JP2015050303A (ja) * 2013-08-30 2015-03-16 東芝ライテック株式会社 発光装置
US9585241B2 (en) * 2013-09-24 2017-02-28 Infineon Technologies Ag Substrate, chip arrangement, and method for manufacturing the same
US10276472B2 (en) * 2017-04-01 2019-04-30 Ixys, Llc Heat transfer plate having small cavities for taking up a thermal transfer material
EP3627546A1 (en) 2018-09-24 2020-03-25 Infineon Technologies AG Power semiconductor module arrangement
DE102018221160A1 (de) * 2018-12-06 2020-06-10 Siemens Aktiengesellschaft Isolierkeramik für elektrische Schaltungen und zugehörige Anwendungen
US11462501B2 (en) * 2019-10-25 2022-10-04 Shinko Electric Industries Co., Ltd. Interconnect substrate and method of making the same
JP2022029328A (ja) * 2020-08-04 2022-02-17 パナソニックIpマネジメント株式会社 半導体装置およびその製造方法
US20230371165A1 (en) * 2022-05-12 2023-11-16 Infineon Technologies Austria Ag Voltage regulator module with inductor-cooled power stage
DE102022113641A1 (de) 2022-05-31 2023-11-30 Rolls-Royce Deutschland Ltd & Co Kg Leiterplattenanordnung

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6406636B1 (en) * 1999-06-02 2002-06-18 Megasense, Inc. Methods for wafer to wafer bonding using microstructures
US20050270744A1 (en) * 2004-06-03 2005-12-08 International Business Machines Corporation Compliant thermal interface for electronic equipment
US20050275114A1 (en) * 2004-06-09 2005-12-15 Kabushiki Kaisha Toshiba Semiconductor device and semiconductor apparatus
CN101165884A (zh) * 2006-10-20 2008-04-23 英飞凌科技股份公司 半导体装置和模块以及连接半导体芯片到陶瓷基板的方法
US20080230905A1 (en) * 2007-03-19 2008-09-25 Karsten Guth Power Semiconductor Module, Method for Producing a Power Semiconductor Module, and Semiconductor Chip

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7821130B2 (en) * 2008-03-31 2010-10-26 Infineon Technologies Ag Module including a rough solder joint
US7928563B2 (en) * 2008-05-28 2011-04-19 Georgia Tech Research Corporation 3-D ICs with microfluidic interconnects and methods of constructing same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6406636B1 (en) * 1999-06-02 2002-06-18 Megasense, Inc. Methods for wafer to wafer bonding using microstructures
US20050270744A1 (en) * 2004-06-03 2005-12-08 International Business Machines Corporation Compliant thermal interface for electronic equipment
US20050275114A1 (en) * 2004-06-09 2005-12-15 Kabushiki Kaisha Toshiba Semiconductor device and semiconductor apparatus
CN101165884A (zh) * 2006-10-20 2008-04-23 英飞凌科技股份公司 半导体装置和模块以及连接半导体芯片到陶瓷基板的方法
US20080230905A1 (en) * 2007-03-19 2008-09-25 Karsten Guth Power Semiconductor Module, Method for Producing a Power Semiconductor Module, and Semiconductor Chip

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446880A (zh) * 2010-09-30 2012-05-09 英飞凌科技股份有限公司 包括插件的半导体模块和用于生产包括插件的半导体模块的方法
CN102437731A (zh) * 2011-09-30 2012-05-02 安徽华东光电技术研究所 基于氧化铍散热结构的电源模块及其制作方法
CN103078491A (zh) * 2011-10-26 2013-05-01 英飞凌科技股份有限公司 功率模块
CN103078491B (zh) * 2011-10-26 2016-08-03 英飞凌科技股份有限公司 功率模块
CN107431056A (zh) * 2015-02-26 2017-12-01 贺利氏(德国)股份两合公司 具有钯‑氧扩散阻挡层的载体和通过烧结与该载体连接的半导体元件的功率电子模块及其制造方法
TWI609469B (zh) * 2015-02-26 2017-12-21 Heraeus Deutschland Gmbh & Co Kg 電力電子模組及其製法
CN110098153A (zh) * 2018-01-31 2019-08-06 Abb瑞士股份有限公司 电力电子模块及制造电力电子模块的方法
CN110098153B (zh) * 2018-01-31 2022-11-18 Abb瑞士股份有限公司 电力电子模块及制造电力电子模块的方法
CN113345809A (zh) * 2021-08-05 2021-09-03 度亘激光技术(苏州)有限公司 一种半导体器件和热沉键合的方法
CN113345809B (zh) * 2021-08-05 2021-11-19 度亘激光技术(苏州)有限公司 一种半导体器件和热沉键合的方法

Also Published As

Publication number Publication date
DE102009028360B3 (de) 2010-12-09
CN101996897B (zh) 2013-05-08
US20110053319A1 (en) 2011-03-03
US8298867B2 (en) 2012-10-30

Similar Documents

Publication Publication Date Title
CN101996897B (zh) 用于制造电路基板组件以及功率电子模块的方法
US8587116B2 (en) Semiconductor module comprising an insert
CN103426861B (zh) 功率半导体的可靠区域接合件
US20170092611A1 (en) Porous metallic film as die attach and interconnect
US7800220B2 (en) Power electronics assembly with cooling element
US8658472B2 (en) Semiconductor device
US20040070072A1 (en) Semiconductor device having radiation structure
US8097959B2 (en) Semiconductor device including first and second carriers
US8129225B2 (en) Method of manufacturing an integrated circuit module
CN103035601A (zh) 在烧结银层上包括扩散焊接层的半导体器件
US12002739B2 (en) Semiconductor device including an embedded semiconductor die
US9583413B2 (en) Semiconductor device
US10283430B2 (en) Power semiconductor device and method for manufacturing same
Mertens et al. Top-side chip contacts with low temperature joining technique (LTJT)
US20220102311A1 (en) Semiconductor device module having vertical metallic contacts and a method for fabricating the same
CN212587507U (zh) 采用多芯片堆叠结构的功率分立器件
US20200098662A1 (en) Power Semiconductor Module Arrangement
US11756923B2 (en) High density and durable semiconductor device interconnect
US11004823B2 (en) Chip assembly and method of manufacturing thereof
US20240250057A1 (en) Semiconductor package and method of manufacturing the same
CN118116894A (zh) 功率半导体封装结构、装置及其烧结方法
CN118712164A (zh) 在金属部件之间具有无应力接头的功率半导体器件及其制造方法
JP2021044456A (ja) 半導体装置
JP2019140334A (ja) 半導体装置および半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130508

CF01 Termination of patent right due to non-payment of annual fee