JP6036739B2 - モジュールおよびその製造方法 - Google Patents
モジュールおよびその製造方法 Download PDFInfo
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- JP6036739B2 JP6036739B2 JP2014077828A JP2014077828A JP6036739B2 JP 6036739 B2 JP6036739 B2 JP 6036739B2 JP 2014077828 A JP2014077828 A JP 2014077828A JP 2014077828 A JP2014077828 A JP 2014077828A JP 6036739 B2 JP6036739 B2 JP 6036739B2
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- layer
- resin layer
- conductive resin
- sealing resin
- metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Description
次に、モジュール1の製造方法について説明する。この実施形態では、複数のモジュール1の集合体をダイシングにより個片化する場合の製造方法について説明する。
次に、上記したモジュール1の製造方法の他の例について説明する。
2 配線基板
3 部品
4 封止樹脂層
5 シールド層
5a 導電性樹脂層
5b 金属めっき層
8a 接地用電極
10 金属フィラ
Claims (9)
- 配線基板と、
前記配線基板の一方主面に実装された部品と、
前記配線基板の一方主面に設けられた前記部品を封止する封止樹脂層と、
前記封止樹脂層の表面を被覆して設けられたシールド層とを備え、
前記シールド層が、前記封止樹脂層に積層された金属フィラを含有する導電性樹脂層と、前記導電性樹脂層に積層された金属めっき層とで形成され、
前記導電性樹脂層に含有する前記金属フィラの密度は、前記封止樹脂層側よりも前記金属めっき層側が高いことを特徴とするモジュール。 - 前記導電性樹脂層の樹脂成分は、前記封止樹脂層の樹脂成分が有する官能基と同じ官能基を有することを特徴とする請求項1に記載のモジュール。
- 前記導電性樹脂層の厚みが、前記金属めっき層の厚みよりも薄いことを特徴とする請求項1または2に記載のモジュール。
- 前記金属フィラが扁平状に形成されていることを特徴とする請求項1ないし3のいずれかに記載のモジュール。
- 前記シールド層が、前記配線基板に形成された接地用電極に接続されていることを特徴とする請求項1ないし4のいずれかに記載のモジュール。
- 前記金属めっき層が、無電解めっきにより形成されていることを特徴とする請求項1ないし5のいずれかに記載のモジュール。
- 配線基板の一方主面に部品を実装する第1の工程と、
前記配線基板の一方主面および前記部品を被覆するように封止樹脂を塗布した後、前記封止樹脂を半硬化状態にする第2の工程と、
前記封止樹脂の表面を被覆するように、金属フィラを含有する導電性樹脂を塗布する第3の工程と、
前記封止樹脂および前記導電性樹脂を完全硬化させることにより、前記封止樹脂から成る封止樹脂層と、前記封止樹脂層に積層された前記導電性樹脂から成る導電性樹脂層とを形成する第4の工程と、
めっき処理により、前記導電性樹脂層に金属めっき層を積層する第5の工程と、
を備えることを特徴とするモジュールの製造方法。 - 前記第4の工程の後に、前記導電性樹脂層の表面に、酸素プラズマ処理、UVオゾン処理、酸化性薬品による酸化処理のうちのいずれかの処理を施すことにより、前記導電性樹脂層の表面の樹脂を分解して当該表面における前記金属フィラの露出量を増加させる工程をさらに備えることを特徴とする請求項7に記載のモジュールの製造方法。
- 前記第5の工程は、無電解めっきにより前記導電性樹脂層上に前記金属めっき層の一部を形成した後、電解めっきにより前記金属めっき層の残りの部分を形成することを特徴とする請求項7または8に記載のモジュールの製造方法。
Priority Applications (2)
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JP2014077828A JP6036739B2 (ja) | 2014-04-04 | 2014-04-04 | モジュールおよびその製造方法 |
CN201520185964.8U CN205177809U (zh) | 2014-04-04 | 2015-03-30 | 具有屏蔽层的模块 |
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JP2014077828A JP6036739B2 (ja) | 2014-04-04 | 2014-04-04 | モジュールおよびその製造方法 |
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JP2015201479A JP2015201479A (ja) | 2015-11-12 |
JP6036739B2 true JP6036739B2 (ja) | 2016-11-30 |
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JP (1) | JP6036739B2 (ja) |
CN (1) | CN205177809U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9759116B2 (en) | 2013-10-29 | 2017-09-12 | Continental Automotive Systems, Inc. | Method and apparatus for detecting selective catalytic reduction injector opening time |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7096640B2 (ja) * | 2016-02-15 | 2022-07-06 | ぺんてる株式会社 | 抵抗性周囲電極 |
JP6407186B2 (ja) * | 2016-03-23 | 2018-10-17 | Tdk株式会社 | 電子回路パッケージ |
JP6107998B1 (ja) * | 2016-03-23 | 2017-04-05 | Tdk株式会社 | 電子回路パッケージ |
JP6328698B2 (ja) * | 2016-07-26 | 2018-05-23 | Tdk株式会社 | 電子回路パッケージ |
JP6654994B2 (ja) * | 2016-10-31 | 2020-02-26 | Towa株式会社 | 回路部品の製造方法 |
JP7074201B2 (ja) | 2018-09-27 | 2022-05-24 | 株式会社村田製作所 | モジュールおよびその製造方法 |
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JPS56129264A (en) * | 1980-03-14 | 1981-10-09 | Kubota Ltd | Coal tar epoxy resin paint |
JPS60246695A (ja) * | 1984-05-22 | 1985-12-06 | 松下電器産業株式会社 | 印刷配線板の製造方法 |
JP2000290617A (ja) * | 1999-04-08 | 2000-10-17 | Asahi Chem Ind Co Ltd | 導電性接着剤およびその使用法 |
JP2002124755A (ja) * | 2000-08-09 | 2002-04-26 | Murata Mfg Co Ltd | 導電性接着剤と電極との接合方法およびその接合構造 |
US7633170B2 (en) * | 2005-01-05 | 2009-12-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and manufacturing method thereof |
JP4735464B2 (ja) * | 2006-08-01 | 2011-07-27 | 富士通株式会社 | 回路基板およびその製造方法 |
JP2009172586A (ja) * | 2007-12-26 | 2009-08-06 | Kyodo Printing Co Ltd | 表面突起膜及びその形成方法 |
JP2010109274A (ja) * | 2008-10-31 | 2010-05-13 | Sanyo Electric Co Ltd | 半導体モジュールおよび半導体モジュールの製造方法 |
JP5481701B2 (ja) * | 2009-06-19 | 2014-04-23 | 新光電気工業株式会社 | 電子装置および電子装置の製造方法 |
JP2013041999A (ja) * | 2011-08-17 | 2013-02-28 | Nec Corp | モジュール部品の製造方法、モジュール部品の製造装置及びモジュール部品集合体 |
JP6136152B2 (ja) * | 2012-09-11 | 2017-05-31 | 日本電気株式会社 | モジュール部品の製造方法 |
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2014
- 2014-04-04 JP JP2014077828A patent/JP6036739B2/ja active Active
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9759116B2 (en) | 2013-10-29 | 2017-09-12 | Continental Automotive Systems, Inc. | Method and apparatus for detecting selective catalytic reduction injector opening time |
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JP2015201479A (ja) | 2015-11-12 |
CN205177809U (zh) | 2016-04-20 |
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