TWI588934B - 用於固持具有定向缺口的半導體晶圓的基座、用於在半導體晶圓上沉積層的方法、以及半導體晶圓 - Google Patents

用於固持具有定向缺口的半導體晶圓的基座、用於在半導體晶圓上沉積層的方法、以及半導體晶圓 Download PDF

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TWI588934B
TWI588934B TW105133134A TW105133134A TWI588934B TW I588934 B TWI588934 B TW I588934B TW 105133134 A TW105133134 A TW 105133134A TW 105133134 A TW105133134 A TW 105133134A TW I588934 B TWI588934 B TW I588934B
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semiconductor wafer
placement surface
notch
susceptor
region
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林哈德 史喬爾
克利斯丁 哈格
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世創電子材料公司
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Description

用於固持具有定向缺口的半導體晶圓的基座、用於在半導體晶圓上沉積層的方法、以及半導體晶圓
本發明的主題係關於一種基座，所述基座係用於在半導體晶圓的前側上沉積層的期間固持具有定向缺口的半導體晶圓。基座具有放置表面和所述放置表面的階梯形外定界，所述放置表面係用於放置半導體晶圓的後側的邊緣區域。本發明的主題也是關於一種用於在具有定向缺口的半導體晶圓上沉積層的方法（其中，所述基座係用於所述方法中），以及由單晶矽製成的半導體晶圓。
如下各個實施態樣中所提及類型的基座係已知的。DE19847101C1中描述了一個實施態樣，其中放置表面是形成基座的環的組件。根據EP1460679A1的實施態樣中，基座額外具有底部因此為盤的形式。放置表面係由在盤邊緣上的凸出部分所形成。DE102006055038A1示出了一個實施態樣，其中半導體晶圓位於環的凹陷部分中，且環位於基盤上。
當在半導體晶圓的前側上沉積層時，特別致力於生成具有均勻層厚度的層並使該層的可用表面盡可能向半導體晶圓的邊緣延伸。當試圖實現該規格時，面臨的問題是發生在半導體晶圓的定向缺口的區域中的平坦度問題，造成問題的原因是半導體晶圓的後側上的較厚的層厚度和材料沉積。為了解決這個問題，在US 2012/0270407 A1和JP 2013-51290中提出了基座的放置表面在一個點處向內擴大，且半導體晶圓係放在基座上使得定向缺口在該點處靠在放置表面上。
US 2013/0264690 A1關於具有磊晶層的半導體晶圓（特別是在半導體晶圓的邊緣區域中）的平坦度的改進。由ESFQR mean表示並考慮1毫米之邊緣去除的前側之邊緣區域中的局部幾何形狀不大於100奈米。
儘管所引用的現有技術，改進經塗覆之半導體晶圓在定向缺口之區域中之局部平坦度的需求仍然存在。
本發明的目的是提出一種解決方案，此解決方案大大減少了在定向缺口區域中過量的層厚度以及沉積在半導體晶圓後側上定向缺口區域中過量的材料。
透過以下基座實現該目的：所述基座用於在具有定向缺口的半導體晶圓的前側上沉積層的期間固持所述半導體晶圓；所述基座包括： 放置表面，其係用於放置半導體晶圓之後側的邊緣區域； 放置表面的階梯形外定界；以及 放置表面之外定界的凹口，以便將半導體晶圓之後側之邊緣區域之所述定向缺口位於其中的局部區域放置在所述放置表面之由其外定界之凹口界定的局部區域上。
放置表面的外定界的凹口係向內定向，且較佳具有與放置在基座上之半導體晶圓之定向缺口的形狀互補的形狀。放置表面之外定界之凹口的存在具有確保在半導體晶圓的外邊緣和放置表面的外定界之間存在一致距離的效果。此距離在定向缺口的區域中以及在定向缺口外的區域中是基本上相同的。這對沉積氣體的流動行為有影響。在定向缺口的區域中以及在定向缺口外的區域中的流動圖像（flow picture）基本上也是相同的。因此在半導體晶圓之邊緣區域中的材料沉積係實質上均勻的。
放置表面和放置表面的階梯形外定界形成具有幾乎一致直徑之接近圓形的穴部（pocket），所述穴部用於容納具有定向缺口的半導體晶圓。由於放置表面之外定界的凹口，放置表面之外定界的直徑在該位置處比在其餘位置處更小。
放置表面的徑向寬度是在放置表面的外定界和放置表面的內邊緣之間的距離。放置表面的徑向寬度比放置表面之外定界之凹口範圍外的直徑小得多。較佳不大於此直徑的10%。另一方面，放置表面足夠寬以於其上可完全墊起半導體晶圓的定向缺口所在的區域，即，在放置表面之外定界之凹口的區域中，放置表面具有徑向寬度，因此放置表面至少向內延伸至在放置表面之此區域上鋪放的半導體晶圓的定向缺口。因此，沉積氣體通過定向缺口至半導體晶圓的後側變得更加困難。
放置表面的徑向寬度較佳係一致的，即，在放置表面之外定界之凹口的區域內與在此區域外是基本上相同的。在這種情況下，在放置表面之由其外定界之凹口界定的區域中設有放置表面之向內定向的凹口。儘管如此，放置表面在其外定界之凹口的區域的徑向寬度比此區域外更小。
放置表面係水平或稍微向內傾斜地設置。傾斜的角度較佳不大於3°。傾斜的外形可為直線或彎曲的。
基座可形成為環，基座包括放置表面和放置表面的外定界。此外，基座可形成為盤，額外包括盤形（disk-shaped）盤底部，所述盤形盤底部接近放置表面的內邊緣並低於放置表面。此外，基座能夠以兩個部分的方式被形成，一個部分被形成為環，所述環包括放置表面和放置表面的外定界，另一部分被形成為承載所述環的單獨的基底盤。盤底部或基底盤可以是不透氣的。然而，盤底部或基底盤也可形成為有孔的，以確保氣體穿過孔輸送。盤底部或基底盤較佳具有微細孔，而不是用於氣體輸送的孔。舉例言之，微孔可在纖維及／或顆粒被緊壓到盤底部或基底盤的形狀中生成。
基座較佳由碳化矽或使用碳化矽塗覆之諸如石墨的材料所組成。
本發明的主題關於是一種用於在具有定向缺口的半導體晶圓上沉積層的方法，其特徵在於 將半導體晶圓放置在根據本發明的基座上，其中，半導體晶圓之後側之邊緣區域之定向缺口位於其中的區域係被放置在基座之放置表面之由其外定界之凹口界定的區域上； 供應處理氣體至半導體晶圓的前側並沉積層在半導體晶圓的前側上。
所述方法使得在定向缺口區域中具有沉積之層之半導體晶圓具有經改進的平坦度以及在具有沉積之層之半導體晶圓的邊緣區域中具有更一致的平坦度。
在將半導體晶圓放置在基座上之後，半導體晶圓的邊緣也在定向缺口的區域中基本上具有距放置表面之外定界相同的距離。如果放置表面之外定界的凹口不存在，那麼在定向缺口之區域內的距離會比此區域外更大。由於更大的距離，在定向缺口的區域內會比此區域外沉積更多的材料，這是因為更大的距離，更大量的沉積氣體達到半導體晶圓之前側的邊緣區域。在半導體晶圓之後側之邊緣區域中的沉積係類似的。半導體晶圓邊緣距放置表面之外定界的更大的距離會導致半導體晶圓之後側在定向缺口之區域中之更強的塗覆。此效果在如下情況係特別顯著：如果放置表面向內成斜坡地傾斜及／或基座係由對沉積氣體是可滲透的多孔材料所組成、及／或盤底部或基底盤上設有規則設置之使沉積氣體更容易到達半導體晶圓之後側的孔。
該方法較佳用於在單晶半導體晶圓上沉積磊晶層，特別佳係在由單晶矽製成的半導體晶圓上沉積由矽製成的磊晶層。由單晶矽製成的半導體晶圓較佳具有不小於200毫米的直徑，特別佳具有不小於300毫米的直徑。磊晶層的厚度較佳不小於1.5微米且不大於5微米。
本發明的主題也關於該方法的產品，也就是由單晶矽製成的半導體晶圓，所述半導體晶圓具有直徑、前側、後側、邊緣區域、在所述邊緣區域中的定向缺口、以及在前側上由矽製成的磊晶層，其中所述磊晶層的厚度不小於1.5微米且不大於5微米，其特徵在於半導體晶圓在定向缺口的區域中之由ESFQR表示的局部平坦度不小於5奈米且不大於20奈米。
ESFQR是描述在半導體晶圓之前側的邊緣區域中之72個扇形（sector）的局部平坦度參數。扇形的角寬度（width）為5°且徑向長度為30毫米。根據本發明，其中所述定向缺口位於其中的扇形具有不小於5奈米和不大於20奈米的局部平坦度ESFQR，其中在ESFQR的測定中，1毫米的邊緣去除（edge exclusion，EE）和圍繞定向缺口的矩形去除窗（rectangular exclusion window）（缺口去除窗（notch exclusion window））仍未被考慮。矩形去除窗位於定向缺口的中央上方，且具有4毫米的寬度以及2.5毫米的高度。所述高度從半導體晶圓的圓周沿著定向缺口的中間延伸。
半導體晶圓之後側上之沉積材料的厚度在包圍定向缺口的矩形評估區上較佳不大於15奈米。評估區位於定向缺口的中央上方且具有8毫米的寬度和3.5毫米的高度。所述高度沿著定向缺口的中心延伸並具有距半導體晶圓之圓周0.5毫米的距離。這樣一種圓的圓周是半導體晶圓的圓周，其中所述圓以半導體晶圓的圓心為圓心並且以半導體晶圓的直徑為直徑。定向缺口的中心從定向缺口的頂點徑向延伸至半導體晶圓的圓周。定向缺口的頂點位於定向缺口之具有距半導體晶圓中心最小距離的位置處。
根據第1圖的反應器，包括具有上冠部1、下冠部2以及側壁3的腔室（chamber）。上冠部1以及下冠部2對於熱幅射是可穿透的，熱輻射係被設置從腔室上方及腔室下方的輻射加熱器發出。自氣相在半導體晶圓4的前側上沉積層，原因在於沉積氣體被引導越過經加熱之半導體晶圓的前側且此時與經暴露之前側的表面反應並同時形成層。半導體晶圓之將要沉積層的側向表面係被稱為前側。在這種情況下，所述側向表面通常是半導體晶圓之經拋光的側向表面。因為層的沉積，所以半導體晶圓獲得由層之自由表面形成的新前側。沉積氣體通過在腔室之側壁中的氣體入口供應，反應後剩餘的廢氣通過在腔室之側壁中的氣體出口排出。具有其它氣體入口以及其它氣體出口的腔室的實施態樣是習知的。舉例言之，這些實施態樣係被用於將沖洗氣體引入及排出存在於半導體晶圓下方的腔室體積。
在層的沉積期間，半導體晶圓由基座5固持並與基座一起圍繞基座的中心旋轉。
第2圖在俯視圖中示出了根據本發明的基座。基座5包括放置表面6以及放置表面的階梯形外定界7，放置表面用於放置半導體晶圓之後側的邊緣區域。放置表面從階梯形外定界7延伸直至放置表面的內邊緣9。基座5具有盤的形狀，盤具有底部8。底部8係設置為比放置表面6低。階梯形外定界7具有向內定向的凹口10。凹口10大致是V形的，因此與半導體晶圓之定向缺口的形狀互補成形。在凹口10之區域外之放置表面的外定界7的直徑d係大於將被放置之半導體晶圓的直徑。
在根據第3圖的放大圖中可看出，示出之實施態樣的放置表面在凹口10之區域內比在此區域外之寬度更小。
第4圖示出了根據第2圖的基座5，具有定向缺口12的半導體晶圓11係被放置在基座上。半導體晶圓11以其後側之邊緣區域位於放置表面6上，使得半導體晶圓之後側之邊緣區域之定向缺口12位於其中的區域被放置在放置表面6之由外定界的凹口10界定的區域上。
第5圖示出之基座之放置表面之外定界之凹口10之區域的放大圖，此實施態樣的基座是特別佳的。放置表面6在凹口10之區域內的寬度與該區域外的寬度相同。為達成此結果，放置表面6之向內定向的凹口13也在此區域中提供。
實施例和比較例：
在根據第1圖的反應器中，由單晶矽製成之具有300毫米直徑的半導體晶圓係塗覆上由矽製成之2.5微米厚的磊晶層。隨後，透過WaferSight類型的測量裝置（製造商：KLA-Tencor Corporation）測定具有定向缺口之扇形的局部平坦度ESFQR，透過共聚焦顯微鏡研究在定向缺口區域之後側的形貌（topography）。
在磊晶層的沉積期間，根據實施例的半導體晶圓以其後側之邊緣區域被鋪放在根據本發明的基座上，所述基座在放置表面之外定界的凹口區域內具有第5圖中所示出的特徵。外定界的凹口和半導體晶圓的定向缺口係如第4圖所示出之相對於彼此被設置。
不同地，根據比較例的半導體晶圓在磊晶層的沉積期間被鋪放在具有US 2012/0270407 A1中所描述之特徵的基座上。定向缺口由US 2012/0270407 A1中示出之放置表面的突出部分墊起。
在根據實施例的半導體晶圓中，對於1毫米的邊緣去除，具有定向缺口之扇形中的ESFQR係不大於20奈米，最好不大於10奈米。
相較下，在根據比較例的半導體晶圓中，在具有定向缺口扇形中的ESFQR係不小於40奈米。
第6圖和第7圖示出了根據實施例（第6圖）和比較例（第7圖）之具有磊晶塗層之半導體晶圓之定向缺口的區域中在後側上之材料沉積的形貌和高度形狀。
在共聚焦顯微鏡中的光學評估中示出了在根據實施例之半導體晶圓的情況下，在定向缺口的區域中幾乎沒有陰影（第6圖）；反觀在根據比較例之半導體晶圓的情況下，在此區域中表示材料沉積的陰影是清晰可辨的（第7圖）。
在這兩種情況下，材料沉積之相關的高度形狀係沿線14被測定的，所述線距相應之半導體晶圓之定向缺口的頂點15有1毫米的距離。選擇所述線的原因是在共聚焦顯微鏡的評估中，其係評估區域內預期所述材料沉積的最大厚度。
在根據實施例的半導體晶圓的情況下，材料沉積的最大厚度不大於10奈米（第6圖），但在根據該比較例的半導體晶圓的情況下，材料沉積的最大厚度大於700奈米（第7圖）。
1：上冠部 2：下冠部 3：側壁 4、11：半導體晶圓 5：基座 6：放置表面 7：外定界 8：底部 9：內邊緣 10、13：凹口 12：定向缺口 14：線 15：頂點 d：直徑
本發明將在下文基於附圖和實施例進行更詳細的描述。 第1圖示出了反應器的標準特徵，其係用於在半導體晶圓上沉積層的方法中。 第2圖在俯視圖中示出了本發明設計的基座。 第3圖示出了根據第2圖之基座的放置表面之區域的放大圖，該區域係由放置表面之外定界的凹口所界定。 第4圖示出了根據第2圖的基座以及額外被放置在基座上之具有定向缺口的半導體晶圓。 第5圖示出了基座之由放置表面之外定界之凹口界定之放置表面的區域以及額外地在此區域中之放置表面的凹口的放大圖。 第6圖示出了根據本發明所生產之半導體晶圓之後側上在定向缺口之區域中的材料沉積，以及沿著與定向缺口的頂點具有微小距離之線之材料沉積的高度形狀。 第7圖示出並非根據本發明所生產之半導體晶圓之對應於第6圖的示意圖。
5：基座 6：放置表面 7：外定界 8：底部 9：內邊緣 10：凹口 d：直徑

Claims (11)

  1. 一種用於在具有定向缺口（orientation notch）之一半導體晶圓的前側上沉積一層的期間固持所述半導體晶圓的基座，包括： 一放置表面，其係用於放置所述半導體晶圓之後側的邊緣區域； 所述放置表面的一階梯形外定界；以及 所述放置表面之外定界的一凹口（indentation），以便將所述半導體晶圓之後側之邊緣區域之所述定向缺口位於其中的局部區域放置在所述放置表面之由其外定界之凹口界定的局部區域上。
  2. 如請求項1所述的基座，其中，所述放置表面的凹口用於放置所述半導體晶圓之後側之邊緣區域之所述定向缺口位於其中的局部區域。
  3. 如請求項1或2所述的基座，其中，所述放置表面係水平設置。
  4. 如請求項1或2所述的基座，其中，所述放置表面係向內傾斜設置，其中傾斜的角度不大於3°。
  5. 如請求項1或2所述的基座，其中，在所述半導體晶圓放置之後，所述放置表面以其由外定界之凹口界定的區域至少向內延伸遠至所述定向缺口。
  6. 一種用於在具有定向缺口的一半導體晶圓上沉積一層的方法，其特徵在於，將所述半導體晶圓放置在如請求項1至5中任一項所述的基座上，其中，所述半導體晶圓之後側之邊緣區域之所述定向缺口位於其中的區域係被放置在所述基座之放置表面之由外定界之凹口界定的區域上； 供應一處理氣體至所述半導體晶圓的前側並沉積所述層在所述半導體晶圓的前側上。
  7. 如請求項6所述的方法，其中，一磊晶層（epitaxial layer）係被沉積在所述半導體晶圓的前側上。
  8. 如請求項6所述的方法，其中，由矽製成的一磊晶層係被沉積在由矽製成的一單晶半導體晶圓上，所述磊晶層的厚度不小於1.5微米且不大於5微米。
  9. 一種由單晶矽製成的半導體晶圓，所述半導體晶圓具有一直徑、一前側、一後側、一邊緣區域、在所述邊緣區域中的一定向缺口、以及在所述前側上之由矽製成的一磊晶層，其中所述磊晶層的厚度不小於1.5微米且不大於5微米，其特徵在於，所述半導體晶圓在所述定向缺口的區域中之由ESFQR表示的局部平坦度不小於5奈米且不大於20奈米。
  10. 如請求項9所述的半導體晶圓，其中所述半導體晶圓具有不小於200毫米的直徑。
  11. 如請求項9或10所述的半導體晶圓，其中，在所述半導體晶圓的後側上的材料沉積是在包圍所述定向缺口的一矩形評估區上，其中，所述材料沉積的厚度不大於15奈米。
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DE102015220924B4 (de) * 2015-10-27 2018-09-27 Siltronic Ag Suszeptor zum Halten einer Halbleiterscheibe mit Orientierungskerbe, Verfahren zum Abscheiden einer Schicht auf einer Halbleiterscheibe und Halbleiterscheibe
DE102015224933A1 (de) * 2015-12-11 2017-06-14 Siltronic Ag Monokristalline Halbleiterscheibe und Verfahren zur Herstellung einer Halbleiterscheibe
DE102017206671A1 (de) * 2017-04-20 2018-10-25 Siltronic Ag Suszeptor zum Halten einer Halbleiterscheibe mit Orientierungskerbe während des Abscheidens einer Schicht auf einer Vorderseite der Halbleiterscheibe und Verfahren zum Abscheiden der Schicht unter Verwendung des Suszeptors
CN108950680A (zh) * 2018-08-09 2018-12-07 上海新昇半导体科技有限公司 外延基座及外延设备
DE102019207772A1 (de) 2019-05-28 2020-12-03 Siltronic Ag Verfahren zum Abscheiden einer epitaktischen Schicht auf einer Vorderseite einer Halbleiterscheibe und Vorrichtung zur Durchführung des Verfahrens
EP3957776A1 (de) * 2020-08-17 2022-02-23 Siltronic AG Verfahren zum abscheiden einer epitaktischen schicht auf einer substratscheibe
EP3996130B1 (de) 2020-11-09 2023-03-08 Siltronic AG Verfahren zum abscheiden einer epitaktischen schicht auf einer substratscheibe

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120270407A1 (en) * 2011-04-19 2012-10-25 Siltronic Ag Susceptor for supporting a semiconductor wafer and method for depositing a layer on a front side of a semiconductor wafer

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63244613A (ja) * 1987-03-30 1988-10-12 Kyushu Denshi Kinzoku Kk 気相成長用支持台
JPH0529230A (ja) 1991-07-22 1993-02-05 Toshiba Corp 気相成長装置
JPH05275355A (ja) * 1992-03-27 1993-10-22 Toshiba Corp 気相成長装置
US5444217A (en) * 1993-01-21 1995-08-22 Moore Epitaxial Inc. Rapid thermal processing apparatus for processing semiconductor wafers
JP2001525997A (ja) 1997-05-20 2001-12-11 東京エレクトロン株式会社 処理装置
DE19847101C1 (de) 1998-10-13 2000-05-18 Wacker Siltronic Halbleitermat CVD-Reaktor und Verfahren zur Herstellung einer mit einer epitaktischen Schicht versehenen Halbleiterscheibe
US6163015A (en) * 1999-07-21 2000-12-19 Moore Epitaxial, Inc. Substrate support element
JP2001110765A (ja) * 1999-10-05 2001-04-20 Sumitomo Metal Ind Ltd 高精度ウェーハとその製造方法
WO2002035593A1 (fr) * 2000-10-26 2002-05-02 Shin-Etsu Handotai Co.,Ltd. Procede de production de plaquettes, appareil de polissage et plaquette
EP1460679A1 (en) 2001-11-30 2004-09-22 Shin-Etsu Handotai Co., Ltd Susceptor, gaseous phase growing device, device and method for manufacturing epitaxial wafer, and epitaxial wafer
JP4093793B2 (ja) * 2002-04-30 2008-06-04 信越半導体株式会社 半導体ウエーハの製造方法及びウエーハ
JP3769262B2 (ja) * 2002-12-20 2006-04-19 株式会社東芝 ウェーハ平坦度評価方法、その評価方法を実行するウェーハ平坦度評価装置、その評価方法を用いたウェーハの製造方法、その評価方法を用いたウェーハ品質保証方法、その評価方法を用いた半導体デバイスの製造方法、およびその評価方法によって評価されたウェーハを用いた半導体デバイスの製造方法
JP4304720B2 (ja) * 2004-07-30 2009-07-29 信越半導体株式会社 サセプタ、気相成長装置、エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ
JP2006186105A (ja) * 2004-12-27 2006-07-13 Steady Design Ltd エピタキシャル成長装置およびそれに用いるサセプター
DE102005045337B4 (de) * 2005-09-22 2008-08-21 Siltronic Ag Epitaxierte Siliciumscheibe und Verfahren zur Herstellung von epitaxierten Siliciumscheiben
DE102005045339B4 (de) * 2005-09-22 2009-04-02 Siltronic Ag Epitaxierte Siliciumscheibe und Verfahren zur Herstellung von epitaxierten Siliciumscheiben
DE102005045338B4 (de) * 2005-09-22 2009-04-02 Siltronic Ag Epitaxierte Siliciumscheibe und Verfahren zur Herstellung von epitaxierten Siliciumscheiben
TWI354320B (en) * 2006-02-21 2011-12-11 Nuflare Technology Inc Vopor phase deposition apparatus and support table
DE102006055038B4 (de) 2006-11-22 2012-12-27 Siltronic Ag Epitaxierte Halbleiterscheibe sowie Vorrichtung und Verfahren zur Herstellung einer epitaxierten Halbleiterscheibe
CN101981664B (zh) * 2008-03-31 2013-08-28 Memc电子材料有限公司 蚀刻硅晶片边缘的方法
CN101572229A (zh) * 2008-04-28 2009-11-04 北大方正集团有限公司 多晶硅表面平坦化的方法
JP5584959B2 (ja) * 2008-05-07 2014-09-10 株式会社Ｓｕｍｃｏ シリコンウェーハの製造方法
JP5098873B2 (ja) 2008-07-30 2012-12-12 株式会社Ｓｕｍｃｏ 気相成長装置用のサセプタ及び気相成長装置
JP5092975B2 (ja) * 2008-07-31 2012-12-05 株式会社Ｓｕｍｃｏ エピタキシャルウェーハの製造方法
JP5635987B2 (ja) * 2008-08-28 2014-12-03 ケーエルエー−テンカー・コーポレーションＫｌａ−Ｔｅｎｃｏｒ Ｃｏｒｐｏｒａｔｉｏｎ 基板の表面の計測特性を評価するシステムおよび方法
DE102009030296B4 (de) * 2009-06-24 2013-05-08 Siltronic Ag Verfahren zur Herstellung einer epitaxierten Siliciumscheibe
US8952496B2 (en) * 2009-12-24 2015-02-10 Sumco Corporation Semiconductor wafer and method of producing same
JP5423384B2 (ja) * 2009-12-24 2014-02-19 株式会社Ｓｕｍｃｏ 半導体ウェーハおよびその製造方法
JP2011171450A (ja) * 2010-02-17 2011-09-01 Nuflare Technology Inc 成膜装置および成膜方法
US8324098B2 (en) * 2010-07-08 2012-12-04 National Semiconductor Corporation Via and method of forming the via with a substantially planar top surface that is suitable for carbon nanotube applications
JP5644401B2 (ja) 2010-11-15 2014-12-24 株式会社Sumco エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ
KR20120123207A (ko) * 2011-04-19 2012-11-08 실트로닉 아게 반도체 웨이퍼를 지지하는 서셉터 및 반도체 웨이퍼의 전면 상에 층을 증착하는 방법
JP5621702B2 (ja) * 2011-04-26 2014-11-12 信越半導体株式会社 半導体ウェーハ及びその製造方法
JP5834632B2 (ja) 2011-08-30 2015-12-24 株式会社Sumco サセプタ、該サセプタを用いた気相成長装置およびエピタキシャルウェーハの製造方法
JP5741497B2 (ja) * 2012-02-15 2015-07-01 信越半導体株式会社 ウェーハの両面研磨方法
US20130263779A1 (en) * 2012-04-10 2013-10-10 Memc Electronic Materials, Inc. Susceptor For Improved Epitaxial Wafer Flatness
JP6312976B2 (ja) * 2012-06-12 2018-04-18 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 半導体ウェーハの製造方法
JP6035982B2 (ja) * 2012-08-09 2016-11-30 株式会社Sumco エピタキシャルシリコンウェーハの製造方法およびエピタキシャルシリコンウェーハ
DE102013218880A1 (de) * 2012-11-20 2014-05-22 Siltronic Ag Verfahren zum Polieren einer Halbleiterscheibe, umfassend das gleichzeitige Polieren einer Vorderseite und einer Rückseite einer Substratscheibe
JP6013155B2 (ja) 2012-11-28 2016-10-25 大陽日酸株式会社 気相成長装置
CN103854965B (zh) * 2012-11-30 2017-03-01 中国科学院微电子研究所 平坦化处理方法
WO2015019706A1 (ja) * 2013-08-09 2015-02-12 株式会社フジミインコーポレーテッド 研磨済研磨対象物の製造方法および研磨用組成物キット
DE102015220924B4 (de) * 2015-10-27 2018-09-27 Siltronic Ag Suszeptor zum Halten einer Halbleiterscheibe mit Orientierungskerbe, Verfahren zum Abscheiden einer Schicht auf einer Halbleiterscheibe und Halbleiterscheibe
JP6838992B2 (ja) * 2017-02-21 2021-03-03 株式会社Ｓｃｒｅｅｎホールディングス 熱処理装置および熱処理方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120270407A1 (en) * 2011-04-19 2012-10-25 Siltronic Ag Susceptor for supporting a semiconductor wafer and method for depositing a layer on a front side of a semiconductor wafer

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