TWI550771B - Reference voltage generating device - Google Patents

Reference voltage generating device Download PDF

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TWI550771B
TWI550771B TW102101631A TW102101631A TWI550771B TW I550771 B TWI550771 B TW I550771B TW 102101631 A TW102101631 A TW 102101631A TW 102101631 A TW102101631 A TW 102101631A TW I550771 B TWI550771 B TW I550771B
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mos transistor
reference voltage
type nmos
doping region
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TW102101631A
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TW201344847A (zh
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Hideo Yoshino
Jun Osanai
Masayuki Hashitani
Yoshitsugu Hirose
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Sii Semiconductor Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883—Combination of depletion and enhancement field effect transistors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Automation & Control Theory (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Human Computer Interaction (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Control Of Electrical Variables (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

基準電壓產生裝置
本發明係關於在半導體積體電路內產生基準電壓之基準電壓產生裝置。
針對在以往之基準電壓產生裝置中所使用之電路，使用第2圖予以說明。
被連接成當作電流源而發揮功能之空乏型NMOS電晶體(D型NMOS)10，係對二極體連接之增強型NMOS電晶體(E型NMOS)20流入定電流。藉由該定電流，在E型NMOS20產生因應各電晶體之臨界值電壓及尺寸的基準電壓。在此，在D型NMOS10之閘極，被摻雜N型之雜質，在E型NMOS之閘極被摻雜P型之雜質(例如，參照專利文獻1(第2圖))。
[先行技術文獻] [專利文獻]
[專利文獻1]日本特開昭59-200320號公報
在此，近年來，隨著電子機器朝高精度化發展，在各個方面也要求控制該電子機器之IC的高精度化。例如，為了實現IC之電特性之高精度化，即使溫度變化，在IC內部，也要求基準電壓產生裝置可以高精度地產生基準電壓，即是基準電壓之溫度特性成為更平坦。
本發明係鑒於上述要求，其課題為提供具有更平坦之溫度特性的基準電壓產生裝置。
本發明為了解決上述課題，提供一種基準電壓產生裝置，該基準電壓產生裝置之特徵為具備：被連接成當作電流源而發揮功能，流通定電流之第一導電型空乏型MOS電晶體；和被二極體連接，具有與上述空乏型MOS電晶體之移動度相等的移動度，根據上述定電流產生基準電壓的第一導電型增強型MOS電晶體。
在本發明中，因第一導電型之空乏型NMOS電晶體和第一導電型之增強型NMOS電晶體之移動度大略相等，故該些溫度特性也大略相等，基準電壓之溫度特性變佳。
10‧‧‧空乏型NMOS電晶體(D型NMOS)
20‧‧‧增強型NMOS電晶體(E型NMOS)
11、21‧‧‧閘極電極
12、22‧‧‧閘極絕緣膜
13、23‧‧‧通道摻雜區域
14、24‧‧‧源極
15、25‧‧‧汲極
16、26‧‧‧井
29‧‧‧基板
第1圖為表示基準電壓產生裝置之剖面的圖示。
第2圖為表示基準電壓產生裝置之等效電路之圖示。
以下，針對本發明之實施型態，參照圖面予以說明。
首先，針對成為基準電壓產生裝置之基本的構成，使用第1圖所示之剖面圖而予以說明。
基準電壓產生裝置具備空乏型NMOS電晶體(D型NMOS)10，及增強型NMOS電晶體(E型NMOS)20。D型NMOS10之閘極電極11及源極14，被連接於基準電壓產生端子，汲極15被連接於電源端子。藉由如此之連接，D型NMOS10當作電流源發揮功能。E型NMOS20之閘極電極21及源極25，被連接於基準電壓產生端子，汲極24被連接於接地端子。即是，被二極體連接之E型NMOS20被串聯連接於D型NMOS10。因此，就以等效電路而言，成為第2圖所示之電路圖，與以往之電路等效。
為了形成D型NMOS10，首先在P型之基板29之表面形成P型之井16。然後，在井16之表面形成N型之通道摻雜區域13。接著，在通道摻雜區域13之上形成閘極絕緣膜12。之後，在閘極絕緣膜12上形成N型之閘極電極11。並且，以夾著閘極電極11及閘極絕緣膜12之下方之通道摻雜區域13之方式，在井16之表面形成N型之源極14及N型之汲極15。
D型NMOS10之閘極電極11之極性，與源極14、汲極15之極性相等，形成N型。如此一來，因N型之閘極 電極11和P型之井16之功函數的差大，基板表面被施加反轉方向之電場，故D型NMOS10之臨界值電壓變低至D型NMOS10成為空乏型之程度。並且，藉由N型之通道摻雜區域13，臨界值電壓下降，通道成為被形成在基板內部，形成嵌入通道。在此，朝閘極電極11及通道摻雜區域13的雜質注入，係被適當控制成D型NMOS10成為空乏型。
為了形成E型NMOS20，首先在P型之基板29之表面形成P型之井26。然後，在井26之表面形成N型之通道摻雜區域23。接著，在通道摻雜區域23之上形成閘極絕緣膜22。之後，在閘極絕緣膜22上形成P型之閘極電極21。並且，以夾著閘極電極21及閘極絕緣膜22之下方之通道摻雜區域23之方式，在井26之表面形成N型之源極24及N型之汲極25。
E型NMOS20之閘極電極21之極性，與源極24、汲極25之極性不同，形成P型。如此一來，P型之閘極電極21和P型之井26之功函數的差小，但是由於在基板表面被施加電洞蓄積方向之電場，故臨界值變高。於是，為了適當地降低臨界值，在P型之井26之表面形成包含N型之雜質的通道摻雜區域23。在此，朝閘極電極21及通道摻雜區域23的雜質注入，係被適當控制成E型NMOS20成為增強型。
並且，基板29並不限定於P型，即使為N型亦可。
被連接成電流源而發揮功能之D型NMOS10之源極 14，係對被二極體連接之E型NMOS20之閘極25流入定電流。藉由該定電流，在E型NMOS20之汲極25(基準電壓產生端子)產生基準電壓。
接著，針對基準電壓產生裝置所產生之基準電壓VREF之溫度特性予以說明。
並且在此，D型NMOS10之通道摻雜區域13係被通道摻雜成井16之表面之極性反轉的程度。此時，通道摻雜區域13和井16之雜質之極性不同，D型NMOS10成為嵌入通道。另外，因E型NMOS20為了降低臨界值在井區域表面具有含有與井26之極性不同的N型之雜質的通道摻雜區域23，故可想像同樣成為嵌入通道。
此時，在閘極之雜質之極性不同之D型NMOS10及E型NMOS20中，當形成相等基板29之表面以下之雜質的分布時，則可以期待產生深度相等的嵌入通道。隨此，D型NMOS10和E型NMOS20之溫度特性相等，可以期待基準電壓VREF之溫度特性變佳。
但是，本發明之發明者經多方面之實驗等的精心努力之結果，發現以下所示之現象。在D型NMOS10及E型NMOS20中，因閘極電極之雜質之極性不同，閘極電極和基板之間的功函數也不同。並且，通道導通用之閘極電壓(臨界值電壓)也不同，於通道導通時朝通道摻雜區域的電場也不同。具體而言，E型NMOS20之臨界值電壓較D型NMOS10之臨界值電壓高，由此使得朝E型NMOS20之通道的電場大。因此，載體在D型NMOS10中，係在 較基板29之表面下方之區域流動，在E型NMOS20中，係在基板29之表面附近流動。即是，可知D型NMOS10為嵌入通道型，但是E型NMOS20不成為嵌入通道型。此係意味著因E型NMOS20之載體受到界面準位之影響，故E型NMOS20之移動度變低，D型NMOS10和E型NMOS20之溫度特性不相等之意。即是，無得到良好的基準電壓VREF之溫度特性。
於是，在本發明中，在D型NMOS10及E型NMOS20中，藉由適當控制閘極之雜質濃度，或閘極絕緣膜之材質和閘極絕緣膜之膜厚和基板29之表面以下之雜質的分布等，使移動度成為相等。依此，D型NMOS10和E型NMOS20之溫度特性相等，可以期待基準電壓VREF之溫度特性變佳。並且，在此就移動度而言，可以使用可從電晶體之電流電壓特性容易求出的移動度。
[實施例1]
以E型NMOS20之閘極氧化膜22之介電常數高於D型NMOS10之閘極氧化膜12之介電常數之方式，適當選擇閘極氧化膜22及閘極氧化膜12之材質。如此一來，由此使得E型NMOS20之閘極氧化膜容量變大，往通道之電場變小，故移動度變高。當預期該效果，而使D型NMOS10和E型NMOS20之移動度成為大略相等之時，該些溫度特性也大略成為相等，可使基準電壓VREF之溫度特性成為平坦。
[實施例2]
將E型NMOS20之閘極氧化膜22形成比D型NMOS10之閘極氧化膜12薄。如此一來，由此使得E型NMOS20之閘極氧化膜容量變大，往通道之電場變小，故移動度變高。當預期該效果，而使D型NMOS10和E型NMOS20之移動度成為大略相等之時，該些溫度特性也大略成為相等，可使基準電壓VREF之溫度特性成為平坦。
[實施例3]
將E型NMOS20之通道摻雜區域23之雜質設為磷，將D型NMOS10之通道摻雜區域13之雜質設為砷。如此一來，因磷之原子半徑小於砷之原子半徑，故磷之平均自由工程較砷之平均自由工程長，由此使得E型NMOS20之移動度變高。當預期該效果，而使D型NMOS10和E型NMOS20之移動度成為大略相等之時，該些溫度特性也大略成為相等，可使基準電壓VREF之溫度特性成為平坦。
並且，若通道摻雜區域23之雜質主要為磷，通道摻雜區域13之雜質主要為砷即可。例如，即使將通道摻雜區域23之雜質設為磷，將通道摻雜區域13之雜質設為砷及磷亦可。再者，即使將通道摻雜區域23之雜質設為砷及磷，將通道摻雜區域13之雜質設為砷亦可。再者，即使將通道摻雜區域23之雜質設為砷及磷，將通道摻雜區 域13之雜質設為砷亦可。此時，藉由適當控制被摻雜之砷及磷之量，使D型NMOS10和E型NMOS20之移動度成為相等。
再者，即使適當分割通道摻雜區域23，設置摻雜磷之磷區域和摻雜砷之砷區域亦可。再者，即使適當分割通道摻雜區域13亦可。再者，即使適當分割通道摻雜區域23及通道摻雜區域13之雙方亦可。即使將通道摻雜區域23及通道摻雜區域13在閘極長方向分割亦可，且在閘極寬方向分割亦可。此時，藉由適當設置磷及砷區域，使D型NMOS10和E型NMOS20之移動度成為相等。
[實施例4]
將E型NMOS20之井26之雜質濃度形成比D型NMOS10之井16之雜質濃度薄。如此一來，由此使得在E型NMOS20之通道的雜質散亂之影響變少，移動度變高。當預期該效果，而使D型NMOS10和E型NMOS20之移動度成為大略相等之時，該些溫度特性也大略成為相等，可使基準電壓VREF之溫度特性成為平坦。
以上所說明之實施型態可適當組合。
10‧‧‧空乏型NMOS電晶體(D型NMOS)
20‧‧‧增強型NMOS電晶體(E型NMOS)
11、21‧‧‧閘極電極
12、22‧‧‧閘極絕緣膜
13、23‧‧‧通道摻雜區域
14、24‧‧‧源極
15、25‧‧‧汲極
16、26‧‧‧井
29‧‧‧基板

Claims (5)

  1. 一種基準電壓產生裝置，其特徵為具備：流通定電流的第一導電型之空乏型MOS電晶體，和第一導電型之增強型MOS電晶體，其係被二極體連接，具有與上述空乏型MOS電晶體之移動度相等的移動度，根據上述定電流產生基準電壓，上述增強型MOS電晶體之井的雜質濃度較上述空乏型MOS電晶體之井的雜質濃度薄。
  2. 如申請專利範圍第1項所記載之基準電壓產生裝置，其中上述增強型MOS電晶體之閘極氧化膜之介電常數高於上述空乏型MOS電晶體之閘極氧化膜之介電常數。
  3. 如申請專利範圍第1項所記載之基準電壓產生裝置，其中上述增強型MOS電晶體之閘極氧化膜較上述空乏型MOS電晶體之閘極氧化膜薄。
  4. 如申請專利範圍第1項所記載之基準電壓產生裝置，其中上述增強型MOS電晶體之通道摻雜區域之主要雜質的原子半徑，小於上述空乏型MOS電晶體之通道摻雜區域之主要雜質的原子半徑。
  5. 如申請專利範圍第4項所記載之基準電壓產生裝置，其中上述增強型MOS電晶體之通道摻雜區域之主要雜質 物為磷，上述空乏型MOS電晶體之通道摻雜區域之主要雜質為砷。
TW102101631A 2012-02-13 2013-01-16 Reference voltage generating device TWI550771B (zh)

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JP2012028733A JP5959220B2 (ja) 2012-02-13 2012-02-13 基準電圧発生装置

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JP6805049B2 (ja) * 2017-03-31 2020-12-23 エイブリック株式会社 基準電圧発生装置
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TWI634661B (zh) * 2017-07-31 2018-09-01 旺宏電子股份有限公司 半導體結構
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US9213415B2 (en) 2015-12-15
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KR102030982B1 (ko) 2019-10-11
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