TWI550768B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TWI550768B
TWI550768B TW103144813A TW103144813A TWI550768B TW I550768 B TWI550768 B TW I550768B TW 103144813 A TW103144813 A TW 103144813A TW 103144813 A TW103144813 A TW 103144813A TW I550768 B TWI550768 B TW I550768B
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Taiwan
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conductive
subset
substrate
pillars
conductive pillars
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TW103144813A
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TW201528432A (zh
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梁裕民
吳俊毅
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台灣積體電路製造股份有限公司
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    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
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Description

半導體裝置及其形成方法
本揭露是有關於一種半導體裝置及半導體裝置形成方法。
在跡線上接合(Bond-on-Trace；BoT)的製程中，單一(singulated)積體電路(integrated circuit；IC)晶片可被翻轉(flipped)且被連接至形成於其它基材上的接合墊部分。跡線的一子集合，亦稱作跳線(skip lines)，包含於此些接合墊之間延伸的跡線，例如用於扇出(fan-out)的目的。因此，跡線間距小於接合墊間距。然而，這會不小心造成焊料接合與相鄰跡線的橋接連接(bridging connections)，以及當跡線間距降至一般測試探針的直徑之下時使探針測試具過度挑戰性。
本揭露引進一種方法，此方法包含從載板(carrier)分離基材，其中附加的基材形成於載板上。被分離的基材包含導電層和多個導電柱，此導電層在基材之頂部表面上，且此些導電柱中之每一者從基材之底部表面延伸並穿過基材至導電層。突起凸塊墊係藉由選擇性移除在此些 導電柱之第一子集合之外的導電層來形成在此些導電柱之第一子集合上。
本揭露亦引進一種裝置，此裝置包含基材和多個導電跡線(conductive traces)，此些導電跡線設置在基材之第一側上。多個導電柱(conductive pillars)從基材的第二側延伸而穿過基材至此些導電跡線之對應多者。多個凸塊墊(bump pads)從此些導電跡線之第一子集合突出，而此些導電跡線之第二子集合之每一者被凹陷至基材之第一側中。
本揭露亦引進一種方法，此方法包含提供晶粒和基材，其中晶粒包含至少一積體電路晶片，且基材包含第一子集合和一第二子集合之多個導電柱，此些導電柱係延伸而穿過基材。此些導電柱之第一子集合中之每一者包含從基材之表面突起之突起凸塊墊，且此些導電柱之第二子集合中之每一者部分形成凹陷至基材之表面中之跡線(trace)。接著，晶粒經由多個導電凸塊來耦合該至該基材，此些導電凸塊中之每一者係於此些突起凸塊墊中之一者與晶粒之間延伸。
10、100、900‧‧‧裝置
12‧‧‧基材
14‧‧‧導電跡線
16‧‧‧側
18‧‧‧導電構件
20‧‧‧凸塊墊
22‧‧‧積體電路晶片
24、920‧‧‧導電凸塊
110‧‧‧積疊層
112‧‧‧第一側
114‧‧‧第二側
120‧‧‧載體基材
122‧‧‧金屬層
124‧‧‧絕緣層
130‧‧‧介電層
140‧‧‧金屬化層
150、152、154‧‧‧導電柱
155‧‧‧接合墊
156‧‧‧導電表面
210、510‧‧‧光阻光罩
220、520‧‧‧光阻層
230‧‧‧突起凸塊墊
410‧‧‧阻焊料部分
810‧‧‧測試探針
910‧‧‧晶粒
915‧‧‧接合墊
d‧‧‧深度
D‧‧‧直徑
G1‧‧‧最小凸塊墊間距
G2‧‧‧最小跡線間距
G3‧‧‧最小凸塊間距
P‧‧‧柱間距
結合圖式來閱讀下面的詳細描述以最完整理解本揭露。需要強調的是，依據在工業上的標準實施，各種特徵未按照比例繪製。事實上，為了清楚討論，各種特徵的尺寸可任意增加或減少。
〔圖1〕係繪示依據本揭露之一或多個態樣之裝置的至少部分的剖面圖。
〔圖2〕係繪示依據本揭露之一或多個態樣之在製造的中間階段之裝置的至少部分的剖面圖。
〔圖3〕係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖2所示的裝置的剖面圖。
〔圖4〕係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖3所示的裝置的剖面圖。
〔圖5〕係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖4所示的裝置的剖面圖。
〔圖6〕係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖2所示的裝置的剖面圖。
〔圖7〕係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖6所示的裝置的剖面圖。
〔圖8〕係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖7所示的裝置的剖面圖。
〔圖9〕係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖5所示的裝置的剖面圖。
〔圖10〕係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖5所示的裝置的剖面圖。
可以理解的是，後續說明書提供許多不同實施例或範例，用以達成各實施例的不同特徵。後續描述的元件及配置的特定範例，係用來簡要說明本揭露。當然，這些只 是範例，並非用來限制本揭露。此外，本說明書中，在許多實例中可能重複標號和/或文字。這些重複的使用係以簡化和明確說明為目的，其本身並非意指多個實施例和/或討論的設置之間的關係，除非有特別註明作為意指一關係。另外，在後續說明中，第一特徵形成於第二特徵上，可能包括的實施例為第一特徵及第二特徵形成直接接觸，以及可能包括的實施例為額外的特徵可能形成介於第一及第二特徵之間，使得第一及第二特徵可能非直接接觸。
圖1係繪示依據本揭露之一或多個態樣之裝置10的至少部分的剖面圖。裝置10包含基材12和多個導電跡線14，此些導電跡線14設置於基材12的一側16上。導電構件(conductive members)18可從此些導電跡線14之對應者延伸至基材12中。每一凸塊墊(bump pads)20從此些導電跡線14之第一子集合中之一者突出。此些導電跡線14之第二子集合的每一者被凹陷至基材12之側16中。裝置10更可包含積體電路晶片22和多個導電凸塊24，此些導電凸塊24耦接至積體電路晶片22與凸塊墊20之對應多者之間。
圖2係繪示依據本揭露之一或多個態樣之如圖1所示的裝置10的一實施，在此指定為標號100。依據本揭露之一或多個態樣，裝置100繪示於圖2中，其為在製造的中間階段中。裝置100包含積疊層(build-up layers)110，此些積疊層110位於載體基材(carrier substrate)120的相對側上。載體基材120可包含無核心(coreless)基材， 例如可包含一或多個金屬層122，此些金屬層形成於絕緣層124的一側或兩側上。絕緣層124和/或載體基材120可包含單側或雙側之覆銅箔層壓板(copper clad laminate；CCL)、預浸漬體(prepreg)或Ajinomoto增層膜(ajinomoto build-up film)、紙、玻璃纖維、不織玻璃纖維、一或多個層之銅、鎳、鋁和/或其它材料、元件、和/或合成物。此一或多個金屬層122可包含一或多個層之銅、鎳、鋁和/或其它材料。
在其它的構件中，此些積疊層110可包含多個介電層130和金屬化層140。金屬化層140部分垂直對準而形成導電柱150。
此些介電層130可包含預浸漬體或Ajinomoto增層膜。或者(或此外)，此些介電層130可包含紙、玻璃纖維和/或不織玻璃纖維，此些介電層130之一或多者可藉由多層貼合(lamination)而採用。或者(或此外)，此些介電層130可包含二氧化矽、氮化矽、氮氧化矽、氧化物、含氮氧化物、氧化鋁、氧化鑭、氧化鉿、氧化鋯、氮氧化給、上述組合和/或其它材料。此些介電層130可藉由濺鍍(sputtering)、旋轉塗佈(spin-on coating)、化學氣相沉積(chemical vapor deposition；CVD)、低壓化學氣相沉積(low-pressure CVD)、快速升溫化學氣相沉積(rapid thermal CVD)、原子層化學氣相沉積(atomic layer CVD)和/或電漿增強型化學氣相沉積(plasma enhanced CVD)來形成，其可利用矽酸四乙酯(tetraethyl orthosilicate)和氧作為前驅物。此些介電層130可藉由氧化製程，例如在包含氧化物、水、氧化氮或上述組合之周遭環境中的溼式或乾式熱氧化(thermal oxidation)，和/或其它製程來形成。此些介電層130之製造亦可包含在其它製程中的化學機械研磨(chemical-mechanical polishing)或平坦化(以下共同稱為CMP)、等向性蝕刻(isotropic etching)和/或非等向性蝕刻(anisotropic etching)。此些介電層130可被形成至介於大約8埃(angstroms)與大約200埃之間的厚度，雖然其它厚度亦在本揭露的範圍中。
金屬化層140可包含銅、鈦、鋁、鎳、金、上述合金和/或組合之一或多者，和/或其它材料。此些金屬化層140可藉由鍍覆(plating)來形成，可能至介於大約4微米(microns)與大約25微米之間的厚度。或者(或此外)，此些介電層130可藉由化學氣相沉積和/或其它製程來形成，且可具有介於大約8埃(angstroms)與大約200埃之間的厚度，雖然其它厚度亦在本揭露的範圍中。
此些導電柱150和/或其接合墊(bond pads)155可具有介於大約150微米與大約400微米之間的直徑和/或其它橫向尺寸。每一接合墊155可為球型陣列(ball grid array；BGA)墊，例如可後續被利用在形成與母板(mother board)印刷電路板和/或其它印刷電路板、印刷線路板(printed wiring board；PWB)、印刷電路組件(printed circuit assembly；PCA)、印刷電路板組件(PCB CCA)、背板組件(backplane assembly)和/或裝置的互連。柱間距P或介於相鄰的導電柱150和/或接合墊155之間的橫向偏移可介於大約300微米與大約500微米之間。
圖3係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖2所示的裝置100的剖面圖，其中積疊層110的區段已從載體基材120移除。此些積疊層110的區段之一者未繪示於圖3中，雖然此僅為了簡化下列討論，且熟習此技藝者可輕易認定此些積疊層110的兩個區段可根據本揭露之一或多個態樣。積疊層110可藉由繞線(routing)、熔化(melting)、機械力、蝕刻和/或其它製程而從載體基材120移除。
接著，光阻層可在積疊層110的一或兩側上塗佈、暴露和顯影。舉例而言，光阻光罩210可形成於積疊層110的第一側112上，且光阻層212可實質覆蓋積疊層110的第二側114。導電柱150可被分為第一子集合和第二子集合。在圖3中，第一子集合包含導電柱152，且第二子集合包含導電柱154。第一子集合將包含多於如圖3所繪示的兩個導電柱152，且第二子集合將包含多於如圖3所繪示的一個導電柱154。
在積疊層110之第一側112上的光阻光罩210形成於第一子集合之每一導電柱152上，而第二子集合之導電柱154和在積疊層110之第一側112上的剩餘平面特徵可維持暴露至後續微影製程。光阻光罩210和光阻層220可包含化學增幅型光阻(chemically amplified photoresist) 或非化學增幅型光阻(non-chemically amplified photoresist)，且可為正型(positive-tone)或負型(negative tone)。光阻光罩210和光阻層220之處理可包含沉積製程，此沉積製程包含例如乾膜類(dry film type)光阻之多層貼合、旋轉塗佈、浸漬塗佈(dip coating)、刷塗(brush coating)和/或噴墨分配(ink-jetdispensing)等。後沉積固化步驟可被進行以移除溶劑和/或其它不要的構件，例如至介於大約攝氏40度至大約攝氏200度之間的溫度，其可用於介於大約10秒至大約10分鐘的固化時間。
圖4係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖3所示的裝置100的剖面圖，其中在第一子集合之導電柱152上的光阻光罩210已在蝕刻製程中被利用為遮罩。此蝕刻製程被利用以移除金屬化層140的最外側部分，此些金屬化層140的最外部分未被光阻光罩210和光阻層220保護。因此，在積疊層110之第一側112上，最外側金屬化層140被移除，而降至最外側介電層130。然而，第二子集合之導電柱154上的最外側金屬化層140之蝕刻以一充分時間繼續，藉以將此些導電柱154之導電表面156凹陷在最外側介電層130的外部表面中。第二子集合之導電柱154之導電表面156因而形成凹陷跡線之部分，而第一子集合之每一導電柱152之標記部分形成突起凸塊墊(protrusion bump pad)230。在凹陷跡線上且在環繞之介電層130的表面下之凹陷的深度d可小於大約7微米，例如大約為4微米，雖然其它厚度亦在本揭露的範圍中。
圖5係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖4所示的裝置100的剖面圖，其中光阻光罩210和光阻層220已被移除，且阻焊料(solder resist)部分410已藉由傳統方式來形成。阻焊料部分410可包含耐熱性(heat-resistant)塗佈材料，且可幫助保護下方的層。
其它形成突起凸塊墊230和凹陷跡線的方法亦在本揭露的範圍中。一種此類的範例係繪示於圖6至圖8中。圖6係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖2所示的裝置100的剖面圖。如上，積疊層110已從載體基材120移除。接著，光阻層可在積疊層110的一或兩側上塗佈、暴露和顯影。舉例而言，光阻光罩510可形成於積疊層110的第一側112上，且光阻層520可實質覆蓋積疊層110的第二側114。在積疊層110之第一側112上的光阻光罩510可實質覆蓋整個第一側112，包含在第二子集合之每一導電柱154上，但不包含在第一子集合之導電柱152上，此些導電柱152維持暴露至後續製程。
圖7係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖6所示的裝置100的剖面圖，其中光阻光罩510已在金屬化製程中被利用為遮罩。此金屬化製程被利用以增加金屬至第一子集合之暴露導電柱152。藉由金屬化製程來增加的材料可包含銅、鈦、鋁、鎳、金、上述合金和/或組合之一或多者，和/或其它材料。此金屬化製程可藉由電鍍(electroplating)、無電鍍(electroless plating)、化學氣相沉積、磊晶成長(epitaxial growth)和/或其它 製程來形成，且可增加材料至導電柱152至介於大約5微米與大約50埃之間的厚度，雖然其它厚度亦在本揭露的範圍中。
圖8係繪示依據本揭露之一或多個態樣之在製造的後續階段之圖7所示的裝置100的剖面圖，其中光阻光罩510和光阻層520已被移除。圖8亦反映蝕刻製程的結果，此蝕刻製程對第一子集合之導電柱152、第二子集合之導電柱154和最外側金屬化層140具選擇性。舉例而言，最外側金屬化層140被移除，而降至最外側介電層130，其包含至足夠將導電柱154之導電表面156凹陷在最外側介電層130的外部表面中之程度。如上，第二子集合之導電柱154之導電表面156形成凹陷跡線之部分，而第一子集合之每一導電柱152之現今突起部分形成突起凸塊墊230。導電柱(突起柱)之頂部亦在此製程中被回蝕刻(etched back)。因此，如圖7所繪示之增加金屬化的製程步驟應被調整至確保突起柱維持足夠高度，即使在此後續蝕刻步驟之後。附加的製程可接著發生，例如以形成阻焊料部分和/或在其它方面達成如圖5所繪示之實施例。如圖8所示，介於相鄰凸塊墊(不包含凹陷跡線)之間的橫向偏移(即最小凸塊墊間距G1)大於介於相鄰導電跡線(包含凹陷跡線)之間的橫向偏移(即最小跡線間距G2)。最小凸塊墊間距G1可至少為或大於最小跡線間距G2的兩倍。在一些實施例中，最小跡線間距G2可小於大約50微米。
圖9係繪示如圖5所示之裝置100的剖面圖，其中使測試探針810與第一子集合之導電柱132的突起凸塊墊152中之一者接觸。測試探針810的頂端可具有直徑D，此直徑D可實質大於柱間距P。舉例而言，若非較小，則柱間距P可大約為40微米，且若非特別大，則直徑D可大約為30微米。然而，因為第二子集合之導電柱154被凹陷，此些導電柱154藉由測試探針810相對於第一子集合之導電柱152未對準(misalignment)而不被縮短。
圖10係繪示依據本揭露之一或多個態樣之裝置900的至少部分的剖面圖。裝置900包含如圖5所示的裝置100、晶粒910和多個導電凸塊920，此些導電凸塊920耦接至積體電路晶片與此些凸塊墊之對應多者之間。晶粒910可包含一或多個積體電路晶片、封裝體和類似元件。導電凸塊920可包含焊料、金、導電膠(conductive pasta)和/或其它電性導電材料。晶粒910可包含接合墊(pads)915，此些接合墊915被配置以在藉由導電凸塊920來耦接至突起凸塊墊230之前與突起凸塊墊230對準。介於相鄰導電凸塊之間的橫向偏移(即最小凸塊間距G3)可小於大約110微米。
前述說明摘要數個實施例的特徵，使得熟習此技藝者可以更了解本揭露的態樣。熟習此技藝者應知其可以輕易地利用本揭露作為一基礎，以進行設計或修改其他製程及結構，用以達成相同目的，和/或達成與在此提出實施例的相同態樣。熟習此技藝者也應可理解，這些等效的結構並 不脫離本揭露的精神與範圍，而且在不脫離本揭露的精神與範圍下，可以做各種變更，替代及潤飾。
當本發明以參考所示實施例來描述時，此描述並非意在以一限制意義來解釋。對熟習此技藝者而言，根據參考本說明書之所示實施例的各種修改和組合，以及本發明之其它實施例是明顯的。因此，附加的請求項包含任何此類的修改和實施例。
10‧‧‧裝置
12‧‧‧基材
14‧‧‧導電跡線
16‧‧‧側
18‧‧‧導電構件
20‧‧‧導電構件
22‧‧‧積體電路晶片
24‧‧‧導電凸塊

Claims (10)

  1. 一種半導體裝置，包含：一基材；複數個導電跡線(conductive traces)，設置在該基材之一側上；複數個導電構件(conductive members)，每一該些導電構件從該些導電跡線之一對應者延伸至該基材中；以及複數個凸塊墊(bump pads)，每一該些凸塊墊從該些導電跡線之一第一子集合中之一者突出，其中該些導電跡線之一第二子集合被凹陷至該基材之該側中。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該側係一第一側，且該些導電構件中之複數者係導電柱(conductive pillar)，該些導電柱從該基材之一第二側延伸至設置在該基材之該第一側上之該些導電跡線之對應多者。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該些導電跡線彼此橫向偏移一最小跡線間距，該些凸塊墊彼此橫向偏移一最小凸塊墊間距，且該最小凸塊墊間距實質大於該最小跡線間距或為該最小跡線間距之至少大約兩倍。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該些導電跡線彼此橫向偏移一最小跡線間距，該最小跡線間距小於大約50微米(microns)，該些凸塊墊彼此橫向偏移一最小凸塊墊間距，該最小凸塊墊間距係該最小跡線間距之大約兩倍。
  5. 如申請專利範圍第1項所述之半導體裝置，更包含：一積體電路晶片，以及；複數個導電凸塊(conductive bumps)，耦接至該積體電路晶片與該些凸塊墊之對應複數者之間，該些導電凸塊彼此橫向偏移一最小凸塊間距，該最小凸塊間距小於大約110微米。
  6. 一種用以形成一半導體裝置之方法，包含：從一載板(carrier)分離一基材，其中一附加的基材形成於該載板上，其中該被分離的基材包含一導電層和複數個導電柱，該導電層在該基材之一頂部表面上，且該些導電柱中之每一者從該基材之一底部表面延伸並穿過該基材至該導電層；藉由選擇性移除在該些導電柱之一第一子集合之外的該導電層來形成一突起凸塊墊(protrusion bump pad)在該些導電柱之一第一子集合上；以及 藉由該些導電柱之該第一子集合中之每一者上來耦合該基材與一半導體晶粒封裝(semiconductor die package)。
  7. 如申請專利範圍第6項所述之方法，其中形成該突起凸塊墊在該些導電柱之該第一子集合包含：形成一光阻光罩(photoresist mask)在該些導電柱之一第一子集合中之每一者上但不在該些剩餘導電柱的該導電層上；以及蝕刻以移除在光阻光罩下面之外的該導電層；其中形成該光阻光罩在該些導電柱之該第一子集合中之每一者上但不在該剩餘導電柱的該導電層上包含：形成該光阻光罩在該些導電柱之該第一子集合中之每一者上但不在該導電層之該剩餘部分的該導電層上，或形成該光阻光罩在僅在該些導電柱之該第一子集合中之每一者上之該導電層上。
  8. 如申請專利範圍第7項所述之方法，其中蝕刻以移除該導電層係從非為該第一子集合之該些導電柱中之每一者上移除該導電層之一足夠的部分，以暴露凹陷至該基材之該頂部表面中之一導電表面，其中該導電層被蝕刻薄化後之一部分包含該導電表面，且該導電表面係非為該第一子集合之該些導電柱之一對應者。
  9. 如申請專利範圍第6項所述之方法，其中形成該突起凸塊墊在該些導電柱之該第一子集合上包含：形成一光阻光罩在該些導電柱之一第一子集合中之每一者上但不在該第一子集合之該些導電柱的該導電層上；增加一附加的導電材料至未被該光阻光罩所覆蓋之該導電層之該部分；移除該光阻光罩；以及蝕刻以從非為該第一子集合之部分之該些導電柱中之每一者上來移除該導電層之一足夠的部分，以暴露凹陷至該基材之該頂部表面中之一導電表面；其中該導電層之被該蝕刻薄化之一部分包含該導電表面，且該導電表面係非為該第一子集合之該些導電柱之一對應者。
  10. 一種用以形成一半導體裝置之方法，包含：提供一晶粒，該晶粒包含至少一積體電路晶片；提供一基材，該基材包含第一子集合和一第二子集合之複數個導電柱，該些導電柱係延伸而穿過該基材，其中該些導電柱之該第一子集合中之每一者包含從該基材之一表面突起之一突起凸塊墊，且其中該些導電柱之該第二子集合中之每一者部分形成凹陷至該基材之該表面中之一跡線(trace)；以及 經由複數個導電凸塊來耦合該晶粒至該基材，該些導電凸塊中之每一者係於該些突起凸塊墊中之一者與該晶粒之間延伸。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9275967B2 (en) * 2014-01-06 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9418928B2 (en) * 2014-01-06 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
JP2017050497A (ja) * 2015-09-04 2017-03-09 株式会社東芝 半導体装置およびその製造方法
US9953911B2 (en) * 2016-07-01 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and method
CN111133574A (zh) * 2017-12-29 2020-05-08 英特尔公司 微电子组件
US12106876B2 (en) 2018-09-18 2024-10-01 Verily Life Sciences Llc Monolithic lead assembly and methods of microfabricating a monolithic lead assembly
US11395923B2 (en) * 2018-11-16 2022-07-26 Verily Life Sciences Llc Branched proximal connectors for high density neural interfaces
CN112165767B (zh) * 2020-10-27 2021-12-07 惠州市特创电子科技股份有限公司 多层线路板以及移动通讯装置
US20220199427A1 (en) * 2020-12-23 2022-06-23 Intel Corporation Multi-step isotropic etch patterning of thick copper layers for forming high aspect-ratio conductors
US20240130040A1 (en) * 2022-10-12 2024-04-18 Innolux Corporation Conductive film and test component

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087251A (en) * 1998-10-30 2000-07-11 United Microelectronics Corp. Method of fabricating a dual damascene structure
US20020048944A1 (en) * 1999-11-02 2002-04-25 Tang Sanh D. Multi-level circuit structure
US20090121349A1 (en) * 2007-11-09 2009-05-14 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2940432B2 (ja) * 1995-04-27 1999-08-25 ヤマハ株式会社 半導体装置とその製造方法
JP3346985B2 (ja) * 1996-06-20 2002-11-18 東芝マイクロエレクトロニクス株式会社 半導体装置
US6118180A (en) * 1997-11-03 2000-09-12 Lsi Logic Corporation Semiconductor die metal layout for flip chip packaging
US6358831B1 (en) * 1999-03-03 2002-03-19 Taiwan Semiconductor Manufacturing Company Method for forming a top interconnection level and bonding pads on an integrated circuit chip
JP3606769B2 (ja) * 1999-07-13 2005-01-05 新光電気工業株式会社 半導体装置
US6350386B1 (en) 2000-09-20 2002-02-26 Charles W. C. Lin Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly
JP2002151618A (ja) * 2000-11-15 2002-05-24 Nippon Avionics Co Ltd ビルドアッププリント配線板およびその製造方法
US6388322B1 (en) 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
EP1386353A2 (en) * 2001-05-01 2004-02-04 Koninklijke Philips Electronics N.V. Method of manufacturing interconnections in a semiconductor device
US6348398B1 (en) * 2001-05-04 2002-02-19 United Microelectronics Corp. Method of forming pad openings and fuse openings
JP3910379B2 (ja) * 2001-06-12 2007-04-25 インターナショナル・ビジネス・マシーンズ・コーポレーション ボール・グリッド・アレイ・モジュール用の多層基板の製造方法
JP3594583B2 (ja) 2002-01-10 2004-12-02 Ｎｅｃエレクトロニクス株式会社 エッチング装置及びその温度制御方法
TWI221664B (en) 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
US7112524B2 (en) * 2003-09-29 2006-09-26 Phoenix Precision Technology Corporation Substrate for pre-soldering material and fabrication method thereof
WO2005048311A2 (en) 2003-11-10 2005-05-26 Chippac, Inc. Bump-on-lead flip chip interconnection
US20060216860A1 (en) * 2005-03-25 2006-09-28 Stats Chippac, Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
TWI225670B (en) 2003-12-09 2004-12-21 Advanced Semiconductor Eng Packaging method of multi-chip module
JP4108643B2 (ja) 2004-05-12 2008-06-25 日本電気株式会社 配線基板及びそれを用いた半導体パッケージ
JP3961537B2 (ja) 2004-07-07 2007-08-22 日本電気株式会社 半導体搭載用配線基板の製造方法、及び半導体パッケージの製造方法
JP4708148B2 (ja) * 2005-10-07 2011-06-22 ルネサスエレクトロニクス株式会社 半導体装置
TW200906260A (en) * 2007-07-20 2009-02-01 Siliconware Precision Industries Co Ltd Circuit board structure and fabrication method thereof
JP5314873B2 (ja) 2007-10-05 2013-10-16 ルネサスエレクトロニクス株式会社 半導体装置
GB0817831D0 (en) 2008-09-30 2008-11-05 Cambridge Silicon Radio Ltd Improved packaging technology
US8659172B2 (en) * 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
US8030776B2 (en) * 2009-10-07 2011-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit with protective structure
US9607936B2 (en) 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
JP5544872B2 (ja) * 2009-12-25 2014-07-09 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP2011138868A (ja) * 2009-12-28 2011-07-14 Ngk Spark Plug Co Ltd 多層配線基板
JP5566720B2 (ja) 2010-02-16 2014-08-06 日本特殊陶業株式会社 多層配線基板及びその製造方法
KR101077304B1 (ko) * 2010-03-08 2011-10-26 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US8127979B1 (en) 2010-09-25 2012-03-06 Intel Corporation Electrolytic depositon and via filling in coreless substrate processing
US20120098120A1 (en) 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Centripetal layout for low stress chip package
US8835217B2 (en) 2010-12-22 2014-09-16 Intel Corporation Device packaging with substrates having embedded lines and metal defined pads
US8344493B2 (en) * 2011-01-06 2013-01-01 Texas Instruments Incorporated Warpage control features on the bottomside of TSV die lateral to protruding bottomside tips
US20120326299A1 (en) * 2011-06-24 2012-12-27 Topacio Roden R Semiconductor chip with dual polymer film interconnect structures
US20130249076A1 (en) * 2012-03-20 2013-09-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces
US8981559B2 (en) * 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
TWI562295B (en) * 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US9177899B2 (en) * 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
TWM462949U (zh) 2013-05-16 2013-10-01 Unimicron Technology Corp 封裝基板
US8772951B1 (en) * 2013-08-29 2014-07-08 Qualcomm Incorporated Ultra fine pitch and spacing interconnects for substrate
US9275967B2 (en) 2014-01-06 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9418928B2 (en) 2014-01-06 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9508637B2 (en) 2014-01-06 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
KR102254874B1 (ko) * 2014-05-30 2021-05-24 삼성전기주식회사 패키지 기판 및 패키지 기판 제조 방법
TWI570816B (zh) * 2014-09-26 2017-02-11 矽品精密工業股份有限公司 封裝結構及其製法
KR102468796B1 (ko) * 2015-08-28 2022-11-18 삼성전자주식회사 인쇄 회로 기판 및 이를 포함하는 반도체 패키지
KR101706470B1 (ko) * 2015-09-08 2017-02-14 앰코 테크놀로지 코리아 주식회사 표면 마감층을 갖는 반도체 디바이스 및 그 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087251A (en) * 1998-10-30 2000-07-11 United Microelectronics Corp. Method of fabricating a dual damascene structure
US20020048944A1 (en) * 1999-11-02 2002-04-25 Tang Sanh D. Multi-level circuit structure
US20090121349A1 (en) * 2007-11-09 2009-05-14 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same

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