CN104766850B - 用于迹线上接合工艺的凸块焊盘 - Google Patents

用于迹线上接合工艺的凸块焊盘 Download PDF

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CN104766850B
CN104766850B CN201410437081.1A CN201410437081A CN104766850B CN 104766850 B CN104766850 B CN 104766850B CN 201410437081 A CN201410437081 A CN 201410437081A CN 104766850 B CN104766850 B CN 104766850B
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conductive
subset
substrate
conductive column
trace
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CN104766850A (zh
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梁裕民
吴俊毅
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种管芯和一种衬底。该管芯包括至少一个集成电路芯片，且该衬底包括至少部分延伸穿过该衬底的导电柱的第一子集和第二子集。导电柱的第一子集的每个都包括突出于衬底的表面的凸块焊盘，且导电柱的第二子集的每个都部分形成凹进衬底的表面中的迹线。通过多个导电凸块将管芯连接到衬底，多个导电凸块的每个都延伸到凸块焊盘的一个焊盘和管芯之间。

Description

用于迹线上接合工艺的凸块焊盘
技术领域
本发明涉及半导体领域，更具体地，涉及用于迹线上接合工艺的凸块焊盘。
背景技术
在迹线上接合(BoT)工艺中，将单一的集成电路(IC)芯片翻转且连接到形成在另一个衬底上的迹线的接合焊盘部分。迹线的子集(也称为skin lines)包括诸如为了扇出的目的延伸到接合焊盘部分之间的迹线。这样，迹线间距小于接合焊盘间距。然而，这将导致焊接接缝(solder bonds)无意间与邻近的迹线桥接，且由于迹线间距降到普通测试探针的直径以下，使探针测试过于富有挑战性。
发明内容
为解决上述问题，本发明提供了一种装置，包括：衬底；多个导电迹线，设置在衬底的侧上；多个导电元件，导电元件的每个都从导电迹线的相应的一个迹线延伸到衬底中；以及多个凸块焊盘，凸块焊盘的每个突出于导电迹线的第一子集的一个，其中，将导电迹线的第二子集在衬底的侧内开槽。
其中，侧是第一侧，且多个导电元件是导电柱，导电柱延伸到设置在衬底的第二侧上的相应导电部件。
其中，多个导电迹线彼此横向偏移最小的迹线间距，多个凸块焊盘彼此横向偏移最小的凸块焊盘间距，最小的凸块焊盘间距基本上大于最小的迹线间距。
其中，多个导电迹线彼此横向偏移最小的迹线间距，多个凸块焊盘彼此横向偏移最小的凸块焊盘间距，最小的凸块焊盘间距是最小的迹线间距的至少约两倍。
其中，多个导电迹线彼此横向偏移最小的迹线间距，最小的迹线间距小于约50微米，且多个凸块焊盘彼此横向偏移最小的凸块焊盘间距，最小的凸块焊盘间距是最小的迹线间距的约两倍。
该装置进一步包括：集成电路芯片；以及多个导电凸块，连接在集成电路芯片和凸块焊盘的相应焊盘之间。
其中，多个导电凸块彼此横向偏移最小的凸块间距，最小的凸块间距小于约110微米。
此外，还提供了一种方法，包括：从载体分离衬底，载体上形成有额外的衬底，其中，分离的衬底包括位于衬底的顶面上的导电层和多个导电柱，多个导电柱的每个都从衬底的底面延伸穿过衬底到达导电层；以及通过选择性去除导电层，除了从导电柱的第一子集的每个上方去除导电层，在导电柱的第一子集的每个上方形成凸块焊盘。
其中，在导电柱的第一子集的每个上方形成凸块焊盘包括：在导电柱的第一子集的每个上方而不是剩余的导电柱上方的导电层上形成光刻胶掩模；以及蚀刻以去除导电层，除了光刻胶掩模下方的导电层。
其中，在导电柱的第一子集的每个上方而不是剩余的导电柱上方的导电层上形成光刻胶掩模包括在导电柱的第一子集的每个上方而不是导电层的剩余部分上方的导电层上形成光刻胶掩模。
其中，在导电柱的第一子集的每个上方而不是剩余的导电柱上方的导电层上形成光刻胶掩模包括仅在导电柱的第一子集的每个上方的导电层上形成光刻胶掩模。
其中，以去除导电层的蚀刻从不是第一子集的部分的导电柱的每个上方去除导电层的足够的部分，从而暴露凹进到衬底的顶面中的导电面。
其中，通过蚀刻减薄的导电层的部分包括导电面。
其中，导电面是不属于第一子集的部分的导电柱的相应导电柱的导电面。
其中，在导电柱的第一子集的每个上方形成凸块焊盘包括：在不是第一子集的每个导电柱上方的导电层上形成光刻胶掩模；将额外的导电材料增加到没有被光刻胶掩模覆盖的导电层的部分；去除光刻胶掩模；以及蚀刻以从不是第一子集的部分的导电柱的每个上方去除导电层的足够的部分，以暴露在衬底的顶面内开槽的导电面。
其中，通过蚀刻减薄的导电层的部分包括导电面。
其中，导电面是不属于第一子集的部分的导电柱的相应导电柱的导电面。
该方法还包括通过将与导电柱的第一子集的每个上方的凸块焊盘接触的焊料凸块回流焊连接衬底与半导体管芯封装件。
该方法还包括使用测试探针接触凸块焊盘的一个焊盘。
此外，还提供了一种方法，包括：提供管芯，管芯包括至少一个集成电路芯片；提供衬底，衬底包括延伸穿过衬底的导电柱的第一子集和第二子集，其中，导电柱的第一子集的每个都包括突出于衬底的表面的突出焊盘，且导电柱的第二子集的每个都部分形成了凹进衬底的表面的迹线；以及通过多个导电凸块将管芯连接到衬底，多个导电凸块的每个都延伸到凸块焊盘的一个焊盘和管芯之间。
附图说明
当结合附图进行阅读时，通过以下详细描述可以最佳理解本发明。应该强调的是，根据工业中的标准实践，各个部件未按比例绘出且仅用于示出的目的。事实上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据本发明的一个或多个方面的装置的至少一部分的截面图。
图2是根据本发明的一个或多个方面的在制造的中间阶段的装置的至少一部分的截面图。
图3是根据本发明的一个或多个方面的图2中示出的装置在随后的制造阶段中的截面图。
图4是根据本发明的一个或多个方面的图3中示出的装置在随后的制造阶段中的截面图。
图5是根据本发明的一个或多个方面的图4中示出的装置在随后的制造阶段中的截面图。
图6是根据本发明的一个或多个方面的图2中示出的装置在随后的制造阶段中的截面图。
图7是根据本发明的一个或多个方面的图6中示出的装置在随后的制造阶段中的截面图。
图8是根据本发明的一个或多个方面的图7中示出的装置在随后的制造阶段中的截面图。
图9是根据本发明的一个或多个方面的图5中示出的装置在随后的制造阶段中的截面图。
图10是根据本发明的一个或多个方面的图5中示出的装置在随后的制造阶段中的截面图。
具体实施方式
应该理解，本发明的以下内容提供了许多用于实施不同实施例的不同特征的不同实施例或实例。以下描述组件和配置的具体实例以简化本发明。当然，这仅仅是实例，并不用于限制本发明。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简明和清楚，而且其本身没有指定所述各种实施例和/或结构之间的关系。而且，在以下描述中，第一部件形成在第二部件上方或者上可以包括第一部件和第二部件直接接触的实施例，还可以包括在第一部件和第二部件之间形成有额外的部件，从而使得第一部件和第二部件不直接接触的实施例。
图1是根据本发明的一个或多个方面的在制造的中间阶段中装置10的至少一部分的截面图。装置10包括衬底12和设置在衬底的侧16上的多个导电迹线14。导电部件18可以从导电迹线14的相应迹线延伸到衬底12中。凸块焊盘20的每个都从导电迹线14的第一子集中的一个迹线突出。将位于衬底12的侧16中的导电迹线14的第二子集中的每个迹线开槽。装置10还可以包括集成电路芯片22和多个连接到集成电路芯片和凸块焊盘20的相应焊盘之间的导电凸块24。
图2是图1中示出的装置10的实现的截面图，本文用参考标号100指定。根据本发明的一个或多个实施例的，在图2中将装置100描绘为处于制造的中间阶段。装置100包括位于载体衬底120的相对两侧上的组合层110。载体衬底120可以包括无核衬底，诸如可以包括形成在绝缘层124的一侧或相对两侧上的一层或多层金属层122。绝缘层124和/或载体衬底120可以包括单面的或双面的覆铜板(CCL)，半固化材料或ajinomoto增层膜(ABF)，纸，玻璃纤维，无纺布玻璃织物，铜、镍、铝、和/或其他材料、元素和/或成分的一层或多层。一层或多层金属层122可以包括铜、镍、铝和/或其他材料的一层或多层。
在其他组件中，组合层110可以包括多个介电层130和金属化层140。将金属化层140的部分垂直对准以形成导电柱150。
介电层130可以包括半固化材料或ajinomoto增层膜(ABF)。可选地，或额外地，介电层130可以包括纸、玻璃纤维、和/或无纺布玻璃织物、可以采用层压的一种或多种材料。可选地，或额外地，介电层130可以包括氧化硅、氮化硅、氮氧化硅、氧化物、含氧化物的氮、氧化铝、氧化镧、氧化铪、氧化锆、氮氧化铪、它们的组合和/或其他材料。也许使用原硅酸四乙酯和氧气作为前体，可以通过溅射、旋涂、化学汽相沉积(CVD)、低压CVD、快速热CVD、原子层CVD、和/或等离子体增强CVD形成介电层130。也可以通过氧化工艺形成介电层130，诸如在包括氧、水、氧化氮、或它们的组合的周围环境中的湿或干热氧化，和/或其他工艺。在其他工艺中，介电层130的制造也可以包括化学机械抛光或平坦化(在此之后全部称为CMP)、各向同性蚀刻、和/或各向异性蚀刻。形成的介电层130的厚度可以在约8埃到200埃的范围内，尽管其他厚度也可以在本发明的范围内。
金属化层140可以包括铜、钛、铝、镍、金、合金和/或它们的组合的一种或多种和/或其他材料。可以使用喷镀形成金属化层140，也许其厚度在约4微米到约25微米的范围内。可选地，或额外地，可以使用CVD和/或其他工艺形成金属化层140，且其厚度在约8埃到约200埃的范围内，尽管其他厚度也可以在本发明的范围内。
导电柱150和/或其接合焊盘155的直径和/或其他横向尺寸在约150微米到约400微米的范围内。接合焊盘155的每个都可以是BGA(球栅阵列)焊盘，诸如可以随后在形成互连件中使用，互连件具有“母板”PCB(印刷电路板)和/或另一个PCB、PWB(印刷线路板)、PCA(印刷电路组件)、PCBA(PCB组件)、CCA(电路卡组件)、背板组件、和/或装置。柱间距P或相邻的导电柱150和/或接合焊盘155之间的横向偏移可以在约300微米和约500微米的范围内。
图3是根据本发明的一个或多个方面的图2中示出的装置100的截面图，其中，组合层110的部分已经从载体衬底120去除。根据本发明的一个或多个方面，组合层110的部分的一个没有在图3中示出，尽管这仅是为了简化下文讨论的目的，但是本领域中的普通技术人员将易于认识到，组合层110的两部分都将可以进行处理。可以通过布线、融化、机械力、蚀刻和/或其他工艺从载体衬底120去除组合层110。
然后，可以在组合层110的一侧或两侧上涂层、曝光和显影光刻胶层。例如，可以在组合层110的第一侧112上形成光刻胶部分210，且光刻胶层220可以基本覆盖组合层110的第二侧114。可以将导电柱150分散在第一子集和第二子集之间。在图3中，第一子集包括导电柱152，且第二子集包括导电柱154。第一子集将包括图3中描绘的两个以上的导电柱152，且第二子集将包括图3中描绘的一个以上的导电柱154。
组合层110的第一侧112的光刻胶部分210形成在第一子集的每个导电柱152上方，然而，第二子集的导电柱154和组合层110的第一侧112上的剩余表面部件可以保留暴露于随后的光刻工艺。光刻胶部分210和层220可以包括化学增强的光刻胶或非化学增强的光刻胶，且可以是正性或负性的。光刻胶部分210或层220的处理可以包括沉积工艺，沉积工艺包括，例如，尤其是层压干膜型光刻胶、旋涂、浸涂、刷涂和/或喷墨分配(ink-jetdispensing)。可以实施后沉积烘烤布置以去除溶剂和/或其他不想要的成分，诸如在约40℃到约200℃的范围内，烘烤时间可在约10秒到约10分的范围内。
图4是根据本发明的一个或多个方面的图3中示出的装置100在随后的阶段中的截面图，其中，在蚀刻工艺期间，将位于第一子集的导电柱152上方的光刻胶部分210用作掩模。使用蚀刻工艺去除没有由光刻胶层210和层220保护的最外面的金属化层140的部分。这样，在组合层110的第一侧112上，去除最外面的金属化层140直到最外面的介电层130。然而，第二子集的导电柱154上方的最外面的金属化层140的蚀刻将持续足够的时间，以便对最外面的介电层130的外表面中的导电柱154的暴露面156进行开槽。这样，导电柱154的第二子集的暴露面156形成了凹进的迹线的部分，而导电柱152的第一子集的每个的掩模部分形成了凸块焊盘230。位于开槽的迹线上方和包围介电层130的表面的下方的凹槽的深度可以小于7微米(诸如约4微米)，尽管其他深度也可以在本发明的范围内。
图5是根据本发明的一个或多个方面的图4中示出的装置100在随后的阶段中的截面图，其中，已经通过传统的方式将光刻胶部分210和光刻胶层220去除，且形成了阻焊部分410。阻焊部分410可以包括耐热涂层材料，且可以有助于保护下面的层。
其他形成凸块焊盘230和凹进的迹线156的方法也在本发明的范围内。在图6至图8中描绘了一种这样的实例。图6是根据本发明的一个或多个方面的图2中示出的装置100在随后的制造阶段中的截面图。如上所述，已经从载体衬底120将组合层110去除。然后，可以在组合层110的一侧或两侧上涂层、曝光和显影光刻胶层。例如，可以在组合层110的第一侧112上形成光刻胶部分510，且光刻胶层520可以基本覆盖组合层110的第二侧114。组合层110的第一侧112上的光刻胶部分510可以基本覆盖全部的第一侧112，包括第二子集的每个导电柱154的上方，除了第一子集的导电柱152的上方，将第一子集的导电柱152剩余暴露于随后的工艺。
图7是根据本发明的一个或多个方面的图6中示出的装置100在随后的制造阶段中的截面图，其中，在金属化工艺期间将光刻胶部分510用作掩模。使用金属化工艺将金属增加到第一子集的暴露的导电柱152。通过金属化工艺增加的材料可以包括铜、钛、铝、镍、金、合金和/或它们的组合的一种或多种，和/或其他材料。可以通过电镀、化学镀、CVD、外延生长和/或其他工艺实施金属化，且可以将材料增加到导电柱152使厚度在约5微米到约50微米的范围内，尽管其他厚度也在本发明的范围内。
图8是根据本发明的一个或多个方面的图7中示出的装置100在随后的制造阶段中的截面图，其中，已将光刻胶部分510和光刻胶层520去除。图8也反映了对第一子集的导电柱152、第二子集的导电柱154和最外面的金属化层140具有选择性的蚀刻工艺的结果。例如，将最外面的金属化层140去除，直到最外面的介电层130，包括将最外面的介电层130的外表面中的导电柱154的第二子集的暴露面156开槽到足够的程度。如上所述，导电柱154的第二子集的暴露面156形成了凹进的迹线的部分，而导电柱152的第一子集的每个突出部分形成了凸块焊盘230。在这个工艺期间，也回蚀刻导电柱(突出柱)的顶部。因此，应该调整增加金属化(图7中所示)的工艺步骤，以确保突出柱剩余足够的高度(甚至在这个随后的蚀刻步骤之后)。额外的工艺可以确保，诸如形成焊料光刻胶部分和/或另外到达图5中示出的实施例。
图9是图5中示出的装置100的截面图，其中，已经将测试探针810引入接触第一子集的导电柱152的凸块焊盘230的一个。测试探针810的尖端直径为D，直径D基本大于柱间距P。例如，柱间距P可以为约40微米(如果不再变小的话)，且测试探针810的尖端直径D可以为约30微米(如果不再明显增大的话)。然而，因为第二子集的导电柱154是凹进的，所以导电柱154与第一子集的导电柱152由于测试探针810未对准而不会短路。
图10是根据本发明的一个或多个方面的装置900的至少一部分的截面图。装置900包括图5中示出的装置100、管芯910、以及多个连接在集成电路芯片和相应的凸块焊盘中的一个凸块焊盘之间的导电凸块920。管芯910可以是或包括一个或多个集成电路芯片、封装件等。导电凸块920可以包括焊料、金、导电胶和/或其他导电材料。管芯910可以包括配置为在由导电凸块920连接之前与凸块焊盘230对准的焊盘915。
上面概述了多个实施例的特征，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或修改其他用于执行与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域普通技术人员还应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。
在本发明的结尾提供摘要以符合37C.F.R.§1.72(b)从而允许读者快速确定本发明技术的性质。提交本发明将应该理解其不用于解释或限制权利要求的范围或含义。
虽然根据示出的实施例介绍本发明，但是，本说明并不构成限制意义。参考本说明，示出实施例的不同修改和组合以及本发明的其他实施例对本领域的技术人员来说是显而易见的。因此，所附权利要求包括任何这样的修改或实施例。

Claims (20)

1.一种半导体装置，包括：
衬底；
多个导电迹线，设置在所述衬底的侧上；
多个导电元件，所述导电元件的每个都从所述导电迹线的相应的一个迹线延伸到所述衬底中；以及
多个凸块焊盘，所述凸块焊盘的每个突出于所述导电迹线的第一子集的一个，其中，将所述导电迹线的第二子集在所述衬底的所述侧内开槽，其中，所述导电迹线的第二子集位于两个邻近的所述导电迹线的第一子集之间。
2.根据权利要求1所述的半导体装置，其中，所述侧是第一侧，且所述多个导电元件是导电柱，所述导电柱延伸到设置在所述衬底的第二侧上的相应导电部件。
3.根据权利要求1所述的半导体装置，其中，所述多个导电迹线彼此横向偏移最小的迹线间距，所述多个凸块焊盘彼此横向偏移最小的凸块焊盘间距，所述最小的凸块焊盘间距大于所述最小的迹线间距。
4.根据权利要求1所述的半导体装置，其中，所述多个导电迹线彼此横向偏移最小的迹线间距，所述多个凸块焊盘彼此横向偏移最小的凸块焊盘间距，所述最小的凸块焊盘间距是所述最小的迹线间距的至少两倍。
5.根据权利要求1所述的半导体装置，其中，所述多个导电迹线彼此横向偏移最小的迹线间距，所述最小的迹线间距小于50微米，且所述多个凸块焊盘彼此横向偏移最小的凸块焊盘间距，所述最小的凸块焊盘间距是所述最小的迹线间距的两倍。
6.根据权利要求1所述的半导体装置，进一步包括：
集成电路芯片；以及
多个导电凸块，连接在所述集成电路芯片和所述凸块焊盘的相应焊盘之间。
7.根据权利要求6所述的半导体装置，其中，所述多个导电凸块彼此横向偏移最小的凸块间距，所述最小的凸块间距小于110微米。
8.一种形成半导体装置的方法，包括：
从载体分离衬底，所述载体上形成有额外的衬底，其中，分离的所述衬底包括位于所述衬底的顶面上的导电层和多个导电柱，所述多个导电柱的每个都从所述衬底的底面延伸穿过所述衬底到达所述导电层；以及
通过选择性去除所述导电层，除了从所述导电柱的第一子集的每个上方去除所述导电层，在所述导电柱的所述第一子集的每个上方形成凸块焊盘，并且从不是所述第一子集的部分的所述导电柱的每个上方去除所述导电层的足够的部分，从而暴露凹进到所述衬底的所述顶面中的导电面；
其中，所述导电柱的不是所述第一子集的部分位于两个邻近的所述导电柱的所述第一子集之间。
9.根据权利要求8所述的方法，其中，在所述导电柱的所述第一子集的每个上方形成所述凸块焊盘包括：
在所述导电柱的所述第一子集的每个上方而不是剩余的所述导电柱上方的所述导电层上形成光刻胶掩模；以及
蚀刻以去除所述导电层，除了所述光刻胶掩模下方的所述导电层。
10.根据权利要求9所述的方法，其中，在所述导电柱的所述第一子集的每个上方而不是剩余的所述导电柱上方的所述导电层上形成所述光刻胶掩模包括在所述导电柱的所述第一子集的每个上方而不是所述导电层的剩余部分上方的所述导电层上形成所述光刻胶掩模。
11.根据权利要求9所述的方法，其中，在所述导电柱的所述第一子集的每个上方而不是剩余的所述导电柱上方的所述导电层上形成所述光刻胶掩模包括仅在所述导电柱的所述第一子集的每个上方的所述导电层上形成所述光刻胶掩模。
12.根据权利要求9所述的方法，其中，以去除所述导电层的蚀刻从不是所述第一子集的部分的所述导电柱的每个上方去除所述导电层的足够的部分，从而暴露凹进到所述衬底的所述顶面中的导电面。
13.根据权利要求12所述的方法，其中，通过所述蚀刻减薄的所述导电层的部分包括所述导电面。
14.根据权利要求12所述的方法，其中，所述导电面是不属于所述第一子集的部分的所述导电柱的相应导电柱的导电面。
15.根据权利要求8所述的方法，其中，在所述导电柱的所述第一子集的每个上方形成所述凸块焊盘包括：
在不是所述第一子集的每个所述导电柱上方的所述导电层上形成光刻胶掩模；
将额外的导电材料增加到没有被所述光刻胶掩模覆盖的所述导电层的部分；
去除所述光刻胶掩模；以及
蚀刻以从不是所述第一子集的部分的所述导电柱的每个上方去除所述导电层的足够的部分，以暴露在所述衬底的所述顶面内开槽的导电面。
16.根据权利要求15所述的方法，其中，通过所述蚀刻减薄的所述导电层的部分包括所述导电面。
17.根据权利要求15所述的方法，其中，所述导电面是不属于所述第一子集的部分的所述导电柱的相应导电柱的导电面。
18.根据权利要求8所述的方法，还包括通过将与所述导电柱的所述第一子集的每个上方的所述凸块焊盘接触的焊料凸块回流焊连接所述衬底与半导体管芯封装件。
19.根据权利要求8所述的方法，还包括使用测试探针接触所述凸块焊盘的一个焊盘。
20.一种形成半导体装置的方法，包括：
提供管芯，所述管芯包括至少一个集成电路芯片；
提供衬底，所述衬底包括延伸穿过所述衬底的导电柱的第一子集和第二子集，其中，所述导电柱的所述第一子集的每个都包括突出于所述衬底的表面的突出焊盘，且所述导电柱的所述第二子集的每个都部分形成了凹进所述衬底的表面的迹线，所述导电柱的所述第二子集位于两个邻近的所述导电柱的所述第一子集之间；以及
通过多个导电凸块将所述管芯连接到所述衬底，所述多个导电凸块的每个都延伸到所述凸块焊盘的一个焊盘和所述管芯之间。
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