TWI496267B - 具有凹陷之半導體晶粒，相關之導線架，相關之系統及方法 - Google Patents

具有凹陷之半導體晶粒，相關之導線架，相關之系統及方法 Download PDF

Info

Publication number
TWI496267B
TWI496267B TW097128166A TW97128166A TWI496267B TW I496267 B TWI496267 B TW I496267B TW 097128166 A TW097128166 A TW 097128166A TW 97128166 A TW97128166 A TW 97128166A TW I496267 B TWI496267 B TW I496267B
Authority
TW
Taiwan
Prior art keywords
foot
support
semiconductor die
recess
die
Prior art date
Application number
TW097128166A
Other languages
English (en)
Other versions
TW200913214A (en
Inventor
Swee Kwang Chua
Yong Poo Chia
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of TW200913214A publication Critical patent/TW200913214A/zh
Application granted granted Critical
Publication of TWI496267B publication Critical patent/TWI496267B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Description

具有凹陷之半導體晶粒，相關之導線架，相關之系統及方法
本發明大體係針對具有凹陷之半導體晶粒、相關之導線架及相關之系統及方法。
半導體處理及封裝技術正不斷地演進以滿足對於具有改良之效能及減小之尺寸及成本的裝置之行業需求。電子產品需要在相對小的空間中具有高的裝置密度之封裝的半導體組合。舉例而言，在行動電話、個人數位助理、膝上型電腦及許多其他產品中，可用於記憶體裝置、處理器、顯示器及其他半導體裝置之空間正不斷減小。因此，存在增加半導體裝置及組件在半導體組合之有限的佔據面積內之密度之需要。增加半導體裝置在給定佔據面積內之密度的一技術為堆疊半導體晶粒。然而，此技術之一難題為在堆疊之晶粒內及之間提供足夠的電互連。
解決與堆疊之半導體晶粒相關之難題的一方法為使用具有支撐最低晶粒之支撐腳座及提供晶粒之堆疊與在完成的封裝之外部的裝置之間的電連接之導線指狀物的導線架。雖然此配置已證明為適合於許多用途，但不僅減小封裝之佔據面積且亦減小封裝之總體積的不斷壓力已產生了對更小且更有效率封裝的晶粒之需要。
以下關於封裝之半導體裝置及組合及用於形成封裝之半導體裝置及組合之方法來描述本發明之若干實施例。以下 關於半導體晶粒來描述某些實施例之許多細節。術語"半導體晶粒"貫穿全文用以包括各種各樣的製品，例如，包括個別積體電路晶粒及/或具有其他半導體特徵之晶粒。某些實施例之許多具體細節在圖1至圖6及以下本文中闡明以提供對此等實施例之徹底理解。若干其他實施例可具有與此章節中所描述之組態、組件及/或製程不同的組態、組件及/或製程。因此，熟習此項技術者應瞭解，在無圖1至圖6中所示的實施例之若干細節之情況下，可實踐額外實施例。
圖1為根據一特定實施例組態之包括一封裝101(展示其一部分)之系統100之部分示意性橫截面圖。封裝101可包括一導線架130，其具有一承載一或多個半導體晶粒110之支撐腳座131。為了說明之目的，展示承載四個堆疊之半導體晶粒110(其分別展示為第一、第二、第三及第四半導體晶粒110a、110b、110c及110d)的導線架130。在其他實施例中，導線架130可承載更多或更少之晶粒110，例如，一單一晶粒110或兩個堆疊之晶粒110。在任何此等實施例中，晶粒110可包括收納支撐腳座131之一或多個凹陷114，如下文進一步詳細地描述。
在圖1所示之實施例中，晶粒110中之每一者具有一第一(例如，面向下)晶粒表面111及一第二(例如，面向上)晶粒表面112。所說明之第一晶粒表面111包括兩個凹陷114，其各自沿著第一晶粒表面111之兩個相對邊緣中之一者，且兩個邊緣中之一者可見於圖1中。凹陷114可局部地減小 晶粒110之厚度T。切割晶粒110中之凹陷114的合適技術包括於美國專利第7,218,001號中，該案已讓與給本申請案之受讓人，且被以引用之方式併入本文中。在圖1中所示之配置中，支撐腳座131之至少部分收納於第一晶粒110a之凹陷114中。在一特定實施例中，凹陷114足夠深，使得第一腳座表面133(例如，面向外之表面)與第一晶粒表面111齊平或自第一晶粒表面111凹陷。因此，單單在第一晶粒110a下方添加支撐腳座131並會不增加第一晶粒110a之總厚度T。支撐腳座131可進一步包括一第二腳座表面134，其面向凹陷114且背向第一腳座表面133。腳座黏著劑135可黏著性地將支撐腳座131結合至凹陷114之表面115。
在一特定實施例中，第一晶粒110a之總厚度可為約120微米，且凹陷114可具有約60微米之深度。支撐腳座131與腳座黏著劑135之組合厚度可為約60微米或更小，使得第一腳座表面133與鄰近第一晶粒表面111齊平或自鄰近第一晶粒表面111凹陷。在其他實施例中，前述特徵可具有不同尺寸，而支撐腳座131仍不增加組合之晶粒110a與支撐腳座131的總厚度T。在另外實施例中，支撐腳座131可僅部分收納於凹陷114中，使得其部分自凹陷114突出。在此等例子中，支撐腳座131確實增加組合之晶粒110a與支撐腳座131的總厚度，但增加的量不如在不存在凹陷114的情況下多。
當封裝101包括多個晶粒110時，額外的晶粒可被堆疊於第一晶粒110a上，且藉由對應的晶粒黏著劑層116而附 著。晶粒黏著劑層116可相對薄以減小總封裝厚度，及/或不同之熱膨脹係數產生之熱導率不匹配的可能性。晶粒110中之每一者可包括一最接近第二晶粒表面112定位且可自第二晶粒表面112接取的結合位點113。堆疊之晶粒110的結合位點113及凹陷114可經配置，使得上部晶粒(例如，第二晶粒110b)之凹陷114直接位於堆疊中之下一個下部晶粒(例如，第一晶粒110a)之對應的結合位點113上。因此，上部晶粒之凹陷114可收容、容納及/或收納導線架130與下部晶粒之結合位點113之間的電連接。
為了支援至半導體晶粒110之電連接，導線架130包括朝向晶粒110向內延伸之導線指狀物132。可用線結合103將個別導線指狀物132連接至晶粒110之對應的結合位點113。當封裝101包括多個晶粒110時，可將個別導線指狀物132連接至晶粒110中之每一者之對應的結合位點113。凹陷114可降低或消除線結合103接觸凹陷114形成於其中的半導體晶粒110之可能性。
可在橫向延伸穿過圖1之平面的方向上並排地排列多個導線指狀物132，且多個導線指狀物132可因此形成一導線指狀物平面L，其邊緣可見於圖1中。一或多個支撐腳座131可在大體橫過圖1之平面的方向上延伸，且可因此形成一腳座平面P。在一特定實施例中，在大體與晶粒110之厚度維度T對準之方向上使導線指狀物平面L自腳座平面P偏移。此配置可減小需要將導線指狀物132連接至最遠的晶粒(例如，第四晶粒110d)的線結合103之長度。在其他實施 例中，導線指狀物平面L及腳座平面P可具有不同於圖1中所示之配置的配置。舉例而言，當封裝101僅包括第一晶粒110a時，導線指狀物平面L可與腳座平面P共平面。在此等配置中之任何者中，一旦形成了導線架130與晶粒110之間的電連接，則可藉由密封劑102至少部分地密封晶粒110、線結合103、支撐腳座131及導線指狀物132。導線指狀物132之自密封劑102向外突出的部分可接著經修剪、成形及/或另外形成以提供至外部組件的連接。
圖2為包括圖1中所示之導線架130及第一晶粒110a的封裝101之一實施例的組件之部分分解示意性平面圖說明。可使用衝壓製程或另一合適製程，由單塊傳導材料(例如，金)薄片形成導線架130。導線架130包括一框架部件136，其臨時地承載向內延伸之導線指狀物132及支撐腳座131。支撐腳座131自導線指狀物132向內地定位且由抽取式紮帶137相對於框架部件136加以支撐。在此特定實施例中，支撐腳座131包括一被分割於第一部分139a及第二部分139b上之腳座表面138。因此，在此實施例中，腳座表面138係不連續的。當第一半導體晶粒110a經倒轉及面向下地定位在框架部件136之頂部上(如由箭頭A指示)時，凹陷114中之每一者與第一部分139a及第二部分139b中之一對應者對準且收納該對應者。接著(例如)使用標準線結合或其他合適傳導耦接器在對應的導線指狀物結合位點141處將第二晶粒表面112上之結合位點113(圖1)電連接至導線指狀物132。若要將另外的晶粒堆疊於第一晶粒110a上， 則每一者經堆疊且在下一個晶粒經堆疊且電連接至導線架130前連接至導線指狀物132。在所有晶粒已經堆疊且電連接至導線架130後，組合經置放於一模子中且經密封，其後，框架部件136、紮帶137及(視情況)導線指狀物132之部分被移除。
在圖2中所示之配置之特定實施例中，導線架130包括一在第一部分139a與第二部分139b之間的開口140。第一部分139a及第二部分139b可為伸長的，以便配合於第一半導體晶粒110a之對應的伸長凹陷114中。由於第一晶粒110a為矩形且凹陷114與第一半導體晶粒110a之相對的邊緣對準，所以支撐腳座131之第一部分139a及第二部分139b亦可大體相互平行地對準。在其他實施例中，導線架130可具有亦支撐一或多個半導體晶粒110之其他配置。以下參看圖3及圖4描述代表性配置。
開始於圖3，根據另一實施例之導線架330包括大體類似於以上參看圖2描述之對應組件之一框架部件136及導線指狀物132。導線架330進一步包括一支撐腳座331，其具有定位於中心開口340周圍之四個間隔開的部分339(分別展示為第一、第二、第三及第四部分339a、339b、339c及339d)。可用一對應的紮帶337將部分339a中之每一者連接至框架部件136。第一半導體晶粒110a可包括大體類似於圖2中所示之凹陷的伸長凹陷114(以虛線展示)，以便容納及收納支撐腳座331之部分339a－339d。在另一實施例中，第一半導體晶粒110a可替代地包括四個分隔的凹陷314a－ 314d，每一者係定位於第一晶粒110a之一角落處，以收納支撐腳座部分339a－339d中之一對應者。支撐腳座部分339a－339d可經對稱地排列，例如，使得連接第一部分339a與第三部分339c之對角線將連接第二部分339b與第四部分339d之對角線一分為二。在其他實施例中，腳座部分339可具有其他對稱或不對稱排列。
圖4說明根據另一實施例之承載一對應之半導體晶粒410的導線架430。導線架430可包括一框架部件436，其承載向內延伸之導線指狀物432及一單塊的支撐腳座431。支撐腳座431可具有一中心開口440，且可用紮帶437相對於框架部件436臨時地加以支撐。因此，支撐腳座431可具有一類似於畫框之形狀，且在一特定實施例中，可具有經整體連接以形成一單塊結構之四個部分439a－439d。對應的半導體晶粒410包括一定位於其周邊周圍之對應的凹陷414，以形成支撐腳座431之配置的鏡像。因此，當半導體晶粒410經倒轉且置放於導線架430上時，大體上框形之支撐腳座431係收納於半導體晶粒410之大體框形之凹陷414中，且半導體晶粒410之中心部分係收納於導線架430之中心開口440中。
圖5為根據若干實施例之用於形成封裝之半導體裝置之過程500的流程圖。為了說明之目的，在圖5中將若干實施例之特徵展示於一起。一般熟習此項技術者應理解，可藉由比圖5中識別之所有步驟少的步驟實踐另外特定實施例，且在其他實施例中，除了圖5中識別之步驟之外，可 執行額外步驟。
過程部分501包括相互最靠近地定位一半導體晶粒及一導線架。在過程部分502中，一支撐腳座經收納於半導體晶粒之凹陷中。舉例而言，具有以上參看圖1至圖4描述之組態中之任一者的支撐腳座或支撐腳座部分可經收納於半導體晶粒之一或多個對應的凹陷中。
過程部分503包括相對於半導體晶粒定位一支撐腳座(具有一腳座表面，其中一開口延伸穿過其)。除了過程部分502之外或代替過程部分502，可執行過程部分503。舉例而言，在以上參看圖1至圖4描述之配置的環境中，支撐腳座中之開口可允許支撐腳座經定位使得腳座表面經收納或部分收納於晶粒之一或多個凹陷中。然而，在其他實施例中，具有一延伸穿過其之開口的腳座可支撐一半導體晶粒，而不必使支撐表面收納於晶粒之凹陷中。
在前述實施例中之任何者中，可將支撐腳座附著至晶粒(過程部分504)，且可將晶粒電連接至導線指狀物(過程部分505)。在過程部分506中，可密封晶粒、導線指狀物及/或支撐腳座以保護此等組件。在過程部分507中，通常在已完成密封過程後可移除可相對於晶粒臨時支撐導線指狀物及支撐腳座之框架部件。
根據以上參看圖1至圖5描述的前述實施例中之至少一些實施例而組態及/或製造之半導體封裝之一特徵為，其包括收納於一對應的半導體晶粒之一或多個凹陷中之支撐腳座。此配置可減小半導體封裝之總厚度，因為支撐腳座之 厚度並不累積至半導體晶粒之厚度。實情為，支撐腳座可完全或部分地凹陷至晶粒之鄰近表面中。凹陷在晶粒中之存在可允許晶粒之總厚度保持相對高(例如，100微米以上)，而不增加組合的晶粒/支撐腳座之總厚度。具有前述範圍中之厚度的晶粒可具有良好的再新裕度及/或讀取/寫入速度，而不危害封裝之晶粒的緊密(例如，薄)構形。在另外特定實施例中，支撐腳座可形成亦包括用於電連接至半導體晶粒之導線指狀物之總體導線架之部分。因此，導線架可提供上述低構形支撐及與外部裝置之電連接兩者。
前述實施例中之至少一些的另一特徵為，支撐腳座可包括由一開口分隔之多個腳座表面。結果，當與習知腳座相比時，可減少需要形成支撐腳座的材料量，該習知腳座具有大體形成其所支撐的晶粒之佔據面積的鏡像之實心幾何形狀。減少用於支撐腳座之材料量可降低腳座之成本，及因此完成的封裝之成本。儘管支撐腳座131之尺寸減小了，但支撐腳座131、紮帶137與導線架130之組合在線結合及密封步驟期間可對其承載的半導體晶粒或晶粒提供充分支撐。
以上參看圖1至圖5描述的半導體封裝中之任一者可被併入於大量較大及/或較複雜的系統中之任一者內，該等系統之一代表性實例為示意性地展示於圖6中之系統600。系統600可包括一處理器602、一記憶體604(例如，SRAM、DRAM、快閃記憶體及/或其他記憶體裝置)、輸入/輸出裝置606及/或其他子系統或組件608。具有以上參看圖1至圖 5描述的特徵中之任一者或組合的半導體封裝可包括於圖6中展示之組件中的任一者中。所得系統600可執行廣泛的各種各樣之計算、處理、儲存、感測、成像及/或其他功能中之任一者。因此，代表性系統600包括(但不限於)電腦及/或其他資料處理器，例如，桌上型電腦、膝上型電腦、網際網路器具、手持式裝置(例如，掌上型電腦、可佩帶式電腦、蜂巢式或行動電話、個人數位助理、音樂播放器等)、多處理器系統、基於處理器或可程式之消費者電子器件、網路電腦及小型電腦。其他代表性系統600可收容於一單一單元中或分布於多個互連之單元上(例如，經由一通信網路)。系統600之組件可因此包括本端及/或遠端記憶體儲存裝置及廣泛的各種各樣之電腦可讀媒體中之任何者。
自前述內容，應瞭解，為了說明之目的，本文中已描述了具體實施例，但前述系統及方法亦可具有其他實施例。舉例而言，雖然以上在大體均勻且連續的導線架之環境中描述導線指狀物及支撐腳座，且因此其具有類似或相同的材料特性，但在其他實施例中，導線指狀物及腳座支撐可具有不同組成及/或非單一的配置。支撐腳座可具有不同於以上具體描述之形狀及/或配置之形狀及/或配置，例如，相對的"C"形支撐部分、四個以上支撐部分及/或其他。可藉由與圖中所示之配置不同的配置(例如，在支撐腳座及鄰近(齊平或半齊平)晶粒表面上延伸之薄膜)來將支撐腳座緊固至晶粒。
在其他實施例中，可組合或消除在特定實施例之環境中描述之某些特徵。舉例而言，上述實施例中之若干者係在腳座支撐收納於對應的半導體晶粒之凹陷中之環境中描述的，但在其他實施例中，腳座支撐可包括多個間隔部分或腳座支撐部分之間的開口，而不必收納於對應的半導體晶粒之凹陷中。在另一實例中，可將圖4中展示之半導體晶粒與圖1至圖3中展示之支撐腳座一起使用。另外，雖然某些優勢可能與某些實施例相關，但其他實施例亦可展示出此等優勢，且並非所有實施例皆必定地需要展示出此等優勢。因此，本發明可包括以上未展示或描述之其他實施例。
100‧‧‧系統
101‧‧‧封裝
102‧‧‧密封劑
103‧‧‧線結合
110‧‧‧半導體晶粒
110a‧‧‧第一半導體晶粒
110b‧‧‧第二半導體晶粒
110c‧‧‧第三半導體晶粒
110d‧‧‧第四半導體晶粒
111‧‧‧第一晶粒表面
112‧‧‧第二晶粒表面
113‧‧‧結合位點
114‧‧‧凹陷
115‧‧‧凹陷之表面
116‧‧‧晶粒黏著劑層
130‧‧‧導線架
131‧‧‧支撐腳座
132‧‧‧導線指狀物
133‧‧‧第一腳座表面
134‧‧‧第二腳座表面
135‧‧‧腳座黏著劑
136‧‧‧框架部件
137‧‧‧紮帶
138‧‧‧腳座表面
139a‧‧‧第一部分
139b‧‧‧第二部分
140‧‧‧開口
141‧‧‧導線指狀物結合位點
314a‧‧‧凹陷
314b‧‧‧凹陷
314c‧‧‧凹陷
314d‧‧‧凹陷
330‧‧‧導線架
331‧‧‧支撐腳座
337‧‧‧紮帶
339a‧‧‧支撐腳座部分(第一部分)
339b‧‧‧支撐腳座部分(第二部分)
339c‧‧‧支撐腳座部分(第三部分)
339d‧‧‧支撐腳座部分(第四部分)
340‧‧‧中心開口
410‧‧‧半導體晶粒
414‧‧‧凹陷
430‧‧‧導線架
431‧‧‧支撐腳座
432‧‧‧導線指狀物
436‧‧‧框架部件
437‧‧‧紮帶
439a‧‧‧整體結構之部分
439b‧‧‧整體結構之部分
439c‧‧‧整體結構之部分
439d‧‧‧整體結構之部分
440‧‧‧中心開口
600‧‧‧系統
602‧‧‧處理器
604‧‧‧記憶體
606‧‧‧輸入/輸出裝置
608‧‧‧其他子系統或組件
A‧‧‧箭頭
L‧‧‧導線指狀物平面
P‧‧‧腳座平面
T‧‧‧厚度
圖1為根據本發明之一實施例而組態的封裝之一部分之部分示意性橫截面側面正視圖。
圖2為根據本發明之一實施例而組態的包括一半導體晶粒及具有導線指狀物及支撐腳座之導線架的封裝組件之部分示意性分解平面圖說明。
圖3為根據本發明之一實施例而組態的半導體晶粒及具有一支撐腳座之導線架之部分示意性分解平面圖說明。
圖4為根據本發明之一實施例而組態的半導體晶粒及具有一支撐腳座之導線架之部分示意性分解平面圖說明。
圖5為說明根據本發明之若干實施例的用於封裝半導體晶粒之方法之流程圖。
圖6為說明根據本發明之另外實施例的其中可併入有封 裝之一系統之部分示意性方塊圖。
100‧‧‧系統
101‧‧‧封裝
102‧‧‧密封劑
103‧‧‧線結合
110‧‧‧半導體晶粒
110a‧‧‧第一半導體晶粒
110b‧‧‧第二半導體晶粒
110c‧‧‧第三半導體晶粒
110d‧‧‧第四半導體晶粒
111‧‧‧第一晶粒表面
112‧‧‧第二晶粒表面
113‧‧‧結合位點
114‧‧‧凹陷
115‧‧‧凹陷之表面
116‧‧‧晶粒黏著劑層
130‧‧‧導線架
131‧‧‧支撐腳座
132‧‧‧導線指狀物
133‧‧‧第一腳座表面
134‧‧‧第二腳座表面
135‧‧‧腳座黏著劑
L‧‧‧導線指狀物平面
P‧‧‧腳座平面
T‧‧‧厚度

Claims (17)

  1. 一半導體系統，其包含：一半導體晶粒，其具有一第一表面及朝向相反於該第一表面之一第二表面，該第一表面具有一晶粒凹陷，該晶粒凹陷包含一定位沿著該半導體晶粒之一第一邊緣的第一伸長之凹陷及一定位沿著該半導體晶粒之一第二凹陷的第二伸長之凹陷；及一承載該半導體晶粒之支撐腳座，該支撐腳座至少部份地收納於該晶粒凹陷，其中該支撐腳座包括收納於該第一伸長之凹陷中之第一及第二間隔開的部分，及收納於該第二伸長之凹陷中之第三及第四間隔開的部分。
  2. 一種半導體系統，其包含：一導線架，其包括：一框架部件；複數個導線指狀物，其連接至該框架部件且自該框架部件向內延伸；及一支撐腳座，其自該等導線指狀物向內定位，該支撐腳座具有：一第一腳座部分，其藉由一第一收縮紮帶連接至該框架部件且自該框架部件向內定位，該第一腳座部分具有一經定位以承載一半導體晶粒之第一支撐表面；一第二腳座部分，其藉由一第二收縮紮帶連接至該框架部件且自該框架部件向內定位，該第二腳座 部分與該第一腳座部分間隔開，且具有一與該第一腳座支撐表面間隔開且與該第一腳座支撐表面不連續且經定位以承載該半導體晶粒之第二腳座支撐表面；一第三腳座部分，其藉由一第三收縮紮帶連接至該框架部件且自該框架部件向內定位，該第三腳座部分與該第一及該第二腳座部分間隔開，並具有一與該第一及該第二腳座支撐表面間隔開且經定位以承載該半導體晶粒之第三腳座支撐表面；及一第四腳座部分，其藉由一第四收縮紮帶連接至該框架部件且自該框架部件向內定位，該第四腳座部分與該第一、該第二及該第三腳座部分間隔開，並具有一與該第一、該第二及該第三腳座支撐表面間隔開且經定位以承載該半導體晶粒之第四腳座支撐表面。
  3. 如請求項2之系統，其中該第一、該第二、該第三及該第四腳座支撐表面大體共平面。
  4. 如請求項2之系統，其中該第一腳座支撐表面與該第三腳座支撐表面之間之一對角線將該第二腳座支撐表面與該第四腳座支撐表面之間之一對角線一分為二。
  5. 一種半導體導線架，其包含：一框架部件；複數個導線指狀物，其連接至該框架部件且自該框架部件向內延伸；及 一支撐腳座，其自該等導線指狀物向內定位，該支撐腳座具有一經定位以承載一半導體晶粒之腳座表面，該支撐腳座具有一自該腳座表面延伸穿過該支撐腳座之開口，且該腳座表面包括在該開口周圍且自該開口向外定位之第一、第二、第三及第四間隔開的腳座表面部分，該框架藉由個別之第一、第二、第三及第四收縮紮帶連接至該第一、第二、第三及第四腳座表面部份。
  6. 如請求項5之導線架，其中該第一及第二間隔開的腳座表面部份係定位於該開口之相對側上。
  7. 一種半導體系統，其包含：一框架部件；複數個導線指狀物，其連接至該框架部件且自該框架部件向內延伸；一支撐腳座，其自該等導線指狀物向內定位，該支撐腳座具有一經定位以承載一半導體晶粒之腳座表面，該支撐腳座具有一從該腳座表面延伸穿過該支撐腳座之一開口，其中該腳座表面包括一包圍該開口之單一連續表面；及一將該支撐腳座連接至該框架之可移除收縮紮帶。
  8. 一種半導體系統，其包含：一半導體晶粒，其具有多個結合位點；一支撐腳座，其具有一承載該半導體晶粒之腳座表面，該支撐腳座具有一自該腳座表面延伸穿過該支撐腳座之開口，該腳座表面包括在該開口周圍且自該開口向 外定位之第一、第二、第三及第四間隔開的部分，其中該等部分中之每一者具有正方形形狀且對準及承載該半導體晶粒之四個角落中之一者；複數個導線指狀物，其自該支撐腳座向外定位；及傳導性連接器，其耦接於該等導線指狀物與該等結合位點之間。
  9. 如請求項8之系統，其中該第一部份係在承載該半導體晶粒之該開口之一側上之朝向該半導體晶粒之一第一邊緣，且該第二部份係在該開口之一相對側上且承載該半導體晶粒朝向與該半導體晶粒之該第一邊緣相對之該半導體晶粒之一第二邊緣。
  10. 如請求項9之系統，其中該腳座表面之該第一部分與該第二部分沿著大體平行的軸線伸長。
  11. 如請求項8之系統，其中該腳座表面具有一在該開口周圍之大體框型形狀。
  12. 如請求項8之系統，進一步包含一至少部分地安置於該半導體晶粒、該支撐腳座、該等導線指狀物及該等傳導性連接器周圍之密封劑。
  13. 一種用於製造一半導體系統之方法，其包含：在一半導體晶粒之一凹陷中收納一支撐腳座之至少部分，該半導體晶粒具有一具有該凹陷之第一表面及一與該第一表面朝向相反之第二表面，該凹陷包括在該半導體晶粒之四個間隔開之角落處之至少一凹陷，使得該支撐腳座之四個間隔開之腳座表面收納於該半導體晶粒之 該四個間隔開之角落處之該至少一凹陷的個別部分中；及將該支撐腳座附著至該半導體晶粒，同時該支撐腳座在該凹陷中，一可移除收縮紮帶連接至該支撐腳座。
  14. 如請求項13之方法，其中該支撐腳座為具有一框架部分及自該框架部分延伸之複數個導線指狀物之一導線架的一部分，且其中該方法進一步包含：當該支撐腳座經收納於該凹陷中時，以最接近該半導體晶粒來定位該等導線指狀物；使用線結合將該等導線指狀物與該半導體晶粒之結合位點電連接；在該半導體晶粒及該導線架周圍安置一密封劑；及移除該導線架之該框架部分。
  15. 如請求項13之方法，其中在該半導體晶粒之該凹陷中收納該支撐腳座之至少部分包括收納該支撐腳座，同時該支撐腳座之一面向外的表面與該半導體晶粒之鄰近該凹陷之該第一表面齊平或自該第一表面凹陷。
  16. 如請求項13之方法，其中該凹陷為一第一凹陷，且其中收納該支撐腳座之至少部分包括在該第一凹陷中收納該支撐腳座之一第一部分，且其中該方法進一步包含在與該第一凹陷間隔開之一第二凹陷中收納該支撐腳座之一第二部分。
  17. 如請求項13之方法，其中該凹陷在該半導體晶粒之一周邊周圍延伸，且其中該支撐腳座具有一在一中心開口周 圍安置之具有一大體框型形狀之支撐表面，且其中該方法進一步包含在該支撐腳座之該中心開口中定位該半導體晶粒之一中心部分。
TW097128166A 2007-07-24 2008-07-24 具有凹陷之半導體晶粒，相關之導線架，相關之系統及方法 TWI496267B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG200705420-8A SG149724A1 (en) 2007-07-24 2007-07-24 Semicoductor dies with recesses, associated leadframes, and associated systems and methods

Publications (2)

Publication Number Publication Date
TW200913214A TW200913214A (en) 2009-03-16
TWI496267B true TWI496267B (zh) 2015-08-11

Family

ID=39777006

Family Applications (2)

Application Number Title Priority Date Filing Date
TW103137281A TWI553823B (zh) 2007-07-24 2008-07-24 具有凹陷之半導體晶粒，相關之導線架，相關之系統及方法
TW097128166A TWI496267B (zh) 2007-07-24 2008-07-24 具有凹陷之半導體晶粒，相關之導線架，相關之系統及方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW103137281A TWI553823B (zh) 2007-07-24 2008-07-24 具有凹陷之半導體晶粒，相關之導線架，相關之系統及方法

Country Status (4)

Country Link
US (4) US20090026592A1 (zh)
SG (1) SG149724A1 (zh)
TW (2) TWI553823B (zh)
WO (1) WO2009014956A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG149724A1 (en) 2007-07-24 2009-02-27 Micron Technology Inc Semicoductor dies with recesses, associated leadframes, and associated systems and methods
US20130157414A1 (en) * 2011-12-20 2013-06-20 Nxp B. V. Stacked-die package and method therefor
US8957510B2 (en) * 2013-07-03 2015-02-17 Freescale Semiconductor, Inc. Using an integrated circuit die configuration for package height reduction
EP3164886A4 (en) * 2014-07-02 2018-06-20 Intel Corporation Electronic assembly that includes stacked electronic devices
JP6560496B2 (ja) * 2015-01-26 2019-08-14 株式会社ジェイデバイス 半導体装置
CN209517682U (zh) * 2016-05-19 2019-10-18 株式会社村田制作所 多层基板
US11139255B2 (en) 2018-05-18 2021-10-05 Stmicroelectronics (Rousset) Sas Protection of integrated circuits
US10957637B2 (en) * 2019-01-03 2021-03-23 Texas Instruments Incorporated Quad flat no-lead package with wettable flanges
CN111834438A (zh) * 2019-04-18 2020-10-27 西部数据技术公司 半导体部件背侧上用于减轻堆叠封装中的分层的孔结构
US11538739B2 (en) 2020-04-21 2022-12-27 Toyota Motor Engineering & Manufacturing North America, Inc. Compact low inductance chip-on-chip power card
CN113410193B (zh) * 2021-05-27 2024-05-03 元成科技(苏州)有限公司 一种8+1堆叠式芯片封装装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091490A (ja) * 1998-09-11 2000-03-31 Sanyo Electric Co Ltd 半導体装置
US20020096754A1 (en) * 2001-01-24 2002-07-25 Chen Wen Chuan Stacked structure of integrated circuits
TWI248176B (en) * 2001-05-07 2006-01-21 Siliconware Precision Industries Co Ltd Windowing lead-frame semiconductor package structure and fabrication process thereof

Family Cites Families (128)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4766095A (en) * 1985-01-04 1988-08-23 Oki Electric Industry Co., Ltd. Method of manufacturing eprom device
JPS61214565A (ja) 1985-03-20 1986-09-24 Toshiba Corp 半導体光センサ装置
USRE36469E (en) * 1988-09-30 1999-12-28 Micron Technology, Inc. Packaging for semiconductor logic devices
US5334872A (en) * 1990-01-29 1994-08-02 Mitsubishi Denki Kabushiki Kaisha Encapsulated semiconductor device having a hanging heat spreading plate electrically insulated from the die pad
US5145099A (en) * 1990-07-13 1992-09-08 Micron Technology, Inc. Method for combining die attach and lead bond in the assembly of a semiconductor package
JPH05251619A (ja) * 1991-11-05 1993-09-28 Oki Electric Ind Co Ltd 樹脂封止半導体装置およびその製造方法
JPH05299444A (ja) * 1992-04-20 1993-11-12 Oki Electric Ind Co Ltd 薄型樹脂封止半導体装置の製造方法
WO1993023982A1 (en) * 1992-05-11 1993-11-25 Nchip, Inc. Stacked devices for multichip modules
US5327008A (en) * 1993-03-22 1994-07-05 Motorola Inc. Semiconductor device having universal low-stress die support and method for making the same
TW254998B (en) 1993-11-05 1995-08-21 Furnas Electric Co Pressure switch
EP0669650A3 (de) * 1994-02-22 1997-03-19 Siemens Ag Gehäuste Halbleiteranordnung und Verfahren zu deren Herstellung.
TW236718B (zh) 1994-04-21 1994-12-21 Texas Instruments Inc
US5677566A (en) * 1995-05-08 1997-10-14 Micron Technology, Inc. Semiconductor chip package
TW260748B (en) 1995-06-15 1995-10-21 Acer Inc Auto testing equipment for computer
TW310481B (zh) * 1995-07-06 1997-07-11 Hitachi Chemical Co Ltd
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
US5673730A (en) * 1996-01-24 1997-10-07 Micron Technology, Inc. Form tooling and method of forming semiconductor package leads
US5907769A (en) * 1996-12-30 1999-05-25 Micron Technology, Inc. Leads under chip in conventional IC package
US6103547A (en) * 1997-01-17 2000-08-15 Micron Technology, Inc. High speed IC package configuration
US6008996A (en) * 1997-04-07 1999-12-28 Micron Technology, Inc. Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die
US6271582B1 (en) * 1997-04-07 2001-08-07 Micron Technology, Inc. Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die
US5879965A (en) * 1997-06-19 1999-03-09 Micron Technology, Inc. Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication
US6159764A (en) * 1997-07-02 2000-12-12 Micron Technology, Inc. Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages
US5955777A (en) * 1997-07-02 1999-09-21 Micron Technology, Inc. Lead frame assemblies with voltage reference plane and IC packages including same
US5986209A (en) * 1997-07-09 1999-11-16 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US6048744A (en) * 1997-09-15 2000-04-11 Micron Technology, Inc. Integrated circuit package alignment feature
US6005286A (en) * 1997-10-06 1999-12-21 Micron Technology, Inc. Increasing the gap between a lead frame and a semiconductor die
JPH11214607A (ja) * 1998-01-22 1999-08-06 Oki Electric Ind Co Ltd 半導体装置
US6297547B1 (en) * 1998-02-13 2001-10-02 Micron Technology Inc. Mounting multiple semiconductor dies in a package
US6002165A (en) * 1998-02-23 1999-12-14 Micron Technology, Inc. Multilayered lead frame for semiconductor packages
US6429528B1 (en) * 1998-02-27 2002-08-06 Micron Technology, Inc. Multichip semiconductor package
US6089920A (en) * 1998-05-04 2000-07-18 Micron Technology, Inc. Modular die sockets with flexible interconnects for packaging bare semiconductor die
US6329705B1 (en) * 1998-05-20 2001-12-11 Micron Technology, Inc. Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and method of designing and fabricating such leadframes
JP2000012741A (ja) * 1998-06-17 2000-01-14 Hitachi Ltd 半導体装置及びその製造方法
US6201186B1 (en) * 1998-06-29 2001-03-13 Motorola, Inc. Electronic component assembly and method of making the same
US6075283A (en) 1998-07-06 2000-06-13 Micron Technology, Inc. Downset lead frame for semiconductor packages
US6124150A (en) * 1998-08-20 2000-09-26 Micron Technology, Inc. Transverse hybrid LOC package
US6153929A (en) * 1998-08-21 2000-11-28 Micron Technology, Inc. Low profile multi-IC package connector
US6291894B1 (en) * 1998-08-31 2001-09-18 Micron Technology, Inc. Method and apparatus for a semiconductor package for vertical surface mounting
US6084297A (en) 1998-09-03 2000-07-04 Micron Technology, Inc. Cavity ball grid array apparatus
US6261865B1 (en) * 1998-10-06 2001-07-17 Micron Technology, Inc. Multi chip semiconductor package and method of construction
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle
US6740870B1 (en) * 1998-11-18 2004-05-25 Micron Technology, Inc. Clear plastic packaging in a CMOS active pixel image sensor
US6351028B1 (en) * 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
US6310390B1 (en) * 1999-04-08 2001-10-30 Micron Technology, Inc. BGA package and method of fabrication
US7179740B1 (en) 1999-05-03 2007-02-20 United Microelectronics Corporation Integrated circuit with improved interconnect structure and process for making same
US6239489B1 (en) * 1999-07-30 2001-05-29 Micron Technology, Inc. Reinforcement of lead bonding in microelectronics packages
US6303981B1 (en) * 1999-09-01 2001-10-16 Micron Technology, Inc. Semiconductor package having stacked dice and leadframes and method of fabrication
US7211877B1 (en) * 1999-09-13 2007-05-01 Vishay-Siliconix Chip scale surface mount package for semiconductor device and process of fabricating the same
US6271060B1 (en) * 1999-09-13 2001-08-07 Vishay Intertechnology, Inc. Process of fabricating a chip scale surface mount package for semiconductor device
FR2800910B1 (fr) * 1999-11-04 2003-08-22 St Microelectronics Sa Boitier semi-conducteur optique et procede de fabrication d'un tel boitier
KR100377471B1 (ko) 1999-12-10 2003-03-26 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6229202B1 (en) * 2000-01-10 2001-05-08 Micron Technology, Inc. Semiconductor package having downset leadframe for reducing package bow
US6525405B1 (en) * 2000-03-30 2003-02-25 Alphatec Holding Company Limited Leadless semiconductor product packaging apparatus having a window lid and method for packaging
US7132841B1 (en) * 2000-06-06 2006-11-07 International Business Machines Corporation Carrier for test, burn-in, and first level packaging
US6576494B1 (en) * 2000-06-28 2003-06-10 Micron Technology, Inc. Recessed encapsulated microelectronic devices and methods for formation
US6544465B1 (en) * 2000-08-18 2003-04-08 Micron Technology, Inc. Method for forming three dimensional structures from liquid with improved surface finish
US6548757B1 (en) * 2000-08-28 2003-04-15 Micron Technology, Inc. Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies
US6479893B2 (en) * 2000-12-04 2002-11-12 Semiconductor Components Industries Llc Ball-less clip bonding
TW473951B (en) * 2001-01-17 2002-01-21 Siliconware Precision Industries Co Ltd Non-leaded quad flat image sensor package
US20030221313A1 (en) * 2001-01-26 2003-12-04 Gann Keith D. Method for making stacked integrated circuits (ICs) using prepackaged parts
KR100369393B1 (ko) * 2001-03-27 2003-02-05 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법
US6603072B1 (en) * 2001-04-06 2003-08-05 Amkor Technology, Inc. Making leadframe semiconductor packages with stacked dies and interconnecting interposer
KR20030001032A (ko) 2001-06-28 2003-01-06 동부전자 주식회사 멀티 스택형 패키지의 실장 구조
US7102216B1 (en) * 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making
US6759745B2 (en) * 2001-09-13 2004-07-06 Texas Instruments Incorporated Semiconductor device and manufacturing method thereof
US6703700B2 (en) * 2001-10-12 2004-03-09 Cheng-Ho Hsu Semiconductor packaging structure
KR20030075860A (ko) * 2002-03-21 2003-09-26 삼성전자주식회사 반도체 칩 적층 구조 및 적층 방법
KR20030083445A (ko) 2002-04-23 2003-10-30 주식회사 하이닉스반도체 칩 스택 패키지 및 그 제조 방법
US6682955B2 (en) * 2002-05-08 2004-01-27 Micron Technology, Inc. Stacked die module and techniques for forming a stacked die module
US6823582B1 (en) * 2002-08-02 2004-11-30 National Semiconductor Corporation Apparatus and method for force mounting semiconductor packages to printed circuit boards
KR20040031995A (ko) 2002-10-08 2004-04-14 주식회사 하이닉스반도체 반도체 장치의 멀티칩 패키지 방법
US6667543B1 (en) * 2002-10-29 2003-12-23 Motorola, Inc. Optical sensor package
KR100477020B1 (ko) * 2002-12-16 2005-03-21 삼성전자주식회사 멀티 칩 패키지
TW586677U (en) * 2003-01-22 2004-05-01 Via Tech Inc Stack structure of chip package
US6781243B1 (en) * 2003-01-22 2004-08-24 National Semiconductor Corporation Leadless leadframe package substitute and stack package
WO2004070792A2 (en) 2003-02-04 2004-08-19 Advanced Interconnect Technologies Limited Thin multiple semiconductor die package
US7002241B1 (en) * 2003-02-12 2006-02-21 National Semiconductor Corporation Packaging of semiconductor device with a non-opaque cover
JP2004253706A (ja) * 2003-02-21 2004-09-09 Seiko Epson Corp リードフレーム、半導体チップのパッケージング部材、半導体装置の製造方法、及び、半導体装置
JP4123027B2 (ja) * 2003-03-31 2008-07-23 セイコーエプソン株式会社 半導体装置の製造方法
TWM248176U (en) 2003-05-19 2004-10-21 Shian-Jin Gung Structure of embedded multimedia voice box
SG143932A1 (en) * 2003-05-30 2008-07-29 Micron Technology Inc Packaged microelectronic devices and methods of packaging microelectronic devices
US7253506B2 (en) * 2003-06-23 2007-08-07 Power-One, Inc. Micro lead frame package
US20060003483A1 (en) * 2003-07-07 2006-01-05 Wolff Larry L Optoelectronic packaging with embedded window
SG153627A1 (en) * 2003-10-31 2009-07-29 Micron Technology Inc Reduced footprint packaged microelectronic components and methods for manufacturing such microelectronic components
US6930378B1 (en) 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
TWI233170B (en) * 2004-02-05 2005-05-21 United Microelectronics Corp Ultra-thin wafer level stack packaging method and structure using thereof
US7351611B2 (en) * 2004-02-20 2008-04-01 Carsem (M) Sdn Bhd Method of making the mould for encapsulating a leadframe package
TWM251887U (en) 2004-02-24 2004-12-01 Feng-Guei Chen Positioning structure of urn
TWI230426B (en) * 2004-04-07 2005-04-01 Optimum Care Int Tech Inc Packaging method of integrated circuit
TWI240385B (en) * 2004-04-14 2005-09-21 Amertron Inc Global Ltd Lead frame packaging structure and manufacturing method thereof
US7588963B2 (en) * 2004-06-30 2009-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming overhang support for a stacked semiconductor device
WO2006009147A1 (ja) * 2004-07-22 2006-01-26 Sumitomo Bakelite Company, Ltd. 半導体封止用樹脂組成物および半導体装置
US7645639B2 (en) 2004-08-26 2010-01-12 Infineon Technologies Ag Packaging of integrated circuits to lead frames
CN100349288C (zh) 2004-09-22 2007-11-14 日月光半导体制造股份有限公司 无外引脚封装结构
US8324725B2 (en) * 2004-09-27 2012-12-04 Formfactor, Inc. Stacked die module
TWI254998B (en) 2004-09-30 2006-05-11 Jian-Ming Jau Packaged piece and packaging method thereof
US20060087013A1 (en) * 2004-10-21 2006-04-27 Etron Technology, Inc. Stacked multiple integrated circuit die package assembly
TWI251887B (en) 2004-11-09 2006-03-21 Domintech Co Ltd Chip-packaging process without lead frame
TWI236718B (en) 2004-11-16 2005-07-21 Domintech Co Ltd Chip packaging method without lead frame
US7675153B2 (en) * 2005-02-02 2010-03-09 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof
JP4500181B2 (ja) 2005-02-25 2010-07-14 東光東芝メーターシステムズ株式会社 半導体素子収納用パッケージ及び電力量計
US20060208344A1 (en) 2005-03-16 2006-09-21 Shiu Hei M Lead frame panel and method of packaging semiconductor devices using the lead frame panel
US7781299B2 (en) * 2005-03-31 2010-08-24 Kingston Technology Corporation Leadframe semiconductor package stand and method for making the same
CN1845324A (zh) 2005-04-08 2006-10-11 钰创科技股份有限公司 堆叠式多重积体电路祼晶封装组合结构
US7545031B2 (en) 2005-04-11 2009-06-09 Stats Chippac Ltd. Multipackage module having stacked packages with asymmetrically arranged die and molding
WO2006124597A2 (en) 2005-05-12 2006-11-23 Foster Ron B Infinitely stackable interconnect device and method
TW200639978A (en) 2005-05-12 2006-11-16 Chien-Yuan Chen IC packaging technique
US7600312B2 (en) * 2005-07-12 2009-10-13 L.H. Carbide Corporation Die assembly for manufacturing lamina stacks that include formed features
TWI260748B (en) 2005-07-13 2006-08-21 Wen-Fu Jiang Die packaging process and metal plate structure used in packaging process
US7602050B2 (en) * 2005-07-18 2009-10-13 Qualcomm Incorporated Integrated circuit packaging
US7745944B2 (en) 2005-08-31 2010-06-29 Micron Technology, Inc. Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts
US7671478B2 (en) * 2005-09-02 2010-03-02 Honeywell International Inc. Low height vertical sensor packaging
US20070090517A1 (en) * 2005-10-05 2007-04-26 Moon Sung-Won Stacked die package with thermally conductive block embedded in substrate
KR100692520B1 (ko) * 2005-10-19 2007-03-09 삼성전자주식회사 웨이퍼 레벨 패키징 캡 및 그 제조방법
US7663216B2 (en) * 2005-11-02 2010-02-16 Sandisk Corporation High density three dimensional semiconductor die package
CN100531308C (zh) * 2005-12-02 2009-08-19 鸿富锦精密工业（深圳）有限公司 数码相机模组
US7468548B2 (en) * 2005-12-09 2008-12-23 Fairchild Semiconductor Corporation Thermal enhanced upper and dual heat sink exposed molded leadless package
DE202005019706U1 (de) 2005-12-16 2006-02-23 Kingpak Technology Inc., Chupei Bildsensormodul
US20070152314A1 (en) * 2005-12-30 2007-07-05 Intel Corporation Low stress stacked die packages
WO2007089229A1 (en) * 2006-02-01 2007-08-09 Designer Molecules, Inc. Semiconductor die assembly
US7535086B2 (en) * 2006-08-03 2009-05-19 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
US20080131998A1 (en) * 2006-12-01 2008-06-05 Hem Takiar Method of fabricating a film-on-wire bond semiconductor device
SG148054A1 (en) * 2007-05-17 2008-12-31 Micron Technology Inc Semiconductor packages and method for fabricating semiconductor packages with discrete components
US20090020859A1 (en) * 2007-07-18 2009-01-22 Mediatek Inc. Quad flat package with exposed common electrode bars
US7847376B2 (en) * 2007-07-19 2010-12-07 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same
SG149724A1 (en) 2007-07-24 2009-02-27 Micron Technology Inc Semicoductor dies with recesses, associated leadframes, and associated systems and methods
US20090045491A1 (en) * 2007-08-15 2009-02-19 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and leadframe thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091490A (ja) * 1998-09-11 2000-03-31 Sanyo Electric Co Ltd 半導体装置
US20020096754A1 (en) * 2001-01-24 2002-07-25 Chen Wen Chuan Stacked structure of integrated circuits
TWI248176B (en) * 2001-05-07 2006-01-21 Siliconware Precision Industries Co Ltd Windowing lead-frame semiconductor package structure and fabrication process thereof

Also Published As

Publication number Publication date
US9679834B2 (en) 2017-06-13
TWI553823B (zh) 2016-10-11
TW201507094A (zh) 2015-02-16
US10431531B2 (en) 2019-10-01
US20170278775A1 (en) 2017-09-28
WO2009014956A1 (en) 2009-01-29
US10074599B2 (en) 2018-09-11
TW200913214A (en) 2009-03-16
US20180350730A1 (en) 2018-12-06
SG149724A1 (en) 2009-02-27
US20160247749A1 (en) 2016-08-25
US20090026592A1 (en) 2009-01-29

Similar Documents

Publication Publication Date Title
TWI496267B (zh) 具有凹陷之半導體晶粒，相關之導線架，相關之系統及方法
TWI508260B (zh) 具有金屬導線之微電子晶粒封裝、含有金屬導線之堆疊晶粒封裝及相關方法及系統
TWI360189B (en) Integrated circuit package system employing device
TWI334639B (en) Offset integrated circuit package-on-package stacking system and method for fabricating the same
US7947529B2 (en) Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
KR101805114B1 (ko) 이중 측부 연결부를 구비한 집적회로 패키징 시스템 및 이의 제조 방법
KR101542216B1 (ko) 패키지가 집적된 집적회로 패키지 시스템
JP2017515306A (ja) 支持部材を有する積層半導体ダイアセンブリと、関連するシステムおよび方法
TW200919666A (en) Chip package structure and method of manufacturing the same
KR20090101116A (ko) 적층 가능한 소자용 집적회로 패키지 시스템 및 그 제조 방법
TWI430425B (zh) 採用凸塊技術之積體電路封裝件系統
TWI445102B (zh) 具有封裝件整合之積體電路封裝件系統
US8389329B2 (en) Integrated circuit packaging system with package stacking and method of manufacture thereof
US8138591B2 (en) Integrated circuit package system with stacked die
TWI730010B (zh) 用以微型化系統級封裝的被動組件之預模鑄主動積體電路
JP2004031916A (ja) 両面半導体チップのための半導体パッケージ及びその製造方法
TWI380383B (en) Integrated circuit package system with package integration
US20140151870A1 (en) Semiconductor package including a heat-spreading part and method for its manufacture
TWI550823B (zh) 晶片封裝結構
US20090194867A1 (en) Integrated circuit package system with internal stacking module adhesive
US9082887B1 (en) Integrated circuit packaging system with posts and method of manufacture thereof
US8148825B2 (en) Integrated circuit package system with leadfinger
TW200536073A (en) Hybrid integrated circuit package and method of the same
KR20080101208A (ko) 반도체 패키지 및 이의 제조 방법
TW201201349A (en) Stacked assembly and method of chip package