TW200536073A - Hybrid integrated circuit package and method of the same - Google Patents

Abstract

A hybrid integrated circuit package includes a substrate. The substrate has an upper surface and a lower surface. The upper surface includes a molding area, a clamping area and a coupling area. A chip is attached to the molding area. A plurality of surface mounting devices are attached to the coupling area. The chip and the surface mounting devices electrically connect the substrate. The clamping area surrounds the molding area. The substrate has a molding opening passing through the upper surface and the lower surface of the substrate and adjacent to the molding area. A molding compound through the molding opening is molded on the molding area of the substrate for sealing the chip.

Description

200536073

V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a package of an integrated circuit & a package structure of a mixed type integrated circuit.冓 ^, in particular, [prior art] At present, in the semiconductor packaging process, it is usually formed by a transfer mold—a solid-state sealant (m0ldi / ^-the packaging area on the upper surface of the substrate), which is provided in a sealed manner. The seal 〇: n = dagger and in order to enable the solid sealant to be successfully formed in the: device; the film needs 2 s of the surface design on the substrate-a channel area plated with gold,

For integrated circuit (㈣ ... ⑹ package structure, the substrate is formed with a plurality of bonding pads on the substrate around the sealing chip Ϊ), and if a transfer injection molding method is used to form a solid sealant Manufacturing the packaging structure of the mixed-type integrated circuit, the transfer injection mold may be stuck in the bonding pads in the bonding area, and because the substrate: the packaging area is far from the edge of the substrate, it can be overcome The above problems prevent the $ bonding pad from being contaminated or damaged by the mold of the transfer injection mold, but because of the need to design a longer runner area, the waste is increased, the cost is increased, and the injection pressure may be insufficient. The packaging area cannot be filled, so the mixed type product is used. The circuit seal can not be made by the method of #transfer injection molding & solid sealant, and the liquid sealant (liquid commpund) is used to seal the seal. Encapsulate the M area. Please refer to FIGS. 1 and 2 for a conventional package structure 100 of a hybrid integrated circuit, which includes a substrate 110, and the substrate 11 () has an upper surface U1 and a lower surface 112, and an upper surface of the substrate 110. ηι system contains a package

200536073 V. Description of the invention (2) Area 11 3 and a bonding area 1 1 4 The package area 丨 3 is provided with a chip 丨 2 0, and the chip 1 2 0 is provided by a plurality of bonding wires 丨 30 and the The substrate 丨 丨 is electrically connected. The bonding region 114 is provided with a plurality of surface bonding elements 501, and the surface bonding elements 1500 are electrically connected to the substrate 1100. 4 are provided with the surface bonding elements 150, so the wafer 12 and the bonding wire 丨 30 are sealed with a 1 / night sealant 1 4 0 (1 i qu id compound), but with the liquid sealant 1 4 0 Seal the wafer 1 2 0 and the bonding wire 1 3 0, not only the productivity and reliability are not as good as sealing the wafer 1 2 0 and the bonding wire 1 30 with a solid sealant, but also the cost of the liquid sealant 1 40 is higher than the solid seal. The glue is high, but sealing the wafer with a solid-state sealant and the bonding wire 130 will cause problems such as the above-mentioned waste and insufficient injection pressure. [Summary of the Invention] β The main purpose of the present invention is to provide a package structure of a hybrid integrated circuit (Hybrid 1C), which includes a substrate, a wafer, a plurality of surface-bonding elements, and a solid-state sealant. The substrate It has a glue injection port. The sealant injection port penetrates the upper and lower surfaces of the substrate and adjoins the packaging area of the substrate. The solid sealing compound passes through the lower surface of the substrate through the substrate. Seal the injection port and mold (mold) in the packaging area of the substrate to seal the chip. This is to replace the packaging structure of the conventional mixed-type integrated circuit with a liquid sealing compound (1 i qu id compound). Sealed 5 Xuan wafers' to increase productivity and product reliability, and reduce costs. Lu Yi 1 The main purpose of the present invention is to provide a method for manufacturing a package structure of a mixed-type integrated circuit, which is moulded (mo 1 d 1 ng) through a sealant injection port of a substrate—solid state sealant The packaging area of the substrate must be sealed with a wafer 'instead of the conventional packaging structure of a packaged integrated circuit.

Page 7 200536073 V. Description of the invention (3) Seal the chip with glue to improve productivity and product reliability, and reduce costs. The package structure of the mixed-type integrated circuit according to this document includes a substrate, a wafer, a solid-state sealant, and a plurality of surface bonding element boards. The upper surface and the lower surface include an upper surface and a lower surface. A sealing area, a mold clamping area, and a bonding area. The mold clamping area surrounds the packaging area. The substrate has a glue injection port that penetrates the upper surface and the surface of the substrate and abuts the packaging area. The chip is located in the packaging area of the substrate and is electrically connected to the substrate. The solid-state sealant is molded in the packaging area of the substrate through the sealant injection port to seal the chip, and the surface bonding components It is set in the bonding area of the substrate and is electrically connected to the substrate. [Embodiment] Referring to the attached drawings, the present invention will enumerate the following embodiments. According to a specific embodiment of the present invention, please refer to FIGS. 3 and 4, a package structure 200 of a hybrid integrated circuit (Hybrid 1C), which includes a substrate 210, a wafer 220, and a solid-state sealant 230 ( mol ding compound) " and a plurality of surface bonding elements 2 4〇, the material of the substrate 2 1 () may be βτ, FR-4 or FR-5, which has an upper surface 2n and a non-surface 212, The upper surface 211 includes a packaging area 2 13, a mold clamping area 214, and a bonding area 215. The packaging area 2 13 may be rectangular, and the packaging area 213 is formed with a plurality of bonding pads 216. The area 214 surrounds the packaging area 215 and is shaped like a sweet-scented shape. It is located between the packaging area 213 and the bonding area 215, and the width of the mold clamping area 21 4 is not less than i 0mni. The upper mold 3 丨 〇 is closed with the lower mold 3 20 (as shown in FIG. 5C). The bonding area 215 is formed with a plurality of bonding pads 217. The substrate 210 is provided with a glue injection port 218.

Page 8 200536073 V. Description of the invention (4) ί Sim surface 211 and lower surface 212, the corner of the population 218 mf adjacent to the packaging area 213, in this implementation * Λ injection port 218 is adjacent to the packaging area 213 at the same time With this mold, Γ Ϊ Ϊ = 系 20 is a mixed-type integrated circuit (Hybrid material is 1 ° square); the substrate 21 〇 the packaging area 213 on the upper surface 211, and a plurality of fresh wires 250 Electrically connected to the solder pad 216 of the substrate 21, the solid seal 230 is molded through the sealant injection port 218 of the substrate 21—the packaging area 213 'on the upper surface 211 of the substrate 210 and filled A metal layer 2 丨 9 is formed on the side wall of the sealant injection port 2 1 8 at the sealant injection port 21 8 to seal the wafer 220 and the bonding wires 250. The mold flow of 230 at the sealant injection port 218 is relatively smooth, and if necessary, the solid sealant 23 in the sealant injection port 2 丨 8 can be removed. The surface bonding elements 240 are solder 260. The bonding pads 2 1 7 fixed in the bonding area 21 5 are electrically connected to the substrate 2 1 0. The above mixed type product The manufacturing method of the circuit packaging structure 2000, first of all, please refer to FIG. 5A, which is provided with a substrate 2110, the substrate 2 1O upper surface 2 1 1 contains the packaging area 2 3, the combination The die area 2 丨 4 and the bonding area 215, the bonding pads 216 are formed in the packaging area 213, the bonding pads 217 are formed in the bonding area 2 1 5 and the substrate 2 1 0 has an adhesive note The inlet 218 penetrates the upper surface 21] 1 and the lower surface 212 of the substrate 21, the glue injection port 21 8 is disposed at a corner of the packaging area 21 3 and is adjacent to the packaging area 21 3, and the sealing glue Note that the metal layer 21 9 is formed on the side wall of the entrance 21 8; referring to FIG. 5B again, the chip 2 2 0 is mounted on the packaging area 213 ′ of the substrate 21 0 and electrically connected by the bonding wires 250. Pads 216 on the substrate 210;

Page 9 200536073 V. Description of the invention (5) Please refer to FIG. 5C again, through the sealant injection port 21 8, mold the solid sealant 2 3 0 in the packaging area 2 1 0 of the substrate 2 1 3. When the package structure 200 of the mixed-type integrated circuit is sealed, the upper mold 31 and the lower mold 320 are clamped to press the upper surface 21] 1 and the lower surface 212 of the substrate 21, The upper mold 310 has a mold surface 311 and a cavity 312. The mold surface 311 presses the mold clamping area 2 1 4 of the substrate 2 1 0, so that the mold cavity 3 1 2 corresponds to the mold 210 of the substrate 210. In the packaging area 213, the lower mold 32 0 has a first-rate channel 321, and the flow channel 32Γ corresponds to the sealant injection port 218 of the substrate 210, so that the solid sealant 2 3 0 flows out through the flow channel 3 2 1. Then inject the cavity 312 of the upper mold 310 through the sealant injection port 2 1 8 to mold the packaging area 2 1 3 of the upper surface 2 11 of the substrate 21 and seal the wafer 2 2 0 and the These bonding wires are shown in FIG. 4. Referring to FIG. 4 again, the surface bonding elements 240 are fixed to the bonding region 213 of the substrate 210 by using solder 260 and the surface bonding elements are fixed. 2 4 0 is electrically connected to the bonding pads 2 1 7 of the substrate 21 10. Since the substrate 21 0 has a sealant injection port 2 1 8 penetrating the upper surface 21] 1 and the lower surface 2 1 2, the solid-state seal is used when manufacturing the package structure 200 of the mixed-type integrated circuit. The glue 230 can be transferred to the encapsulation area 21 3 of the upper surface 2 11 of the substrate 2 1 0 through the sealant injection port 218 through the lower surface 21 1 of the substrate 2 10 through a transfer mold. The wafer 2 2 0 and the bonding wires 2 50 are used to replace the conventional mixed-type integrated circuit. The structure of the chip must be sealed with a liquid compound (1 i quid compound) and the bonding wires 2 5 0, and it is not necessary to design a conventional flow channel region on the upper surface 211 of the substrate 2 10 to improve the production capacity and product reliability of the package structure 2000 of the mixed integrated circuit, and reduce costs.

200536073 V. Description of the invention (6) The scope of protection of the present invention shall be determined by the scope of the appended patent application. Any person skilled in the art will make any changes and modifications without departing from the spirit and scope of the present invention. All belong to the protection scope of the present invention.

Page 11 200536073

Brief description of the diagram [Schematic description of the diagram] ί Ge \ Picture: Top view of the package structure of the conventional mixed-type integrated circuit & circle,! ^ 2. Figure: Package structure of the conventional mixed-type integrated circuit Sectional drawing 3: A schematic plan view of a packaging structure of a body circuit according to the present invention. FIG. 4: A schematic cross-sectional view of a packaging structure of a circuit according to the present invention. FIGS. 5A to 5C: A packaging structure of a body circuit according to the present invention. A specific embodiment of the manufacturing method of the substrate constructed in the manufacturing process, a mixed type product map; ~ a specific embodiment, the mixed type product, and a specific embodiment, a mixed type so far, the mixed type The cover of the integrated circuit is shown. Brief description of component symbols: I 0 0 Package structure of integrated circuit 112 Lower surface 1 4 0 Liquid sealant II 0 Substrate 111 upper surface 11 3 Packaging area 11 4 Bonding area 1 2 0 Chip 1 3 0 Welding wire 1 5 0 Surface-bonding component 200 210 213 216 219 Package structure substrate for mixed integrated circuit 211 Upper surface packaging area 214 Molding area solder pad 21 7 Bonding pad metal layer 220 Wafer

2 1 2 Lower surface 21 5 Bonding area 218 Seal injection port 230 Solid sealant

The 12th tribute 200536073 Brief description of the drawing 2 4 0 Surface bonding element 2 5 0 Glow line 3 1 1 Mold surface 3 2 1 Flow channel 2 6 0 Solder 3 1 2 Mold cavity 3 1 0 Upper mold 320 Lower mold page 13 Μ

Claims (1)

200536073 6. Scope of patent application [Patent for patent application 1. A mixed substrate includes a package area, the upper surface of which is connected to the next chip; a solid-state package of several watches and the Substrate electrical properties 2, such as applying for a special structure, where the 3, such as applying for a special structure, where the 4, such as applying for a special structure, where the 5, such as applying for a special structure, where the 6, such as applying for a special structure, and the area. 7. A packaging structure for a mixed integrated circuit, including ..., having an upper surface and a lower surface, the upper surface system area, a mold clamping area, and a bonding area, the mold clamping area having A glue injection port penetrates the surface of the substrate and abuts the packaging area; it is provided in the packaging area of the substrate, and is electrically connected to the substrate's electrical glue, its mounting area, and surface. The solid-state sealing range, the clamping range, the sealing range, the sealing range, the sealing range, the sealing range, the sealing range, and the sealing-molding system are molded by the sealing injection port to seal the chip; It is set in the bonding area of the substrate, and the sealing glue of the mixed type integrated circuit described in item 11 is filled in the sealing glue injection port. 〇_。 The width of the package of the mixed type integrated circuit described in item 1 is not less than 1. 〇_. 2. The side wall of the entrance of the sealed integrated circuit described in item 1 is formed with a metal layer. The sealed inlet of the mixed type integrated circuit described in item 1 is located at the corner of the package area. The entrance of the mixed-type integrated circuit described in item 1 is the packaging structure adjacent to the packaging area and the input mode circuit at the same time, including: 200536073 Six 'patent application scope a substrate, including a package, the substrate has a lower surface and abutting, a chip, connected; and its system has an upper surface and a lower surface, the upper surface system area and a mold clamping area, the combination The mold area surrounds the packaging area / one glued population, which passes through the substrate ^ III the packaging area; ^ It is located in the packaging area of the substrate, and is electrically sealed to the substrate with the substrate The sealant injection port 8 is applied for a special structure, wherein the 9, is applied for a special structure, wherein the 10, is applied for a special structure, wherein 11, is applied for a special structure, and the area. 12. A mixed package provided with a base upper surface including a region is mounted on the substrate through a crystal-solid sealant, which is molded through the sealant injection port. In order to seal the chip, the solid sealant is filled in the package clamping area of the mixed type integrated circuit described in the profit range item 7 with a width of not less than 0. 0mm. A metal layer is formed on the side wall of the sealant injection port of the mixed type integrated circuit as described in the seventh item of the utility model. The encapsulation of the mixed integrated circuit described in item 7 of the scope of interest is provided at the corner of the packaging area. The method for manufacturing a package seal injection port of the mixed type integrated circuit described in item 7 of the utility model is adjacent to the packaging structure of the packaging area and the combined integrated circuit. The manufacturing method includes: On the surface and the lower surface, there is a packaging area, a mold clamping area, and a bonding area. The mold clamping area 'the substrate has a glue injection port, which runs through the surface and the lower surface and is adjacent to the packaging area; Package area of a substrate, the chip is electrically connected to the substrate 200536073 Through the sealant injection port, molding—a sealing region of the solid-state sealant substrate to seal the wafer; and ~ fixing a plurality of surface-bonding elements to a bonding region of the substrate, the surface The bonding element is electrically connected to the substrate. 1-3. The manufacturing method of the packaging structure of the mixed type integrated circuit as described in item 丨 2 of the scope of patent application, wherein the solid-state sealant is filled in the sealant injection, π 〇4, as in the scope of patent application The manufacturing method of the packaging structure of the mixed type integrated circuit described in Item 12, wherein the width of the mold clamping area is not less than h 0 mm 15. The mixed type described in Item 12 of the scope of patent application A method for manufacturing a sealed structure of an integrated circuit, wherein a sidewall of the sealant injection port is formed with a metal layer. 16. The manufacturing method of the package structure of the mixed-type integrated circuit as described in item 12 of the scope of the patent application, wherein the inlet of the sealant is set at a corner of the packaging area. 17. The manufacturing method of the package structure of the mixed type integrated circuit as described in item 2 of the patent application scope, wherein the 対 # 浲 entrance is adjacent to the packaging area and the mold clamping area at the same time.