TWI509770B - Semiconductor device with stacked mosfets and method of manufacture - Google Patents
Semiconductor device with stacked mosfets and method of manufacture Download PDFInfo
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- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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Description
本發明一般涉及一種功率半導體器件及制備方法，更確切的說，本發明涉及一種包含雙MOSFET的堆疊式封裝結構及其制備方法。The present invention generally relates to a power semiconductor device and a method of fabricating the same, and more particularly to a stacked package structure including a dual MOSFET and a method of fabricating the same.
隨著晶片尺寸縮小的趨勢，器件熱傳導工程在半導體工藝和器件性能改善方面所起的作用越來越明顯，如何使最終所獲得的封裝體具有最小尺寸，或者說使內部封裝的晶片尺寸最大，這是對半導體行業的一個挑戰。尤其是在一些功耗較大的封裝類型上，如DC-DC轉換器，通常將N型的高端和低端MOSFET封裝在同一封裝體內。As wafer size shrinks, device thermal conduction engineering plays an increasingly important role in semiconductor process and device performance improvement, how to minimize the size of the resulting package, or maximize the size of the internal package. This is a challenge for the semiconductor industry. Especially in some power-consuming package types, such as DC-DC converters, N-type high-side and low-side MOSFETs are usually packaged in the same package.
例如圖1及圖2A-2E是在當前技術中一種將兩個晶片封裝在一個堆疊式半導體器件內的透視結構示意圖，圖2A是圖1中封裝體10沿A-A線的橫截面結構示意圖，圖2B是圖1中封裝體10沿B-B線的橫截面結構示意圖，圖2C是圖1中封裝體10沿C-C線的橫截面結構示意圖。圖1是封裝體10的俯視透視示意圖，頂層金屬片11a、11b與圖2A-2B中的第一晶片15正面的電極電性連接，該金屬片11a、11b作為電極導出端子的同時還用於散熱。圖2B-2C中金屬片12a、12b位於第一晶片15之下並與第一晶片16背面的部分電極電性連接，同時金屬片12a、12b還與第二晶片16正面的電極電性連接，而第二晶片16背面的電極則與底層金屬片13焊接，金屬片13不僅是連接晶片16的電極至外界的信號端子，還作為散熱片。圖2E是封裝體10的仰視結構示意圖，引腳13a、13b、13c、13d分布在金屬片13的四周，並且引腳13a連接在金屬片13上。參見圖2C，其中引腳13b、13d分別通過具有向上延伸並大概靠近金屬片12a所 在平面的延伸部分13e、13f而與金屬片11a、11b焊接。為了便於解釋和簡潔的進行示意，將第一晶片15的電極與金屬片11a、11b、12a焊接的焊接材料在圖2A-2C中並未進行圖示，同樣將第二晶片16的電極與金屬片12a、12b、13a焊接的焊接材料在圖2A-2C中並未進行圖示。For example, FIG. 1 and FIG. 2A - 2E are schematic perspective views of a package in which a two-chip package is packaged in a stacked semiconductor device, and FIG. 2A is a schematic cross-sectional view of the package 10 of FIG. 2B is a schematic cross-sectional view of the package body 10 along the BB line in FIG. 1, and FIG. 2C is a schematic cross-sectional view of the package body 10 in FIG. 1 is a top perspective view of the package body 10. The top metal sheets 11a, 11b are electrically connected to the electrodes on the front surface of the first wafer 15 in FIGS. 2A-2B, and the metal sheets 11a, 11b are used as electrode lead terminals. Cooling. 2B-2C, the metal sheets 12a, 12b are located under the first wafer 15 and are electrically connected to the partial electrodes on the back surface of the first wafer 16, and the metal sheets 12a, 12b are also electrically connected to the electrodes on the front surface of the second wafer 16. The electrode on the back surface of the second wafer 16 is soldered to the underlying metal sheet 13, which is not only a signal terminal for connecting the electrodes of the wafer 16 to the outside, but also serves as a heat sink. 2E is a bottom view of the package body 10, the pins 13a, 13b, 13c, 13d are distributed around the metal piece 13, and the leads 13a are connected to the metal piece 13. Referring to FIG. 2C, in which the pins 13b, 13d respectively have an upward extension and are approximately adjacent to the metal piece 12a. The metal sheets 11a, 11b are welded to the flat extending portions 13e, 13f. For ease of explanation and succinct illustration, the solder material for soldering the electrodes of the first wafer 15 to the metal sheets 11a, 11b, 12a is not illustrated in FIGS. 2A-2C, and the electrodes and metal of the second wafer 16 are also similar. The solder material soldered to the sheets 12a, 12b, 13a is not illustrated in Figures 2A-2C.
另外，金屬片11a與金屬片11b具有垂直方向上的高度差， 金屬片11a與金屬片11b並不處於同一平面。因此，圖2D所示的封裝體10的俯視結構中，金屬片11b所在的位置低於金屬片11a所在位置，所以金屬片11b被塑封在封裝體10內，而金屬片11a的頂面則外露於封裝體10的塑封料之外。在圖2B中，為了避免金屬片12b觸及到第一晶片15的背面，還設置了與金屬片10b在垂直方向上的位置比金屬片12a的位置低。實際上，在該方案中將兩個晶片進行堆疊封裝所採用的引線框的結構較為複雜，大量使用了金屬片，致使其制備工藝難以實現而且可靠性極低，封裝體的最終體積也很大。基於該等問題，提出了本發明後續所提供的各種實施例。In addition, the metal piece 11a and the metal piece 11b have a height difference in the vertical direction. The metal piece 11a and the metal piece 11b are not in the same plane. Therefore, in the planar structure of the package 10 shown in FIG. 2D, the position of the metal piece 11b is lower than the position of the metal piece 11a, so the metal piece 11b is molded in the package 10, and the top surface of the metal piece 11a is exposed. It is outside the molding compound of the package 10. In FIG. 2B, in order to prevent the metal piece 12b from coming into contact with the back surface of the first wafer 15, the position in the vertical direction with respect to the metal piece 10b is set lower than the position of the metal piece 12a. In fact, the structure of the lead frame used for stacking and packaging two wafers in this solution is complicated, and a large number of metal sheets are used, which makes the preparation process difficult to implement and the reliability is extremely low, and the final volume of the package is also large. . Based on these issues, various embodiments provided by the present invention are presented.
在本發明的一種實施例中，揭示的集成堆疊式多晶片的半導體器件包括：一帶有相互分離的第一、第二和第三基座的晶片安裝單元，在第一基座的主平板部分的一對相對的側緣中，一個側緣連接有與主平板部分具高度落差的一引腳以及相對的另一個側緣附近設置有第二、第三基座；在主平板部分的靠近第二、第三基座的側緣的兩端之一處形成有一切口，第三基座具有與第一基座的引腳、第二基座共面的一引腳和具有嵌入在切口中的且與主平板部分共面的一臺面部分；一倒裝安裝的第一晶片，其正面的多個電極通過金屬凸塊分別相對應的電性連接到主平板部分和臺面部分上；一設置在第一晶片之上的金屬片，包括水平方向上延伸的本體部分和自本體部分一側緣向下彎折延伸直至接觸第二基座的一側翼；以及一粘貼至主平板部分的底面上的第二晶片，第二晶片正面的各電極上設置的金屬凸塊的頂端面與第一和第三基座各自引腳的底面、第二基座的底面位於同一平面上。In one embodiment of the present invention, a disclosed stacked multi-wafer semiconductor device includes: a wafer mounting unit having first, second, and third pedestals separated from each other, in a main slab portion of the first pedestal One of the pair of opposite side edges, one side edge is connected with a pin having a height difference from the main flat plate portion, and the other side edge is provided with a second and third base portion; the main plate portion is close to the first Second, a slit is formed at one of the two ends of the side edge of the third pedestal, and the third pedestal has a pin coplanar with the pin of the first pedestal and the second pedestal and has a surface embedded in the slit a countertop portion coplanar with the main flat plate portion; a flip-chip mounted first wafer having a plurality of electrodes on the front surface electrically connected to the main flat plate portion and the mesa portion via respective metal bumps; a metal piece above the first wafer, comprising a body portion extending in a horizontal direction and a side wing extending downward from a side edge of the body portion until contacting a side of the second base; and a paste onto the bottom surface of the main flat plate portion Second wafer, Electrodes provided on the bottom surface of each of the two front wafer to the top surface of the metal bumps and the first and third base of each pin, the bottom surface of the second base on the same plane.
上述的半導體器件，第一晶片背面的電極通過導電粘合材料 電性連接到本體部分上，第二晶片背面的電極通過導電粘合材料電性連接到主平板部分上。In the above semiconductor device, the electrode on the back surface of the first wafer passes through the conductive adhesive material Electrically connected to the body portion, the electrodes on the back side of the second wafer are electrically connected to the main flat plate portion by a conductive adhesive material.
上述的半導體器件，包括將晶片安裝單元、第一和第二晶 片、金屬片及各金屬凸塊予以包覆的一塑封體，其包覆方式為至少使第一和第三基座各自引腳的底面、第二基座的底面、第二晶片正面的各電極上焊接的金屬凸塊的頂端面皆從塑封體的底面予以外露。The above semiconductor device includes a wafer mounting unit, first and second crystals a molding body coated with a sheet, a metal sheet and each metal bump, which is covered by at least a bottom surface of each of the first and third pedestals, a bottom surface of the second pedestal, and a front surface of the second wafer The top end faces of the metal bumps welded on the electrodes are exposed from the bottom surface of the molded body.
上述的半導體器件，第一晶片正面覆蓋有一塑封層，包覆在 第一晶片正面的電極上安置的金屬凸塊的側壁周圍，並使金屬凸塊從塑封層中外露出來從而將第一晶片的電極連接至臺面部分的頂面和主平板部分頂面；並且塑封層被包覆在所述塑封體內。In the above semiconductor device, the front surface of the first wafer is covered with a plastic sealing layer, and is coated on a side wall of the metal bump disposed on the electrode on the front surface of the first wafer, and exposing the metal bump from the outside of the plastic sealing layer to connect the electrode of the first wafer to the top surface of the mesa portion and the top surface of the main flat portion; and molding A layer is coated in the molded body.
上述的半導體器件，第二晶片正面覆蓋有一塑封層，包覆在 第二晶片正面的電極上安置的金屬凸塊的側壁周圍，並使金屬凸塊的頂端面從塑封層中外露出來；並且塑封層被包覆在所述塑封體內。In the above semiconductor device, the front surface of the second wafer is covered with a plastic sealing layer, and is coated on The side surface of the metal bump disposed on the electrode on the front surface of the second wafer is exposed, and the top end surface of the metal bump is exposed from the outside of the plastic sealing layer; and the plastic sealing layer is coated in the plastic sealing body.
上述的半導體器件，所述本體部分的頂面從所述塑封體的頂 面予以外露。In the above semiconductor device, the top surface of the body portion is from the top of the molded body The face is exposed.
在本發明的一種實施例中，揭示的一種集成堆疊式多晶片的 半導體器件的制備方法，包括以下步驟：提供帶有相互分離的第一、第二和第三基座的晶片安裝單元，在第一基座的主平板部分的一對相對的側緣中，一個側緣連接有與主平板部分具高度落差的一引腳以及相對的另一個側緣附近設置有第二、第三基座；其中在主平板部分的靠近第二、第三基座的側緣的兩端之一處形成一切口，第三基座具有與第一基座的引腳、第二基座共面的一引腳和具有嵌入在切口中的且與主平板部分共面的一臺面部分；將一第一晶片進行倒裝安裝，其正面的多個電極通過金屬凸塊分別相對應的電性連接到在臺面部分的頂面和主平板部分頂面上；將一金屬片粘貼至第一晶片上，同時將自金屬片的本體部分一側緣向下彎折延伸的一側翼與第二基座進行粘接；翻轉帶有第一晶片、金屬片的晶片安裝單元；將一第二晶片粘貼至主平板部分的底面上，使第二晶片正面的各電極上設置的金屬凸塊的頂端面與第一和第三基座各自引腳的底面、第二基座的底面位於同一平面上。In an embodiment of the invention, an integrated stacked multi-wafer is disclosed A method of fabricating a semiconductor device, comprising the steps of: providing a wafer mounting unit with first, second, and third pedestals separated from each other, one of a pair of opposite side edges of a main slab portion of the first pedestal The side edge is connected with a pin having a height difference from the main flat plate portion and the opposite side is provided with a second and third base; wherein the side edge of the main flat plate portion adjacent to the second and third bases Forming a port at one of the two ends, the third base has a pin coplanar with the pin of the first base, the second base, and a body having a surface embedded in the slit and coplanar with the main plate portion a mesa portion; a first wafer is flip-chip mounted, and a plurality of electrodes on the front surface are electrically connected to the top surface of the mesa portion and the top surface of the main flat portion through metal bumps respectively; and a metal sheet is pasted Adhering to the first wafer, and bonding a side wing bent downward from a side edge of the body portion of the metal sheet to the second base; flipping the wafer mounting unit with the first wafer and the metal piece; Paste the second wafer to the main flat section The bottom surface of the second wafer front surface electrode provided on the end surface of each metal bump of the first and third base of each pin of the bottom surface, the bottom surface of the second base on the same plane.
上述方法，第一晶片正面的電極上安置的金屬凸塊包含焊錫 材料，其具有第一熔點，金屬片通過具第二熔點的導電粘合材料粘接到第一晶片背面的電極和第二基座上；第二晶片背面的電極通過具第三熔點的導電粘合材料電性連接到主平板部分上，其中第一、二熔點值高於第三熔點值。In the above method, the metal bumps disposed on the electrodes on the front surface of the first wafer include solder a material having a first melting point, the metal sheet being bonded to the electrode on the back surface of the first wafer and the second pedestal through a conductive adhesive material having a second melting point; the electrode on the back surface of the second wafer passing through the conductive paste having a third melting point The composite material is electrically connected to the main flat plate portion, wherein the first and second melting point values are higher than the third melting point value.
上述方法，第一晶片正面電極上安置的為非焊錫材料的金屬 凸塊，其通過具第一熔點的導電粘合材料粘接到主平板部分或臺面部分上，金屬片通過具第二熔點的導電粘合材料粘接到第一晶片背面的電極和第二基座上；第二晶片背面的電極通過具第三熔點的導電粘合材料電性連接到主平板部分上，其中第一、二熔點值高於第三熔點值。In the above method, the metal of the non-solder material is disposed on the front electrode of the first wafer a bump bonded to the main flat plate portion or the mesa portion by a conductive adhesive material having a first melting point, the metal sheet being bonded to the electrode on the back surface of the first wafer and the second base through a conductive adhesive material having a second melting point The electrode on the back side of the second wafer is electrically connected to the main flat plate portion through a conductive adhesive material having a third melting point, wherein the first and second melting point values are higher than the third melting point value.
上述方法，還包括利用一塑封體將晶片安裝單元、第一和第 二晶片、金屬片及各金屬凸塊予以包覆的步驟，其包覆方式為至少使第一和第三基座各自引腳的底面、第二基座的底面、第二晶片正面各電極上安置的金屬凸塊的頂端面皆從塑封體的底面予以外露。The above method further includes using a plastic package to mount the wafer, the first and the first The step of coating the two wafers, the metal sheet and the metal bumps is carried out by at least a bottom surface of each of the first and third pedestals, a bottom surface of the second pedestal, and an electrode on the front surface of the second wafer The top ends of the metal bumps placed are exposed from the bottom surface of the molded body.
上述方法，第一晶片正面覆蓋有一塑封層，包覆在第一晶片 正面的電極上安置的金屬凸塊的側壁周圍，並使金屬凸塊從塑封層中外露出來從而將第一晶片的電極連接至臺面部分的頂面和主平板部分頂面；在形成塑封體的塑封步驟中，塑封層還被塑封體包覆。In the above method, the front surface of the first wafer is covered with a plastic sealing layer and coated on the first wafer. a metal bump is disposed on the front surface of the metal bump, and the metal bump is exposed from the plastic sealing layer to connect the electrode of the first wafer to the top surface of the mesa portion and the top surface of the main flat portion; In the molding step, the plastic sealing layer is also covered by the molding body.
上述方法，第二晶片正面覆蓋有一塑封層，包覆在第二晶片 正面的電極上安置的金屬凸塊的側壁周圍，並使金屬凸塊的頂端面從塑封層中外露出來；在形成所述塑封體的塑封步驟中，塑封層還被塑封體包覆。In the above method, the front surface of the second wafer is covered with a plastic sealing layer and coated on the second wafer. The side surface of the metal bump disposed on the front electrode is disposed, and the top end surface of the metal bump is exposed from the outside of the plastic sealing layer; in the molding step of forming the plastic sealing body, the plastic sealing layer is further covered by the molding body.
上述方法，還包括在塑封體的底面粘附一保護膜的步驟，將 第二晶片正面的各電極上安置的金屬凸塊覆蓋住但第一和第三基座各自引腳的底面、第二基座的底面未被保護膜所覆蓋；之後再在第一、第二和第三基座外露於塑封體的表面上鍍上保護層。The above method further comprises the step of adhering a protective film on the bottom surface of the molded body, Metal bumps disposed on the electrodes on the front surface of the second wafer cover but the bottom surfaces of the respective pins of the first and third pedestals, and the bottom surface of the second pedestal are not covered by the protective film; then in the first and second And a protective layer is plated on the surface of the third base exposed on the plastic body.
上述的方法，還包括在所述塑封體的底面進行研磨的步驟， 以避免第二晶片正面的各電極上安置的金屬凸塊的頂端面及第一和第三基座各自引腳的底面、第二基座的底面被塑封料覆蓋住。The above method, further comprising the step of grinding on the bottom surface of the molded body, The top surface of the metal bumps disposed on the electrodes on the front surface of the second wafer and the bottom surfaces of the respective pins of the first and third pedestals, and the bottom surface of the second pedestal are covered by the molding compound.
本領域的技術人員閱讀以下較佳實施例的詳細說明，並參照 附圖之後，本發明的這些和其他方面的優勢無疑將顯而易見。Those skilled in the art will read the detailed description of the following preferred embodiments and refer to These and other advantages of the present invention will no doubt become apparent from the drawings.
10‧‧‧封裝體10‧‧‧Package
11a、11b‧‧‧頂層金屬片11a, 11b‧‧‧ top metal sheet
15‧‧‧第一晶片15‧‧‧First chip
12a、12b‧‧‧金屬片12a, 12b‧‧‧metal pieces
16‧‧‧第二晶片16‧‧‧second chip
13‧‧‧金屬片13‧‧‧metal piece
13a、13b、13c、13d‧‧‧引腳Pins 13a, 13b, 13c, 13d‧‧‧
13e、13f‧‧‧延伸部分13e, 13f‧‧‧ extension
10b‧‧‧金屬片10b‧‧‧metal piece
150‧‧‧半導體器件150‧‧‧Semiconductor devices
110‧‧‧安裝單元110‧‧‧Installation unit
101‧‧‧第一基座101‧‧‧First base
102‧‧‧第二基座102‧‧‧Second base
103‧‧‧第三基座103‧‧‧ Third base
101a-1‧‧‧左側邊緣101a-1‧‧‧left edge
101b‧‧‧引腳101b‧‧‧ pin
101a-2‧‧‧右側邊緣101a-2‧‧‧ right edge
101a-4‧‧‧後側邊緣101a-4‧‧‧back side edge
101c‧‧‧切口101c‧‧‧ incision
110’‧‧‧晶片安裝單元110’‧‧‧ wafer mounting unit
103b‧‧‧引腳103b‧‧‧ pin
103a‧‧‧臺面部分103a‧‧‧ countertop part
101a‧‧‧主平板部分101a‧‧‧Main tablet section
104‧‧‧第一晶片104‧‧‧First chip
105‧‧‧金屬片105‧‧‧metal pieces
105a‧‧‧本體部分105a‧‧‧ body part
105b‧‧‧側翼105b‧‧‧Flanking
106‧‧‧第二晶片106‧‧‧second chip
110‧‧‧晶片安裝單元110‧‧‧ wafer mounting unit
106a-1、106b-1‧‧‧金屬凸塊106a-1, 106b-1‧‧‧ metal bumps
107‧‧‧塑封體107‧‧‧plastic body
108‧‧‧保護膜108‧‧‧Protective film
206‧‧‧功率晶片206‧‧‧Power chip
2060‧‧‧晶片2060‧‧‧ wafer
206b‧‧‧柵極206b‧‧‧Gate
206a‧‧‧源極206a‧‧‧ source
206b-1‧‧‧金屬凸塊206b-1‧‧‧metal bumps
206a-1‧‧‧金屬凸塊206a-1‧‧‧Metal bumps
250‧‧‧塑封層250‧‧‧plastic layer
2061‧‧‧晶圓2061‧‧‧ wafer
2500‧‧‧覆蓋層2500‧‧‧ Coverage
2700‧‧‧金屬化層2700‧‧‧metallization
206’‧‧‧晶片206’‧‧‧ wafer
270‧‧‧金屬層270‧‧‧metal layer
參考所附附圖，以更加充分的描述本發明的實施例。然而，所附附圖僅用於說明和闡述，並不構成對本發明範圍的限制。Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.
圖1~圖2E是背景技術涉及到的堆疊式半導體器件的示意圖。1 to 2E are schematic views of a stacked semiconductor device related to the background art.
圖3A是本發明形成的堆疊式半導體器件的透視結構示意圖。3A is a perspective structural schematic view of a stacked semiconductor device formed by the present invention.
圖3B-1~圖3H是形成堆疊式半導體器件的流程示圖。3B-1 to 3H are flow diagrams for forming a stacked semiconductor device.
圖4A~圖4F是所集成的晶片的一些可選類型的結構示意圖及簡略的制備流程。4A-4F are schematic diagrams of some alternative types of integrated wafers and a simplified preparation process.
圖3A是集成堆疊式多晶片的半導體器件150的透視結構示意圖，其具體結構將在後續內容中詳細介紹。在圖3B-1或圖3B-2中，金屬材質的晶片安裝單元110包含相互分離的第一基座101、第二基座102和第三基座103，未示意出的引線框架通常包含多個這樣的晶片安裝單元110，而每個晶片安裝單元110的第一基座101、第二基座102和第三基座103均依賴於未示意出的連筋來與引線框架的支撐條連接在一起才得以固持。第一基座101包含一方形的主平板部分101，第二基座102和第三基座103設置在主平板部分101的左側邊緣101a-1附近，第一基座101所含的一個長條狀的引腳101b連接在主平板部分101的右側邊緣101a-2上並沿著右側邊緣101a-2的長度方向延伸，引腳101b與主平板部分101兩者間具有高度落差，後者的高度較之前者要高。如圖3B-1的晶片安裝單元110，左側邊緣101a-1與主平板部分101的後側邊緣101a-4的拐角處具有一矩形切口101c，而使實質為矩形的主平板部分101形成為L形結構。如圖3B-2所示，在另一種晶片安裝單元110’中，左側邊緣101a-1與主平板部分101的前側邊緣101a-3的拐角處具有一矩形切口101c，所以切口101c可以設置在左側邊緣101a-1的兩個端部中任意之一處。此處人為設定的“前後左右”僅僅是為了敘述的方便，不構成特定的限制條件。另外，長條狀的第二基座102沿著左側邊緣101a-1的長度方向延伸。第三基座103具有相互連接一引腳103b和一臺面部分103a，它們之間存在高 度落差，後者的高度較之前者要高，臺面部分103a嵌入在切口101c中。其中，臺面部分103a與主平板部分101a處於一公共平面上，可直接作為一引腳使用的第二基座102與引腳103b、引腳101b處於另一公共平面上。FIG. 3A is a schematic perspective view of a semiconductor device 150 incorporating a stacked multi-wafer, the specific structure of which will be described in detail later. In FIG. 3B-1 or FIG. 3B-2, the metal wafer mounting unit 110 includes a first pedestal 101, a second pedestal 102, and a third pedestal 103 separated from each other, and the unillustrated lead frame usually includes a plurality of Such a wafer mounting unit 110, and the first pedestal 101, the second pedestal 102, and the third pedestal 103 of each of the wafer mounting units 110 are connected to the support bars of the lead frame depending on the ribs not illustrated. Only together can they be held. The first base 101 includes a square main plate portion 101, and the second base 102 and the third base 103 are disposed near the left side edge 101a-1 of the main flat plate portion 101, and the first base 101 includes a strip. The pin 101b is connected to the right side edge 101a-2 of the main flat plate portion 101 and extends along the length direction of the right side edge 101a-2, and the height difference between the pin 101b and the main flat plate portion 101 is higher than that of the main plate portion 101. The former is higher. As shown in the wafer mounting unit 110 of Fig. 3B-1, the left side edge 101a-1 and the rear side edge 101a-4 of the main flat plate portion 101 have a rectangular slit 101c at the corner, and the substantially rectangular main flat plate portion 101 is formed as L. Shape structure. As shown in FIG. 3B-2, in another wafer mounting unit 110', the left side edge 101a-1 has a rectangular cutout 101c at the corner of the front side edge 101a-3 of the main flat plate portion 101, so the slit 101c can be disposed on the left side. Any one of the two ends of the edge 101a-1. The "front, rear, left, and right" set by the person here is merely for convenience of description and does not constitute a specific restriction condition. Further, the elongated second pedestal 102 extends along the longitudinal direction of the left side edge 101a-1. The third pedestal 103 has a pin 103b and a mesa portion 103a connected to each other with a high height therebetween. The height difference is higher than the former, and the mesa portion 103a is embedded in the slit 101c. The mesa portion 103a and the main flat portion 101a are on a common plane, and the second pedestal 102 and the lead 103b and the lead 101b, which can be directly used as one pin, are on another common plane.
如圖3C，將一個第一晶片104也即高端MOSFET倒裝安裝到臺面部分103a和主平板部分101a各自的項面上。在一些實施方式中，先在高端MOSFET正面的各個電極上植上金屬凸塊。如果植在N通道的高端MOSFET正面的柵極或源極上的金屬凸塊(Bumping)自身不是焊錫類材料，如銅或其他金屬或合金，則無法起到焊接的作用，需要塗覆導電的粘合材料(如焊錫膏)至臺面部分103a的頂面和主平板部分101a的頂面上，再將安置在柵極電極上的金屬凸塊通過粘合材料與臺面部分103a進行粘接，和將安置在源極電極上的金屬凸塊通過粘合材料與主平板部分101a進行粘接。在一些實施方式中，如果金屬凸塊為包含焊錫類材料的物質，則上述塗覆導電粘合材料的步驟可以省去，因為金屬凸塊自身在受熱的條件下，就可以將柵極或源極直接電性及機械的連接到臺面部分103a或主平板部分101a上。在一些實施方式中，第一晶片104正面覆蓋有一塑封層，包覆在第一晶片104正面的電極上安置的金屬凸塊的側壁周圍，並使金屬凸塊從塑封層中外露出來，從而可以將柵極、源極對應的電性連接至臺面部分103a的頂面和主平板部分分101a的頂面上。基於圖3C中視覺角度的關系，這些結構在圖3C中沒有體現，但是後續內容中如圖4A~4F將會詳細介紹。As shown in Fig. 3C, a first wafer 104, i.e., a high-side MOSFET, is flip-chip mounted to the respective faces of the mesa portion 103a and the main plate portion 101a. In some embodiments, metal bumps are first implanted on the respective electrodes on the front side of the high side MOSFET. If the bump on the gate or source of the front side of the high-side MOSFET of the N-channel is not itself solder-like material, such as copper or other metals or alloys, it will not function as a solder, and it needs to be coated with a conductive paste. a bonding material (such as solder paste) to the top surface of the mesa portion 103a and the top surface of the main flat portion 101a, and then bonding the metal bumps disposed on the gate electrode to the mesa portion 103a through the bonding material, and The metal bumps disposed on the source electrodes are bonded to the main flat plate portion 101a by an adhesive material. In some embodiments, if the metal bump is a material containing a solder-based material, the step of coating the conductive adhesive material may be omitted because the metal bump itself may be under a heated condition, and the gate or source may be used. It is extremely directly electrically and mechanically connected to the mesa portion 103a or the main plate portion 101a. In some embodiments, the front surface of the first wafer 104 is covered with a plastic coating layer covering the sidewalls of the metal bumps disposed on the electrodes on the front surface of the first wafer 104, and the metal bumps are exposed from the plastic sealing layer, thereby Correspondingly, the gate and the source are electrically connected to the top surface of the mesa portion 103a and the top surface of the main flat portion 101a. These structures are not shown in Fig. 3C based on the relationship of the visual angles in Fig. 3C, but will be described in detail later in Figs. 4A to 4F.
如圖3D，在第一晶片104背面的金屬化層如漏極電極上塗覆導電的粘合材料，以及在第二基座102的頂面上塗覆導電的粘合材料，從而將金屬片105粘接在第一晶片104和第二基座102上。金屬片105包括大致為矩形並位於於水平面的本體部分105a，和包括自本體部分105a的一側緣向下彎折延伸的一側翼105b，第一晶片104背面的電極通過導電粘合材料電性連接到本體部分105a上。安裝金屬片105之後，側翼105b延伸至其前端接觸第二基座102的頂面，從而可以通過第二基座102項面上的粘合材料與第二基座102實施焊接，以保持兩者間的電性及機械連接關系。這之後還往往需要執行標准工藝的回流焊的步驟。As shown in FIG. 3D, a conductive adhesive material is coated on a metallization layer such as a drain electrode on the back surface of the first wafer 104, and a conductive adhesive material is coated on the top surface of the second susceptor 102, thereby bonding the metal sheet 105. Connected to the first wafer 104 and the second pedestal 102. The metal piece 105 includes a body portion 105a that is substantially rectangular and located at a horizontal plane, and a side wing 105b that is bent downwardly from a side edge of the body portion 105a. The electrodes on the back surface of the first wafer 104 are electrically conductive by a conductive adhesive material. Connected to the body portion 105a. After the metal piece 105 is installed, the side flap 105b extends to the front end of the second base 102 so that the front end thereof can be welded to the second base 102 through the adhesive material on the second base 102 to maintain the two. Electrical and mechanical connections. It is often necessary to perform the reflow soldering steps of the standard process after this.
如圖3E~3F，翻轉帶有第一晶片104、金屬片105的晶片 安裝單元110，讓主平板部分101a的底面朝上(這之前的工藝過程中該底面一直是保持朝下)，然後塗覆導電的粘合材料至該底面上，用於將第二晶片106也即N通道的低端MOSFET粘貼到主平板部分101a的底面上。很容易理解，因為大量晶片安裝單元110均被固定在一條引線框架上，所以只要翻轉一條引線框架則其上的每個晶片安裝單元110都得以翻轉。該步驟中，第二晶片106的背面朝向主平板部分101a的底面，其背面的金屬化層如漏極電極可通過粘合材料與主平板部分101a的底面實現電性連接，第二晶片106的正面則背離主平板部分101a的底面。值得注意的是，設置第二晶片106盡量遠離切口101c，避免其背面的電極接觸到嵌入在切口101c中的臺面部分103a，防止低端MOSFET的漏極和高端MOSFET的柵極直接短接。這之後同樣還需要執行標准工藝的回流焊的步驟。第二晶片106的粘貼步驟中，很重要的一點是，要使第二晶片106正面的各電極(如源極、柵極)上設置的金屬凸塊(如106a-1、106b-1)的頂端面與第一基座的引腳101b的底面、第三基座103引腳的底面103b、第二基座102的底面位於同一平面上。3E~3F, flipping the wafer with the first wafer 104 and the metal piece 105 The mounting unit 110 has the bottom surface of the main flat plate portion 101a facing upward (the bottom surface is kept facing downward during the previous process), and then a conductive adhesive material is applied to the bottom surface for the second wafer 106 to be That is, the N-channel low-side MOSFET is attached to the bottom surface of the main flat plate portion 101a. It is easily understood that since a large number of wafer mounting units 110 are fixed to one lead frame, each wafer mounting unit 110 thereon can be flipped as long as one lead frame is flipped. In this step, the back surface of the second wafer 106 faces the bottom surface of the main flat plate portion 101a, and the metallization layer of the back surface such as the drain electrode can be electrically connected to the bottom surface of the main flat plate portion 101a by the adhesive material, and the second wafer 106 is The front side faces away from the bottom surface of the main flat plate portion 101a. It is to be noted that the second wafer 106 is disposed as far as possible from the slit 101c, and the electrode on the back side thereof is prevented from contacting the mesa portion 103a embedded in the slit 101c, preventing the drain of the low-side MOSFET and the gate of the high-side MOSFET from being directly short-circuited. This also requires a reflow soldering step of the standard process. In the pasting step of the second wafer 106, it is important to make metal bumps (such as 106a-1, 106b-1) disposed on the electrodes (such as the source and the gate) of the front surface of the second wafer 106. The top end surface is on the same plane as the bottom surface of the pin 101b of the first pedestal, the bottom surface 103b of the third pedestal 103 pin, and the bottom surface of the second pedestal 102.
我們設定，第一晶片104正面的電極通過具第一熔點的金 屬凸塊(如焊錫類材料)來電性連接到主平板部分101a和臺面部分103a上，或者，正面的電極上安置的金屬凸塊(非焊錫類材料)通過具第一熔點的粘合材料來電性連接到主平板部分101a和臺面部分103a上，本體部分105a、側翼105b分別通過具第二熔點的導電粘合材料相對應的粘接到第一晶片104背面的電極上和第二基座102上，對於材料的選擇，第一、二熔點值可設定為完全相同或相差不大。同時，塗覆在主平板部分101a底面的具第三熔點值的導電粘合材料將第二晶片106背面的漏極電極電性連接到主平板部分101上，我們要求前述的第一、二熔點值高於該第三熔點值，原因在於，完成第二晶片106的粘貼之後需要進行對塗覆在主平板部分101a底面上的導電材料的回流焊，但是這一回流焊的使用的溫度步驟不能影響第一晶片104的金屬凸塊(焊錫類材料)、用來粘接金屬片105至第一晶片104和第二基座102上的粘合材料，避免該金屬凸塊或導電材料進 入熔融態而導致第一晶片104、金屬片105松動或脫落(例如晶片安裝單元110翻轉後它們自身的重力是一個誘因)。同樣，另一些實施例中，用來粘接第一晶片104的金屬凸塊(非焊錫類材料)和主平板部分101a、臺面部分103a的粘合材料，也不能受到塗覆在主平板部分101a底面上的導電材料的回流焊的影響。We set the electrode on the front side of the first wafer 104 to pass the gold with the first melting point. A bump (such as a solder-like material) is electrically connected to the main flat plate portion 101a and the mesa portion 103a, or a metal bump (non-solder material) placed on the front electrode is electrically fed through a bonding material having a first melting point. Connected to the main plate portion 101a and the mesa portion 103a, the body portion 105a and the side flaps 105b are respectively bonded to the electrodes on the back surface of the first wafer 104 and the second pedestal 102 by corresponding conductive bonding materials having a second melting point. Above, for the choice of materials, the first and second melting point values can be set to be identical or not much different. At the same time, a conductive adhesive material having a third melting point coated on the bottom surface of the main flat plate portion 101a electrically connects the drain electrode on the back surface of the second wafer 106 to the main flat plate portion 101, and we require the aforementioned first and second melting points. The value is higher than the third melting point value because reflow soldering of the conductive material coated on the bottom surface of the main flat plate portion 101a is required after the bonding of the second wafer 106 is completed, but the temperature step of the use of this reflow soldering cannot be performed. A metal bump (solder-like material) affecting the first wafer 104, a bonding material for bonding the metal piece 105 to the first wafer 104 and the second pedestal 102, to prevent the metal bump or conductive material from entering The molten state causes the first wafer 104 and the metal piece 105 to loosen or fall off (for example, their own gravity is a cause after the wafer mounting unit 110 is turned over). Also, in other embodiments, the bonding material of the metal bump (non-solder type material) for bonding the first wafer 104 and the main flat plate portion 101a and the mesa portion 103a cannot be coated on the main flat plate portion 101a. The effect of reflow soldering of conductive material on the bottom surface.
如圖3G，利用環氧樹脂之類的塑封料形成一個塑封體 107，將晶片安裝單元110、第一晶片104和第二晶片106、金屬片105及各晶片上安置的各個金屬凸塊予以包覆，其包覆方式為至少使引腳101b和103b各自的底面、第二基座102的底面、第二晶片106正面柵極和源極上安置的金屬凸塊106b-1和106a-1的頂端面皆從塑封體107的底面予以外露，可以結合圖3A進行理解。塑封工藝的詳細步驟是，引線框架上的每個晶片安裝單元110及其帶有的第一晶片104、第二晶片106、金屬片105和各晶片上安置的各個金屬凸塊均被一個整體性的封裝體塑封包覆住，封裝體是由注入在塑封模具中的塑封料經固化成型才形成的。之後對任意兩個相鄰晶片安裝單元110之間的封裝體和引線框架實施切割，其實也即沿著引線框架上預設的切割線實施切割，引線框架經切割後(主要是第一至第三基座與支撐條的連筋被切斷)使晶片安裝單元110的各個構件與原始引線框架分離斷開，與此同時，該整體性的封裝體經過切割後形成多個類似於圖3G中單個的塑封體107。在一些實施方式中，還包括在封裝體的底面也即後續定義為塑封體107的底面進行研磨的步驟，因為塑封工序中很難完全阻止溢料的發生，研磨步驟可避免第二晶片106正面的各電極上安置的金屬凸塊106a-1、106a-2的頂端面、及引腳101b、103b各自的底面、第二基座102的底面被塑封料覆蓋住，容易覆蓋住這些區域的溢料(Molding flash)可以在研磨步驟中被完全研磨移除掉。As shown in Fig. 3G, a molding compound is formed by using a molding compound such as an epoxy resin. 107. The wafer mounting unit 110, the first wafer 104 and the second wafer 106, the metal piece 105, and the respective metal bumps disposed on the respective wafers are covered by at least the bottom surfaces of the pins 101b and 103b. The bottom surface of the second pedestal 102, the front surface of the second wafer 106, and the top surfaces of the metal bumps 106b-1 and 106a-1 disposed on the source are exposed from the bottom surface of the molding body 107, which can be understood in conjunction with FIG. 3A. . The detailed steps of the molding process are that each of the wafer mounting units 110 on the lead frame and the first wafer 104, the second wafer 106, the metal piece 105, and the respective metal bumps disposed on each wafer are integrated. The package is covered by a plastic package, and the package is formed by curing the molding compound injected into the mold. Then, the package and the lead frame between any two adjacent wafer mounting units 110 are cut, that is, the cutting is performed along the preset cutting line on the lead frame, and the lead frame is cut (mainly first to first) The three pedestals and the ribs of the support strip are cut) to separate the respective components of the wafer mounting unit 110 from the original lead frame, and at the same time, the integral package is cut to form a plurality of similar to FIG. 3G. A single molded body 107. In some embodiments, the step of grinding on the bottom surface of the package, that is, the bottom surface of the package body 107 is further defined, because it is difficult to completely prevent the occurrence of flash in the molding process, and the polishing step can avoid the front surface of the second wafer 106. The top end faces of the metal bumps 106a-1, 106a-2 disposed on the respective electrodes, and the bottom surfaces of the pins 101b, 103b and the bottom surface of the second pedestal 102 are covered by the molding compound, and it is easy to cover the overflow of these regions. The Molding flash can be completely removed by grinding in the grinding step.
在塑封步驟中，在一些實施例中，可以選擇金屬片105被 封裝體也即後續切割為塑封體107完全包覆住。在另一些實施例中，也可以選擇讓本體部分105b的頂面從封裝體的頂面也即在切割步驟之後定義為塑封體107的頂面中外露出來，作為消散第一晶片104、第二晶片106所產生的熱量的一個途徑，具有較佳的散熱效果，因為功率MOSFET的功 耗比較大，所以產生的熱量也大。In the molding step, in some embodiments, the metal sheet 105 can be selected to be The package, that is, the subsequent cut, is completely covered by the molded body 107. In other embodiments, the top surface of the body portion 105b may also be selected to be exposed from the top surface of the package, that is, the top surface of the molding body 107 after the cutting step, as the first wafer 104 and the second wafer are dissipated. One way of heat generated by the wafer 106 has better heat dissipation because of the power of the power MOSFET The consumption is relatively large, so the heat generated is also large.
在一些實施方式中，完成研磨之後，還包括在封裝體的底面 也即後續定義為塑封體107的底面粘附保護膜108的步驟，如圖3H，保護膜108用於將第二晶片106的柵極和源極上安置的金屬凸塊106b-1和106a-1覆蓋住，但第一基座101和第三基座103各自的引腳101b和103b的底面、第二基座102的底面仍然是裸露的，未被保護膜108覆蓋住，這之後再在第一基座101、第二基座102和第三基座103外露於塑封體107的表面上鍍上金屬保護層，起到防氧化和為表面安裝工序SMT提供促進焊接的效果。比如利用電鍍層覆蓋引腳101b和103b外露的底面和側面及覆蓋第二基座102外露的底面和側面，應用保護膜108是因為如果金屬凸塊106b-1和106a-1為焊錫材料則它們不需要進行電鍍。通常形成保護層之後就可以揭去保護膜108。實施鍍保護層的步驟在對引線框架和封裝體進行切割之前。在一些實施方式中，如果金屬凸塊106b-1和106a-1不含焊錫材料，則完成研磨之後可直接進行電鍍工序而無需保護膜108，金屬凸塊106b-1和106a-1的外露表面也可以鍍上金屬保護層。In some embodiments, after the grinding is completed, it is also included on the bottom surface of the package. That is, the step of subsequently adhering to the protective film 108 is adhered to the bottom surface of the molded body 107. As shown in FIG. 3H, the protective film 108 is used to place the metal bumps 106b-1 and 106a-1 on the gate and the source of the second wafer 106. Covered, but the bottom surfaces of the respective pins 101b and 103b of the first pedestal 101 and the third pedestal 103 and the bottom surface of the second pedestal 102 are still bare and are not covered by the protective film 108, and then A pedestal 101, a second pedestal 102, and a third pedestal 103 are exposed on the surface of the molding body 107 with a metal protective layer to prevent oxidation and provide an effect of promoting soldering for the surface mounting process SMT. For example, the exposed bottom surface and side surfaces of the leads 101b and 103b and the exposed bottom surface and side surface of the second pedestal 102 are covered with a plating layer, and the protective film 108 is applied because if the metal bumps 106b-1 and 106a-1 are solder materials, they are No plating is required. The protective film 108 can be removed after the protective layer is usually formed. The step of applying a protective layer is performed before the lead frame and the package are cut. In some embodiments, if the metal bumps 106b-1 and 106a-1 are free of solder material, the plating process can be directly performed after the completion of the polishing without the protective film 108, and the exposed surfaces of the metal bumps 106b-1 and 106a-1 It can also be plated with a metal protective layer.
圖4A~4B是功率MOSFET的晶片206的鳥瞰示意圖，功 率晶片206可以應用於第一晶片104或第二晶片106。針對應用於第一晶片104，晶片2060正面設置有柵極206b和源極206a，為了滿足第一晶片104在倒裝步驟中其柵極206b上植的金屬凸塊206b-1能與圖3C中的臺面部分103b進行對准粘接，柵極206b設置在晶片2060正面的一個角落處(第二晶片106的柵極電極無此布局要求)，源極206a上植的金屬凸塊206a-1是為了與圖3C中與主平板部分101a對准粘接。此實施例中，晶片2060正面沒有設置任何塑封層。4A-4B are bird's eye view of the wafer 206 of the power MOSFET, The rate wafer 206 can be applied to the first wafer 104 or the second wafer 106. For the application of the first wafer 104, the front surface of the wafer 2060 is provided with a gate 206b and a source 206a, and the metal bump 206b-1 implanted on the gate 206b of the first wafer 104 in the flip-chip step can be used in FIG. 3C. The mesa portion 103b is aligned and bonded, and the gate 206b is disposed at a corner of the front surface of the wafer 2060 (the gate electrode of the second wafer 106 has no such layout requirement), and the metal bump 206a-1 implanted on the source 206a is For alignment with the main flat plate portion 101a in Fig. 3C. In this embodiment, no plastic encapsulation layer is provided on the front side of the wafer 2060.
圖4C~4F是在晶片2060正面形成塑封層250的方法。如 圖4C，矽片或晶圓2061通常包含大量的鑄造連接在一起的譬如圖4A所示的晶片2060，先行在晶圓2061中各晶片2060正面的各電極上植上金屬凸塊，譬如在源極和柵極上分別安置圖4B所示的金屬凸塊206a-1、206b-1，然後再在晶圓2061正面形成由塑封料構成的一覆蓋層2500，覆蓋層2500至此將各金屬凸塊都包覆住。之後對覆蓋層2500進行研磨減 薄，從覆蓋層2500的減薄頂面中外露出各金屬凸塊，並且形成各個金屬凸塊各自的平坦化的頂端面，如圖4D所示。基於覆蓋層2500的物理支撐作用，晶圓2061的機械強度得到加強，所以在晶圓背面進行研磨的步驟中晶圓2061可以研磨得足夠薄，來降低功率MOSFET的襯底電阻。之後再在晶圓2061的減薄背面沉積一金屬化層2700，如圖4E。再依照切割道來實施切割工序，對晶圓2061、覆蓋層2500和金屬化層2700進行切割，來形成圖4F所示的晶片206’，晶圓2061經切割分離後形成多個晶片2060，覆蓋層2500經切割後形成每個晶片2060正面的一塑封層250，包覆在金屬凸塊206a-1、206b-1側壁的周圍，金屬凸塊206a-1、206b-1的頂端面從塑封層250中外露出來，金屬化層2700經切割後形成每個晶片2060背面的金屬層270作為漏極電極。4C-4F are methods of forming a mold layer 250 on the front side of the wafer 2060. Such as 4C, the wafer or wafer 2061 typically comprises a plurality of wafers 2060, as shown in FIG. 4A, cast together, with metal bumps implanted on the electrodes on the front side of each wafer 2060 in the wafer 2061, such as at the source. The metal bumps 206a-1 and 206b-1 shown in FIG. 4B are respectively disposed on the poles and the gates, and then a cover layer 2500 composed of a molding compound is formed on the front surface of the wafer 2061, and the cover layer 2500 has the metal bumps Covered. Then, the cover layer 2500 is ground and reduced. Thin, each metal bump is exposed from the thinned top surface of the cover layer 2500, and the flattened top end faces of the respective metal bumps are formed as shown in FIG. 4D. Based on the physical support of the cover layer 2500, the mechanical strength of the wafer 2061 is enhanced, so that the wafer 2061 can be ground thin enough to reduce the substrate resistance of the power MOSFET in the step of polishing the back side of the wafer. A metallization layer 2700 is then deposited on the thinned back side of the wafer 2061, as shown in FIG. 4E. Then, the dicing process is performed according to the dicing street, and the wafer 2061, the capping layer 2500 and the metallization layer 2700 are diced to form the wafer 206' shown in FIG. 4F, and the wafer 2061 is diced and separated to form a plurality of wafers 2060, covering The layer 2500 is cut to form a plastic layer 250 on the front surface of each of the wafers 2060, wrapped around the sidewalls of the metal bumps 206a-1, 206b-1, and the top end faces of the metal bumps 206a-1, 206b-1 are from the plastic seal layer. The outer portion of the 250 is exposed, and the metallization layer 2700 is diced to form a metal layer 270 on the back surface of each of the wafers 2060 as a drain electrode.
功率晶片206’可以應用於第一晶片104或第二晶片106。 如果第一晶片104的正面覆蓋有塑封層250，則在對晶片安裝單元110、第一晶片104和第二晶片106、金屬片105及第一和第二晶片各自的金屬凸塊進行塑封的步驟中，塑封層250直接包覆在第一晶片104的金屬凸塊側壁周圍，而塑封體107則進一步將第一晶片104正面覆蓋的塑封層250包覆在內；同樣，如果第二晶片106的正面覆蓋有塑封層250，塑封層250直接包覆在第二晶片104的金屬凸塊側壁周圍，而塑封體107則進一步將第二晶片106正面覆蓋的塑封層250包覆在內，並且第二晶片106正面覆蓋的塑封層250的頂面連同第二晶片106各個電極上所植的金屬凸塊的頂端面，同時從封裝體的底面也即在封裝體的切割步驟之後定義為塑封體107的底面中一並外露。The power die 206' can be applied to the first wafer 104 or the second wafer 106. If the front surface of the first wafer 104 is covered with the mold layer 250, the steps of molding the metal bumps of the wafer mounting unit 110, the first wafer 104 and the second wafer 106, the metal sheet 105, and the first and second wafers are respectively performed. The plastic sealing layer 250 is directly coated around the metal bump sidewall of the first wafer 104, and the molding body 107 further covers the plastic sealing layer 250 covered by the front surface of the first wafer 104; likewise, if the second wafer 106 is The front surface is covered with a plastic sealing layer 250, and the plastic sealing layer 250 is directly wrapped around the metal bump sidewall of the second wafer 104, and the molding body 107 further covers the plastic coating layer 250 covering the front surface of the second wafer 106, and the second The top surface of the molding layer 250 covered by the front surface of the wafer 106 together with the top surface of the metal bumps implanted on the respective electrodes of the second wafer 106 is defined as the molding body 107 from the bottom surface of the package body, that is, after the cutting step of the package body. The bottom surface is exposed together.
對於本領域的技術人員而言，閱讀上述說明後，各種變化和修正無疑將顯而易見。因此，所附的申請專利範圍書應看作是涵蓋本發明的真實意圖和範圍的全部變化和修正。在申請專利範圍書範圍內任何和所有等價的範圍與內容，都應認為仍屬本發明的意圖和範圍內。Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and Any and all equivalent ranges and contents within the scope of the claims are intended to be within the spirit and scope of the invention.
150‧‧‧半導體器件150‧‧‧Semiconductor devices
101‧‧‧第一基座101‧‧‧First base
102‧‧‧第二基座102‧‧‧Second base
103‧‧‧第三基座103‧‧‧ Third base
104‧‧‧第一晶片104‧‧‧First chip
105‧‧‧金屬片105‧‧‧metal pieces
107‧‧‧塑封體107‧‧‧plastic body
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| TW102146696A TWI509770B (en) | 2013-12-17 | 2013-12-17 | Semiconductor device with stacked mosfets and method of manufacture |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050151235A1 (en) * | 2004-01-14 | 2005-07-14 | Tetsuya Yokoi | Semiconductor device and manufacturing method for the same |
| US20070145609A1 (en) * | 2005-12-22 | 2007-06-28 | Xiaotian Zhang | Semiconductor package having improved thermal performance |
| US20070246772A1 (en) * | 2006-03-31 | 2007-10-25 | James Lee | MOSFET power package |
| US20090130799A1 (en) * | 2006-09-07 | 2009-05-21 | Sanjay Havanur | Stacked dual MOSFET package |
| US20110233746A1 (en) * | 2010-03-29 | 2011-09-29 | Kai Liu | Dual-leadframe Multi-chip Package and Method of Manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050151235A1 (en) * | 2004-01-14 | 2005-07-14 | Tetsuya Yokoi | Semiconductor device and manufacturing method for the same |
| US20070145609A1 (en) * | 2005-12-22 | 2007-06-28 | Xiaotian Zhang | Semiconductor package having improved thermal performance |
| US20070246772A1 (en) * | 2006-03-31 | 2007-10-25 | James Lee | MOSFET power package |
| US20090130799A1 (en) * | 2006-09-07 | 2009-05-21 | Sanjay Havanur | Stacked dual MOSFET package |
| US20110233746A1 (en) * | 2010-03-29 | 2011-09-29 | Kai Liu | Dual-leadframe Multi-chip Package and Method of Manufacture |
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