TWI240394B - Semiconductor package for 3D package - Google Patents

Abstract

A semiconductor package for 3D package is used for stacking an electrical component mainly includes a substrate with double side connection, a chip and a molding compound. An upper surface of the substrate defines a molding area and a stacking area. The molding compound is formed on the molding area for sealing the chip. The substrate includes an integrated barrier mechanism on the upper surface. The barrier mechanism is formed between the molding area and the stacking area for separating the molding area and the stacking area, so that the mold flash of the molding compound can be avoided to contaminate a plurality of ball pads on the stacking area.

Description

1240394 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor three-dimensional package (3D package). In particular, the present invention relates to a semiconductor package structure suitable for three-dimensional packaging. Electronic components to form a three-dimensional package. [Prior art] A conventional 3D package is a chip that can integrate many different functions, such as an SRAM chip, an Application Specific Integrated Circuit (ASIC) chip, a memory chip, and a flash memory ( flash) or synchronous dynamic random access memory (SDRAM) to achieve complete electrical performance, which is used in built-in multi-function electronic products such as mobile phones and digital cameras. ROC Patent Bulletin No. 554509 "Multi-chip Package Structure" discloses a conventional three-dimensional package structure in which an interposer substrate is sandwiched between two stacked package structures. Please refer to FIG. 丨. The three-dimensional package structure 10 () includes a semiconductor carrier package structure 110, an interposer substrate 120, and a semiconductor package structure 130. The first semiconductor wafer ill system of the semiconductor carrier package structure HQ is On the top surface 112 & of a base substrate 112, and the first semiconductor wafer ill is coated in the first encapsulant 114. A first group of pads 115 and a second group of pads 116 are provided on the upper surface 112a of the base substrate 112, and a third group of pads 117 is provided on the lower surface 1121 of the base substrate 112. The 11 7 series is electrically connected to the first group of pads 5 and the second group of pads 116. The first semiconductor wafer lu is electrically connected to the first group of pads 115 of the base substrate 112 by a plurality of bonding wires ι3. The second set of pads 116 is ring-connected to the first set of pads 115 and is electrically connected by a plurality of first solder balls.

1240394 V. Description of the invention (2) The interposer substrate 120 connected to it. A plurality of second solder balls 119 are disposed on the third group of pads 117 for electrical connection to the outside. The second semiconductor wafer 131 of the semiconductor package structure 130 is disposed on an upper surface 13 2a of a connection substrate 132 and is electrically connected to the connection pads 134 of the connection substrate 132 through a plurality of bonding wires 133. Covered in the second sealant 35. The connection substrate 132 is electrically connected to the connection pad 134 and the second external pad 122 of the interposer 120 through a plurality of solder balls 136. Therefore, the interposer substrate 120, the first solder balls 118, and the solder balls 136 can electrically connect the semiconductor carrier package structure 110 and the semiconductor package structure 130.

In the semiconductor carrier package structure 110, in addition to the upper surface 11 2a of the base substrate 112 can be provided for the formation of the semiconductor wafer π! And the first encapsulant 114, an appropriate peripheral area needs to be reserved for the first The second group then connected to 116. However, during the sealing process, the first sealing compound 114 easily overflows to the first group of pads 116. Especially in the case of pursuing a small and thin package volume today, the area of the upper surface 112a is getting smaller and smaller, and the distance between the second group of pads 115 and the molding area of the first sealant 114 will be closer, The second group of pads 115 will be more likely to be covered by mold flash. Therefore, it is not conducive to bonding the solder balls, resulting in electrical connection failure. Please refer to FIG. 2. Another conventional three-dimensional package structure 200 is a semiconductor package structure 220 stacked directly on a semiconductor carrier package structure 2 10. One of the semiconductor carrier package structures 2 10 has a circuit board 211. The surface 211a and the lower surface 211b, the upper surface 211a is formed with a plurality of first pads 212, and the lower surface 211b is formed with a plurality of second pads 213. A chip 21 4 is electrically connected to the circuit substrate 211 with a plurality of bonding wires 2 1 5.

Page 7 1240394___ V. Description of the invention (3) A molding compound 2 1 6 is formed on the upper surface 2 1 1 a, which seals the wafer 2 1 4 and the bonding wires 2 1 5 and exposes these First pad 2 1 2. The semiconductor carrier package structure 210 includes a plurality of solder balls 217, which are disposed on the second pads 2 1 3 of the circuit substrate 2 1 1 for external electrical connection. In addition, the upper surface 221a of one of the circuit substrates 221 of the semiconductor package structure 220 is provided with a plurality of wafers 222, and the wafers 222 are electrically connected to the circuit substrate 2 21 with a plurality of bonding wires 2 2 3 and are molded. The gel 2 2 4 is sealed. A plurality of spacer balls 230 are disposed on the lower surface 221 b of the circuit substrate 221. As the electrical connection components of the semiconductor carrier package structure 21 〇 and the semiconductor package structure 2 2 ′, the spacer balls 2 3 0 are connected to the first pads 212 of the circuit substrate 2 1 1 and the circuit. A plurality of pads 225 of the substrate 221. However, in the semiconductor carrier package structure 21 〇, because the upper surface 2ι1 & forming the mold compound 216 and the first pads 212 are small distance, when the mold compound 216 overflow occurs, then The first pads 21 2 can be flashed, or the spacer balls 2 3 0 cannot be joined. [Summary of the Invention] ... The main object of the present invention is to provide a semiconductor package structure suitable for three-dimensional packaging, which is used to stack an electronic component. A circuit substrate included in the semiconductor package structure has an upper surface system = There are = molding area and-stacking area, a plurality of pads are formed in the stack and the area, the circuit board system includes an isolation mechanism (barrler mechanism) integrally formed on the upper surface, such as a bar (_U1 ... ), Strip groove or ring groove (_ula ^

(1) page 8 1240394 5. Description of the invention (4) groove), the isolation mechanism is located between the molding area and the stacking area to block the molding area and the pads to prevent a molding gel A molding compound overflows to the stacking area and contaminates the pads to facilitate stacking and bonding of electronic components. ... A second object of the present invention is to provide a semiconductor package structure suitable for three-dimensional packaging. An isolation mechanism is integrally formed on one surface of a circuit substrate, and the isolation mechanism is a closed loop. To effectively isolate one of the molding area and a stacking area of the upper surface to achieve a better barrier effect to avoid a molding gel or die attaching

Pieces s ’D / A process) overflows to the stacking area. Another object of the present invention is to provide a circuit substrate suitable for three-dimensional packaging. A plurality of first pads and a plurality of second pads are respectively formed on an upper surface and a lower surface of the circuit substrate and are electrically connected to each other. The upper surface defines a molding area and a stacking area. An isolation mechanism is integrally formed on the upper surface and is located between the molding area and the stacking area to prevent one of the molding gels from overflowing during the packaging process. Glue to the stacking area and contaminate the first contacts. ', Mouth ^ Another object of the present invention is to provide a three-dimensional package structure, which is stacked with a semiconductor carrier package structure and an electronic component, wherein the conductor carrier package structure-the circuit substrate system includes an isolation mechanism, The t isolation mechanism is integrally formed on one of the upper surfaces of the circuit substrate and is located between a molding area and a stacking area to block the molding area and the stacking area and prevent the molding gel from overflowing and contaminating the stack. A plurality of connections in the area are used to facilitate the stacking and bonding of the electronic component. Page 9 1240394

The three-dimensional package suitable for the three-dimensional package according to the present invention includes a circuit substrate, a wafer, and a stacking area with a top surface and a second pad. The molding areas of the 5th circuit substrate are Between the circuit bases is used to isolate the glue to the stacking area and the lower surface, and the surface of the semiconductor mold compound on the surface is a fixed packaging structure. The circuit substrate includes a plurality of circuit substrates and an isolation mechanism. The first and second connections are formed on the upper surface, the mold is sealed to seal the wafer, the upper surface of the board is juxtaposed with the mold sealing area and the lower surface of the stack, and the spacer is in the form of a glue system. In the mold sealing area, a mold has a first pad sealing area, and a plurality of the pads are arranged on the pad system to form the wafer system. The circuit board is separated from the mechanism system into an integrated area and the stacking area stops the mold. [Embodiment] With reference to the attached drawings, the present invention will enumerate the following embodiments. According to a first specific embodiment of the present invention, please refer to FIG. 3, a semiconductor package structure 300 suitable for three-dimensional packaging mainly includes a circuit substrate 310, which includes an integrally formed isolation mechanism 3li (baRier mechanism), To prevent the occurrence of glue overflow during the molding process. The semiconductor package structure 300 further includes a wafer 320 and a molding compound 3 300 (molding compound). The semiconductor package structure 300 is used to stack an electronic component with a plurality of external terminals (not shown). The electronic element series may be the above-mentioned semiconductor package structure 130 or 22 (), and a package structure (3D Package). Please refer to Figures 3 and 4 at the same time. The circuit board 310 has an upper surface 312 and a lower surface 313. The upper surface 312 defines a molding area gw 1240394. 5. Description of the invention (6) and a stack District 31 5. In the present embodiment, the molding area 314 is located at the center of the upper surface 312, and the stacking area 315 surrounds the molding area 314 and is located around the upper surface 312. The isolation mechanism 311 is integrally formed on the upper surface 312 of the circuit substrate 310 and is located between the molding area 314 and the stacking area 315 ′ to isolate the molding area 3 丨 4 and the stacking area 3 丨 5. In order to prevent the molding compound 3 30 from overflowing to the stacking area 315. The isolation mechanism 311 utilizes the special design of the circuit substrate 310, which can be a solder mask pattern / metal pattern, a layered dielectric pattern or a sunken groove of the circuit substrate 310. The isolation mechanism 311 is used to form the circuit substrate It is formed together at 31:00. The isolation mechanism 311 @ can be a strip-shaped dam, an annular dam, or a plurality of circular-shaped strip-shaped dams. The isolation mechanism 3 n is protruding above the circuit board 3 0. Surface 31 2. In this embodiment, the isolation mechanism 3 j is a ring-shaped dam. As shown in FIG. 4, preferably, the isolation mechanism 3 is a closed ring to achieve a better anti-spilling effect. The circuit substrate 3 1 0 further includes a plurality of first pads 3 丨 6, a plurality of second pads 31 7 and a plurality of connection pads 318. The first pads 316 are formed in the stacking area 31 5. It can also be a double-row arrangement for stacking and connecting the external terminals of the electronic element (not shown). The second pads 317 are formed on the lower surface 3 丨 3 of the circuit substrate 3 丨 0, and the second pads 317 are electrically connected to the first pads 316. As shown in FIG. 3, the connection pads 318 are formed in the molding area 314 for the chip 32 to be electrically connected. Please refer to FIGS. 3 and 4 at the same time. Preferably, the isolation mechanism 311 is adjacent to the molding area 314, and the gap 31 la (spacing) between the isolation mechanism 311 and the molding area 314 is not more than 10 mm. To avoid taking up the stack

mm Page 11 1240394 V. Description of the invention (7) 315 The area formed by the first pads 316 and the circuit structure, and the mesophilic gap 3Ua can be pressed by a mold (not shown) to avoid the mold = The line structure. Please refer to FIG. 3 again, the wafer 32 is disposed on the upper surface 312 of the circuit substrate 31 (), the wafer 320 has an active surface 321, an inactive surface 322, and includes a plurality of pads 323, The bonding pads 323 are formed on the active surface 321, and an adhesive 324 is used to adhere the non-active surface 322 of the wafer 32 to the mold area 3 14 of the circuit substrate 3 10, so that the wafer 32 〇 is located in the molding area 314, and a plurality of bonding wires 340 are connected to the pads 3 2 3 of the wafer 32 and the connection pads 318 of the circuit substrate 3 10 to electrically connect the wafer 320 And this circuit board 31. The molding compound 330 seals the wafer 32 and the bonding wires 34. Please refer to FIG. 4 again, the molding compound 330 has a gate on one side). In this embodiment, the side-washing port " I is directed toward one of the corners 319 of the circuit board 3.10. Preferably, the stacking area 315 of the circuit substrate 31 is at the side wash port 331 and the corresponding corner pads 319 and the first pads 316 to avoid contamination during the injection. If there is no further installation, please refer to FIG. 3 again. The plurality of first solder balls 3 51 can be disposed on the circuit substrates 31 0 of the first pads 3 1 6 to electrically connect the stacked electronic components. The electronic component can be a Ball Grid Array (BGA) package structure, an interposer substrate, or a cavity-down ball grid array package structure that is commonly used in stereo packaging to connect the circuit substrate 3 1 () and the circuit substrate. Electronic component. In this embodiment, a plurality of second solder balls 352 may be disposed on the second pads 317 for external electrical connection. This semiconductor package structure 3〇〇

Page 1212394394 I. Description of the invention (8) ---------- System I is a micro-pitch ball grid array package structure (⑽pitch Ball Γ1 ΑΓΙΎ, VFBGA), which has a short wire bond pitch (F ine pi = h) and a smaller solder ball volume, and the distance between solder balls (bau "than h) can be as small as 0.5 to 0.8 mm, which can meet the needs of high integration and low cost, and Ensure the stability of the product. ^ In the above-mentioned semiconductor packaging structure 300 suitable for three-dimensional packaging, the electric circuit / circuit board 3 1 0 is integrally formed with the isolation mechanism 3, and the isolation mechanism 311 is located in the molding area. Between 314 and the stacking area 315, a closed loop is formed to prevent the molding gel 33 or the adhesive 324 from overflowing during the die attaching process (D / A prcess), The first pads 316 that contaminate the stacking area 315 facilitate the bonding of stacked electronic components. The isolation mechanism of the present invention can be of different types. According to the second embodiment of the present invention, please refer to FIG. 5 A semiconductor package structure 4 00 suitable for three-dimensional packaging mainly includes a circuit substrate 41. The circuit substrate 41 0 includes an integrated barrier mechanism 41 1 (barrier mechanism). The semiconductor package structure 400 series further includes a wafer 42 () and a molding compound 430. The circuit substrate 410 has a top The surface 412 and the lower surface 413. The center of the upper surface 412 defines a molding area, and the periphery of the upper surface 412 defines a stacking area 415 surrounding the molding area 414. The isolation mechanism 411 is integrally formed in the circuit. The upper surface 412 of the substrate 41 is located between the molding area 414 and the stacking area 415, so as to isolate the molding area 414 and the stacking area 415 to prevent the sealing process.

1240394 5. The encapsulating process (9) (encapsulating process) overflows the molding compound 430 to the stacking area 415. The isolation mechanism 411 may be a single groove, an annular groove, or a plurality of annular grooves. The isolation mechanism 411 is recessed on the upper surface 412 of the circuit substrate 410. . In this embodiment, the isolation mechanism 4 11 is an annular groove and has a closed ring. In this embodiment, a gap 411a (spacing) between the isolation mechanism 41} and one of the molding areas 414 may not exceed 1.0 mm. In addition, the circuit board 4 10 includes a plurality of first contacts 416, a plurality of second contacts 417, and a plurality of connection pads 418. The first pads 416 are formed in the stacking area 415. The second pads 417 are formed on the lower surface 413 of the circuit substrate 4 10. The connection pads 418 are formed in the molding area 4 14 of the circuit substrate 4 10. The helium sheet 4 2 0 is adhered to the upper surface 412 of the circuit substrate 4 1 0 with a sticky crystal layer 4 2 1 and is electrically connected to the connection pads 418 of the circuit substrate 410. The molding compound 430 is formed in the molding area 414 of the circuit substrate 41 to seal the wafer 420. The plurality of first solder balls 441 can be disposed on the first pads 416 of the circuit substrate 41 to stack another electronic component (not shown). In this embodiment, a plurality of second solder balls 442 can be disposed on the second pads 4 1 7 for external electrical connection. In the aforementioned semiconductor package structure 400 suitable for three-dimensional packaging, the circuit substrate 410 is integrally formed with the isolation mechanism 411, and the isolation mechanism 411 is located between the molding area 414 and the stacking area 415 to prevent The molding compound 4 30 overflows with glue, and contaminates the first pads in the stacking area 415

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Page 14 l24〇394 -------- ㈣, using the dimensional stacking of ㈣ elements. The scope of protection of the present invention shall be subject to the scope of the appended patent application. Any person skilled in the art, without departing from the "π 斫 work of this invention, shall make any changes and modifications within the scope of yy ηβ The ascended J pigeon is sacrificed in the protection scope of the present invention

Page 15 1240394 Brief description of the drawings [Simplified description of the drawings] Figure 1: A schematic sectional view of a conventional three-dimensional package structure; Figure 2: A schematic sectional view of a conventional three-dimensional package structure; Figure 3: According to the first of the present invention A specific embodiment is a schematic cross-sectional view of a semiconductor package structure suitable for three-dimensional packaging; Figure 4: According to a first specific embodiment of the present invention, a top view of the semiconductor package structure suitable for three-dimensional packaging; and Figure 5: A second specific embodiment of the present invention is a schematic cross-sectional view of a semiconductor package structure suitable for a three-dimensional package. Simple explanation of component symbols: 100-dimensional three-dimensional package structure 110 semiconductor carrier package structure 111 first semiconductor wafer 112 base substrate 112a upper surface 112b lower surface 113 bonding wire 114 first colloid 115 first group connector 116 second group connector 117 Third group of pads 118 First solder ball 119 Second solder ball 120 Intermediate substrate 121 First external pad 122 Second external pad 130 Semiconductor package structure 131 Second semiconductor wafer 132 Connection substrate 132a Upper surface 132b Lower surface 133 Bonding wire 134 connection pad 135 second sealant 136 solder ball

Package structure 211 211b Lower surface 212 214 Wafer 215 217 Solder ball structure 221 221b Lower surface 223 Welding wire 225 Semiconductor package structure for encapsulation 311 Isolation mechanism 311a 313 Lower surface 314 316 First connection 317 319 Corner 321 Active surface 322 324 Adhesive glue 331 Side wash mouth 352 Semiconductor package structure with second solder ball 411 Isolation mechanism 411a 413 Lower surface 414 416 First pad 417 Circuit board First pad Fresh line Circuit board gap Mould sealing area Second connection Pad Non-active surface gap Moulded area second pad 224 230 300 310 312 315 318 320 323 330 340 351 400 410 412 415 1240394 Brief description of the diagram 200 Three-dimensional package structure 210 Semiconductor support 21 la Upper surface 213 Second connection 216 Molded colloid 220 Semiconductor seal 2 21 a Upper surface 222 Wafer molded gel spacer ball is suitable for the upper surface stacking area of the vertical circuit substrate. Connection pad wafer welding Molded gel glue wire The first solder ball is suitable for the upper surface stacked area of the vertical circuit substrate. 1240394 Schematic description of 418 connection 塾 420 chip 421 die attach 430 die Sealant 441 First solder ball 442 Second solder ball

ism p. 18

Claims (1)

1240394 VI. Scope of patent application [Scope of patent application] 1. Two types of semiconductor package structures suitable for three-dimensional packaging, including: 矣 & sun substrate, which has an upper surface and a lower surface, and there is a mold package on it. And a stacking area, the circuit substrate includes a first pad, a plurality of second pads, and an isolation mechanism. The first pads are formed in the stacking area and the second pads. Is formed on the lower surface; the second sheet is disposed on the upper surface of the circuit substrate; and a molding compound is formed on the molding area of the circuit substrate to seal the wafer; wherein, The isolation mechanism is integrally formed on the upper surface of the circuit substrate and located between the molding area and the stacking area to prevent the molding gel from overflowing to the stacking area. 2. The semiconductor package structure suitable for three-dimensional packaging as described in item 1 of the scope of the patent application, wherein the isolation mechanism is selected from one of a ring-shaped dam or a strip-shaped dam, and the isolation mechanism is prominent On the upper surface of the circuit substrate. 3. The semiconductor package structure suitable for three-dimensional packaging as described in the first scope of the patent application, wherein the isolation mechanism is selected from one of a ring groove or a strip groove, and the isolation mechanism is a depression On the upper surface of the circuit substrate. 4. The semiconductor packaging structure suitable for three-dimensional packaging as described in item 1 of the scope of patent application, wherein the isolation mechanism is a closed ring. 5. The semiconductor packaging structure suitable for three-dimensional packaging as described in item 1 of the scope of the patent application, wherein the molding area of the circuit substrate is located on the upper surface. Page 19 1240394 In the center, the stacking area is located on the periphery of the upper surface. Guide ib j, such as the scope of patent application! The half of the package applicable to the three-dimensional package described in the item _ package edge, wherein the stacking area surrounds the molding area. J. For example, please refer to the patent for the three-dimensional package of the three-dimensional package of the "1" structure. Some of the second pads are electrically connected to the first rail. As described in item 丨 of the scope of the patent application, it is applicable to the three-dimensional 2 structure: it further includes a plurality of first fresh balls, and it is provided with: some first connections. 9. The half applicable to the three-dimensional package as described in item 丨 of the scope of the patent application. It also includes a plurality of second solder balls, which are provided with second contacts. The semiconductor in the three-dimensional package is electrically connected to the crystal 10, the applicable body package structure described in item 1 of the scope of the patent application, and further includes a plurality of bonding wires, a sheet and the circuit substrate. 11. The semiconductor packaging structure suitable for three-dimensional packaging as described in item 1 of the scope of the patent application, wherein the molding compound system has a side gate, which faces one of the corners of the circuit substrate. 12. The half-body package structure suitable for three-dimensional packaging as described in item n of the scope of the patent application, wherein the stacking area of the circuit substrate is not provided with the first and second gates between the side gate and the corresponding corner. One after another. 13 、 Semiconductor packaging structure suitable for three-dimensional packaging as described in item 1 of the scope of the patent application, wherein the gap between the isolation mechanism and the molding area is not more than 1.0 mm. 1240394 VI. Application for patent scope 14. As described in item i of the scope of application for a semiconductor package structure suitable for three-dimensional packaging, the semiconductor package I structure may be a micro-pitch ball grid array package structure (Very Fine pitch BaU Grid & VFBGA). 15. The semiconducting structure suitable for three-dimensional packaging as described in item 丨 of the scope of the patent application, further comprising-a crystal adhesive, which is used to adhere the chip to the molding area of the circuit substrate. 16. A circuit substrate suitable for three-dimensional packaging, which has an upper surface: 1 lower surface, the upper surface defines a molding area and a stacking area, the circuit substrate system comprises: a plurality of- It is formed on the upper surface of the stacking area; a plurality of second pads are formed on the lower surface and the structure, which are integrally formed on the upper surface and located between the molding & and the stacking area between. 1: The scope of the patent described on page 16 applies to the three-dimensional package of electricity, where the isolation mechanism is selected from one of a ring-shaped field or a strip-shaped channel --- and the isolation mechanism is protruding from the On the surface. The electric field suitable for three-dimensional packaging according to item 16 of the scope of application for patent: In i, the isolation mechanism is selected from one of a ring groove or a strip groove, and the isolation mechanism is recessed on the upper surface . Lumei = Shen = Electricity applicable to three-dimensional packaging as described in Item 16 of Patent Qianwei, where the isolation mechanism is a closed ring. The electric circuit suitable for three-dimensional packaging described in item 16 of the road substrate, wherein the molding area is located in the center of the upper surface, the stacking area is on page 21 1240394 6. The scope of patent application is located on the Table 21. If applying for a dedicated circuit board, of which 22, if applying for a dedicated circuit board, which includes pads. 23. If applying for a circuit board, one of the corners 隅 2. If applying for a circuit board, the perimeter of the 1.0mm surface. The electric field applicable to the three-dimensional package described in item 16 of the fJ range. The stacking area surrounds the mold area. The second pads suitable for the three-dimensional package described in Item 16 are electrically connected to the electrical circuit substrates for the three-dimensional package described in the first item 16 There are a plurality of corner pads, and the first pads are not provided in the stacking area. The clearance between the isolation mechanism and the molding area described in item 16 of the scope of interest is not more than 25. A three-dimensional package structure, including a semiconductor carrier package structure, including a circuit substrate, The system has an upper surface and a lower surface. The upper surface defines a molding area and a stacking area. The circuit substrate includes a plurality of first pads, a plurality of second pads, and a barrier mechanism. ), The first pads are formed in the stacking area of the upper surface, the second pads are formed in the lower surface, and the isolation mechanism is integrally formed on the upper surface and is located in the molding area and the stack Between the regions; a wafer that is disposed on the upper surface of the circuit substrate; and a molding compound that is formed in the molding region of the circuit substrate to seal the wafer; and an electronic component that is stacked In the semiconductor carrier package structure, the Page 22 1240394 VI. Scope of patent application Electronic components have a plurality of external terminals which are electrically connected to the first connectors of the circuit substrate. 2 6 < The three-dimensional package structure according to item 25 of the scope of patent application, wherein the isolation mechanism of the circuit substrate is selected from one of a ring-shaped barrier or a strip-shaped barrier, and the isolation The mechanism protrudes from the upper surface of the circuit substrate. 27. The three-dimensional package structure according to item 25 of the scope of patent application, wherein the isolation mechanism of the circuit substrate is selected from one of a ring groove or a strip groove, and the isolation mechanism is Recessed on the upper surface of the circuit substrate. 28. The three-dimensional package structure described in item 25 of the scope of application for a patent, wherein the isolation mechanism of the circuit substrate is in a closed loop shape. 29. The three-dimensional package structure according to item 25 of the scope of the patent application, wherein the molding area of the circuit substrate is located at the center of the upper surface, and the stacking area is located at the periphery of the upper surface. 30. The three-dimensional package structure described in item 25 of the scope of patent application, wherein the stacked area of the circuit substrate surrounds the molding area. 31. The three-dimensional package structure described in item 25 of the scope of application for a patent, wherein the second pads of the circuit substrate are electrically connected to the first pads. 32. The three-dimensional package structure as described in item 25 of the scope of the patent application, wherein the semiconductor carrier package structure includes a plurality of first solder balls, which are disposed on the first pads to connect the electronic components. Some external terminals. 33. The three-dimensional package structure described in item 25 of the scope of patent application, wherein Page 23 1240394 6. Scope of patent application ----- The body-loaded package structure includes a plurality of second solder balls, which are arranged on the second pads. 34. The three-dimensional package structure described in item 25 of the declared patent scope, wherein the 4 semiconductor carrier package structure includes a plurality of bonding wires, which are electrically connected to the chip and the circuit substrate. 35. The three-dimensional package structure according to Item 25 of the declared patent scope, wherein the molding compound of the semiconductor carrier package structure has a side gate (side gat /), which faces one corner of the circuit substrate. 3 6. For example, the three-dimensional package structure described in claim 35 of the patent scope, wherein the stacked areas of the circuit substrate are not provided with the first contacts between the side gate and the corresponding corner. 37. The three-dimensional package structure as described in item 25 of the patent application scope, wherein the gap between the isolation mechanism of the circuit substrate and the molding area is not more than 1.0 mm. The three-dimensional package structure described in item 25, wherein the semiconductor carrier package structure may be a Very Fine Pitch Ball Grid Array (VFBGA) package structure. 3 > 9. The three-dimensional package structure according to item 25 of the scope of application for a patent, wherein the electronic component is selected from one of a ball grid array package structure, an interposer, and a cavity-down type ball grid array package structure. 4 > 0. The three-dimensional package structure according to item 25 of the scope of application for a patent, wherein the semiconductor carrier package structure includes a die-bonding adhesive, which is bonded to the wafer in the molding area of the circuit substrate. Page 24