CN110970414A - Multi-chip packaging structure and manufacturing method - Google Patents
Multi-chip packaging structure and manufacturing method Download PDFInfo
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- CN110970414A CN110970414A CN201911244763.XA CN201911244763A CN110970414A CN 110970414 A CN110970414 A CN 110970414A CN 201911244763 A CN201911244763 A CN 201911244763A CN 110970414 A CN110970414 A CN 110970414A
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- logic unit
- chip
- bottom substrate
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- carrier layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4502—Disposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a multi-chip packaging structure and a manufacturing method thereof, and the multi-chip packaging structure comprises a bottom substrate, storage chips and a plastic package body, wherein a carrier layer is bonded at the middle position of the top surface of the bottom substrate, a control chip is embedded in the carrier layer, a plurality of storage chips are stacked on the top surface of the carrier layer, and a first logic unit and a second logic unit are respectively arranged on the two sides of the carrier layer, which are positioned on the top surface of the bottom substrate, through solder balls; according to the invention, the first logic unit and the second logic unit are additionally arranged on the bottom substrate, the memory chip is electrically connected with the bottom substrate, the first logic unit and the second logic unit are electrically connected with the bottom substrate through the solder balls, and part of the stacked memory chips are electrically connected with the first logic unit and the second logic unit through WB (wire bond) routing, so that routing connection of a plurality of stacked memory chips is realized.
Description
Technical Field
The invention relates to the technical field of storage chip packaging, in particular to a multi-chip packaging structure and a manufacturing method thereof.
Background
In the fabrication of integrated circuits, the chips are fabricated by wafer fabrication, forming integrated circuits, and dicing the wafer. The wafer has an active surface, which broadly refers to the surface of the wafer having active devices. After the integrated circuits inside the wafer are completed, the active surface of the wafer is further configured with a plurality of pads, so that the chips finally formed by wafer dicing can be electrically connected to a carrier through the pads. The carrier is, for example, a lead frame or a package substrate. The chip can be connected to the carrier by wire bonding or flip chip bonding, so that the pads of the chip can be electrically connected to the pads of the carrier to form a chip package structure.
The trend of semiconductor chip packaging, especially memory chip packaging, is that the packaging thickness is thin, the volume is small, the integration level is high, the reliability and the high integration level of multi-chip stacking become a great trend of packaging, and meanwhile, the wiring and routing space is limited, which is a challenge for technical personnel in the industry.
Therefore, a multi-chip package structure is provided to solve the above drawbacks.
Disclosure of Invention
The invention aims to solve the defects in the prior art and provides a multi-chip packaging structure and a manufacturing method thereof.
In order to achieve the purpose, the invention adopts the following technical scheme:
the utility model provides a multi-chip packaging structure, includes bottom base plate, memory chip and plastic-sealed body, the intermediate position of bottom base plate top surface bonds and has the carrier layer, and the embedded control chip that is equipped with of carrier layer to the top surface of carrier layer is piled up and is had a plurality of memory chip, first logical unit and second logical unit are installed through the tin ball respectively to the both sides of carrier layer are located the top surface of bottom base plate, first logical unit and second logical unit are respectively through a plurality of WB routing and a plurality of memory chip electric connection who piles up, bottom base plate, first logical unit and the inside metal level that all is provided with of second logical unit, the top surface of bottom base plate is packaged with the plastic-sealed body.
As a further description of the above technical solution: the bottom surface of the bottom substrate is equidistantly provided with a plurality of solder balls, and the solder balls are electrically connected with the corresponding first logic unit and the second logic unit respectively through the metal layer of the bottom substrate.
As a further description of the above technical solution: and the control chip embedded in the carrier layer is electrically connected with the corresponding metal layer on the bottom substrate through WB routing.
As a further description of the above technical solution: the storage chips stacked on the top surface of the carrier layer are distributed in a step shape.
As a further description of the above technical solution: the carrier layer is made of FOD (film on die) material.
As a further description of the above technical solution: the metal layers in the first logic unit and the second logic unit are electrically connected with the stacked memory chips through WB routing, and the top surfaces of the first logic unit and the second logic unit are provided with logic unit upper circuits corresponding to the WB routing.
The invention also discloses a manufacturing method of the multi-chip packaging structure, which is used for the multi-chip packaging structure and comprises the following steps:
providing a bottom substrate, a logic unit, a control chip and a storage chip;
sticking a control chip and a storage chip with a carrier layer on the top surface of the bottom substrate, and electrically connecting the bottom substrate with the control chip, the bottom substrate and the storage chip;
sticking a logic unit on the top surface of the bottom substrate;
the bottom substrate and the logic unit are electrically connected, and the storage chip and the logic unit are electrically connected;
the process plastic-packaged bottom substrate, the logic unit, the control chip and the storage chip.
As a further description of the above technical solution: the step of electrically connecting the bottom substrate with the control chip, the bottom substrate and the memory chip comprises the following steps:
electrically connecting the bottom substrate with the control chip, the bottom substrate and the memory chip by using a wire bond process;
the step of electrically connecting the memory chip and the logic unit includes:
and electrically connecting the memory chip and the logic unit by using a wire bond process.
As a further description of the above technical solution: the logic unit comprises a first logic unit and a second logic unit, and the step of providing the bottom substrate, the logic unit, the control chip and the memory chip comprises the following steps:
forming a via hole on the underlying substrate;
forming a plurality of solder balls with equal intervals on the bottom surface of the bottom substrate;
the step of pasting the logic unit on the top surface of the bottom substrate comprises the following steps:
the solder ball is electrically connected with the first logic unit, the solder ball is electrically connected with the second logic unit.
The invention has the following beneficial effects:
according to the invention, the first logic unit and the second logic unit are additionally arranged on the bottom substrate, the memory chip is electrically connected with the bottom substrate, the first logic unit and the second logic unit are electrically connected with the bottom substrate through the solder balls, and part of the stacked memory chips are electrically connected with the first logic unit and the second logic unit through WB (wire bond) routing, so that routing connection of a plurality of stacked memory chips is realized.
Drawings
FIG. 1 is a schematic structural view of a multi-chip package structure of the present invention, in which a control chip and a memory chip with FOD material are attached to a bottom substrate, and the electrical connection between the control chip and the bottom substrate is completed by a wire bond process;
FIG. 2 is a schematic diagram of the structure of FIG. 1 after logic cells are attached to an underlying substrate;
FIG. 3 is a schematic structural diagram of the structure shown in FIG. 2, in which a logic unit is attached to the bottom substrate and electrically connected to the bottom substrate, and the memory chip is electrically connected to the logic unit by a wire bond process;
FIG. 4 is a schematic structural view of the structure shown in FIG. 3 after process molding;
FIG. 5 is a flow chart of a method of fabricating a multi-chip package structure according to the present invention;
FIG. 6 is another flow chart of a method for manufacturing a multi-chip package structure according to the present invention.
Illustration of the drawings:
1. a base substrate; 2. tin balls; 3. a carrier layer; 4. a control chip; 5. WB routing; 6. a memory chip; 7. a logic cell upper line; 8. a first logic unit; 9. a metal layer; 10. molding the body; 11. a second logic unit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance, and furthermore, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
According to an embodiment of the present invention, a multi-chip package structure is provided.
Referring to the drawings and the detailed description, as shown in fig. 1-4, a multi-chip package structure according to an embodiment of the present invention includes a bottom substrate 1, memory chips 6 and a plastic package body 10, a carrier layer 3 is bonded to a middle position of a top surface of the bottom substrate 1, a control chip 4 is embedded in the carrier layer 3, a plurality of memory chips 6 are stacked on the top surface of the carrier layer 3, a first logic unit 8 and a second logic unit 11 are respectively mounted on two sides of the carrier layer 3 on the top surface of the bottom substrate 1 through solder balls 2, the first logic unit 8 and the second logic unit 11 are respectively electrically connected to the plurality of stacked memory chips 6 through a plurality of WB wire bonds 5, a metal layer 9 is disposed inside the bottom substrate 1, the first logic unit 8 and the second logic unit 11, and the plastic package body 10 is packaged on the top surface of the bottom substrate 1, the first logic unit 8 and the second logic unit 11 are added on the bottom substrate 1, the memory chip 6 is electrically connected with the bottom substrate 1, the first logic unit 8 is electrically connected with the second logic unit 11 through the solder ball 2 and the bottom substrate 1, part of the stacked memory chips 6 are electrically connected with the first logic unit 8 and the second logic unit 11 through a WB (wire bond) routing 5, the routing connection of the plurality of stacked memory chips 6 is realized, and the problems of wiring space and routing space can be solved under the condition of not being limited by the number of substrate units and the number of substrate routing layers;
in one embodiment, the bottom surface of the bottom substrate 1 is provided with a plurality of solder balls 2 at equal intervals, and the solder balls 2 are electrically connected to the first logic unit 8 and the second logic unit 11 through the metal layer 9 of the bottom substrate 1, respectively, the solder balls 2 can be used as base points for connecting the bottom substrate 1 and the first logic unit 8 with the second logic unit 11, and the first logic unit 8 and the second logic unit 11 are electrically connected transition pieces.
In one embodiment, the control chip 4 embedded in the carrier layer 3 is electrically connected to the metal layer 9 of the bottom substrate 1 through the WB wire bonding 5, so that the control chip 4 is directly electrically connected to the bottom substrate 1.
In one embodiment, the memory chips 6 stacked on the top surface of the carrier layer 3 are distributed in a step shape, and the plurality of memory chips 6 arranged by the memory chips 6 are convenient for carrying the WB wire bonding 5.
In one embodiment, the carrier layer 3 is formed of FOD (film on die) material.
In one embodiment, the metal layer 9 is disposed inside the first logic unit 8 and the second logic unit 11, the metal layer 9 is electrically connected to the stacked memory chips 6 through the WB wire bonding 5, the top surfaces of the first logic unit 8 and the second logic unit 11 are provided with the logic unit upper circuit 7 corresponding to the WB wire bonding 5, and the logic unit upper circuit 7 facilitates the connection of the WB wire bonding 5.
The working principle is as follows:
the first logic unit 8 and the second logic unit 11 are added on the bottom substrate 1, the memory chip 6 is electrically connected with the bottom substrate 1, the first logic unit 8 and the second logic unit 11 are electrically connected with the bottom substrate 1 through the solder balls 2, part of the stacked memory chips 6 are electrically connected with the first logic unit 8 and the second logic unit 11 through WB (wire bond) routing 5, the routing connection of the plurality of stacked memory chips 6 is realized, and the problems of wiring space and routing space can be solved under the condition that the limitation of the number of substrate units and the number of substrate routing layers is avoided.
As another embodiment of the present invention, a method for manufacturing a multi-chip package structure is also disclosed, which is applied to the multi-chip package structure, and includes the steps of:
s100: providing a bottom substrate, a logic unit, a control chip and a storage chip;
s200: sticking a control chip and a storage chip with a carrier layer on the top surface of the bottom substrate, and electrically connecting the bottom substrate with the control chip, the bottom substrate and the storage chip;
s300: sticking a logic unit on the top surface of the bottom substrate;
s400: the bottom substrate and the logic unit are electrically connected, and the storage chip and the logic unit are electrically connected;
s500: the process plastic-packaged bottom substrate, the logic unit, the control chip and the storage chip.
Specifically, the step of electrically connecting the bottom substrate and the control chip, the bottom substrate and the memory chip includes:
electrically connecting the bottom substrate with the control chip, the bottom substrate and the memory chip by using a wire bond process;
the step of electrically connecting the memory chip and the logic unit includes:
and electrically connecting the memory chip and the logic unit by using a wire bond process.
As a further description of the above technical solution: the logic unit comprises a first logic unit and a second logic unit, and the step of providing the bottom substrate, the logic unit, the control chip and the memory chip comprises the following steps:
s600: forming a via hole on the underlying substrate;
s700: forming a plurality of solder balls with equal intervals on the bottom surface of the bottom substrate;
the step of pasting the logic unit on the top surface of the bottom substrate comprises the following steps:
s800: the solder ball is electrically connected with the first logic unit, the solder ball is electrically connected with the second logic unit.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments or portions thereof without departing from the spirit and scope of the invention.
Claims (9)
1. The utility model provides a multi-chip package structure, includes bottom base plate (1), memory chip (6) and plastic-sealed body (10), its characterized in that: the middle position of bottom base plate (1) top surface bonds and has carrier layer (3), and carrier layer (3) embedded control chip (4) that is equipped with to the top surface of carrier layer (3) is piled up and is had a plurality of memory chip (6), the top surface that the both sides of carrier layer (3) are located bottom base plate (1) installs first logic unit (8) and second logic unit (11) through tin ball (2) respectively, first logic unit (8) and second logic unit (11) are respectively through stranded WB routing (5) and a plurality of memory chip (6) electric connection who piles up, bottom base plate (1), first logic unit (8) and second logic unit (11) inside all is provided with metal level (9), the top surface encapsulation of bottom base plate (1) has plastic envelope body (10).
2. The multi-chip package structure of claim 1, wherein: the bottom surface of the bottom substrate (1) is equidistantly provided with a plurality of solder balls (2), and the solder balls (2) are respectively electrically connected with the corresponding first logic unit (8) and the second logic unit (11) through the metal layer (9) of the bottom substrate (1).
3. The multi-chip package structure of claim 1, wherein: the control chip (4) embedded in the carrier layer (3) is electrically connected with the corresponding metal layer (9) on the bottom substrate (1) through a WB routing (5).
4. The multi-chip package structure of claim 1, wherein: the storage chips (6) stacked on the top surface of the carrier layer (3) are distributed in a step shape.
5. The multi-chip package structure of claim 1, wherein: the carrier layer (3) is made of FOD material.
6. The multi-chip package structure of claim 1, wherein: the metal layers (9) in the first logic unit (8) and the second logic unit (11) are electrically connected with the stacked memory chips (6) through WB routing (5), and the top surfaces of the first logic unit (8) and the second logic unit (11) are provided with logic unit upper circuits (7) corresponding to the WB routing (5).
7. A method of manufacturing a multi-chip package structure according to any of claims 1 to 6, comprising the steps of:
providing a bottom substrate, a logic unit, a control chip and a storage chip;
sticking a control chip and a storage chip with a carrier layer on the top surface of the bottom substrate, and electrically connecting the bottom substrate with the control chip, the bottom substrate and the storage chip;
sticking a logic unit on the top surface of the bottom substrate;
the bottom substrate and the logic unit are electrically connected, and the storage chip and the logic unit are electrically connected;
the process plastic-packaged bottom substrate, the logic unit, the control chip and the storage chip.
8. The method of manufacturing of claim 7, wherein the step of electrically connecting the base substrate and the control chip, the base substrate and the memory chip comprises:
electrically connecting the bottom substrate with the control chip, the bottom substrate and the memory chip by using a wire bond process;
the step of electrically connecting the memory chip and the logic unit includes:
and electrically connecting the memory chip and the logic unit by using a wire bond process.
9. The method of manufacturing of claim 7, wherein the logic cells include a first logic cell and a second logic cell, the step of providing the base substrate, the logic cells, the control chip, and the memory chip comprising the steps of, after:
forming a via hole on the underlying substrate;
forming a plurality of solder balls with equal intervals on the bottom surface of the bottom substrate;
the step of pasting the logic unit on the top surface of the bottom substrate comprises the following steps:
the solder ball is electrically connected with the first logic unit, the solder ball is electrically connected with the second logic unit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911244763.XA CN110970414A (en) | 2019-12-06 | 2019-12-06 | Multi-chip packaging structure and manufacturing method |
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| CN201911244763.XA CN110970414A (en) | 2019-12-06 | 2019-12-06 | Multi-chip packaging structure and manufacturing method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111816641A (en) * | 2020-08-27 | 2020-10-23 | 华天科技（西安）有限公司 | Electromagnetic shielding packaging structure and method based on secondary plastic packaging |
| CN113823604A (en) * | 2021-08-06 | 2021-12-21 | 紫光宏茂微电子(上海)有限公司 | Chip stack package and manufacturing method thereof |
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| CN101542628A (en) * | 2006-10-05 | 2009-09-23 | 诺基亚公司 | 3D chip arrangement including memory manager |
| CN104576546A (en) * | 2013-10-22 | 2015-04-29 | 三星电子株式会社 | Semiconductor package and method of fabricating the same |
| CN107004663A (en) * | 2014-11-21 | 2017-08-01 | 美光科技公司 | The system and method for storage arrangement and correlation with the controller under memory package |
| US9899347B1 (en) * | 2017-03-09 | 2018-02-20 | Sandisk Technologies Llc | Wire bonded wide I/O semiconductor device |
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2019
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101542628A (en) * | 2006-10-05 | 2009-09-23 | 诺基亚公司 | 3D chip arrangement including memory manager |
| CN104576546A (en) * | 2013-10-22 | 2015-04-29 | 三星电子株式会社 | Semiconductor package and method of fabricating the same |
| CN107004663A (en) * | 2014-11-21 | 2017-08-01 | 美光科技公司 | The system and method for storage arrangement and correlation with the controller under memory package |
| US9899347B1 (en) * | 2017-03-09 | 2018-02-20 | Sandisk Technologies Llc | Wire bonded wide I/O semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111816641A (en) * | 2020-08-27 | 2020-10-23 | 华天科技（西安）有限公司 | Electromagnetic shielding packaging structure and method based on secondary plastic packaging |
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