TWI246754B - Semiconductor package having stacked chip and a method for fabricating - Google Patents

Abstract

A semiconductor package having stacked chip and a method for fabricating the same are proposed. A semiconductor package includes a chip carrier having a carrier surface. At least one first chip is mounted on the carrier surface of the chip carrier. A spacer formed with a recess is used receive a second chip. Wires are bonded to be electrically connected the chip carrier, spacer, first chip and second chip. A resin body is formed to encapsulate the chip carrier, spacer, first chip, second chip and wires. By means of the recess of the spacer, the semiconductor package can be reduced in thickness and volume, and delaminate of the chips and uneven speed of the resin flow can be prevented.

Description

1246754 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Field of the Invention A semiconductor package of a stacked wafer and a method of fabricating the same, and more particularly to a semiconductor package of a stacked wafer which can reduce the overall height of a semiconductor package and a method of fabricating the same. [Prior Art] With the booming development of the electronics industry, electronic products are gradually entering the direction of multi-functional and south-performance research to meet the high integration and miniaturization of semiconductor packages (μ iniaturizati ο η). In order to improve the performance and capacity of a single semiconductor package, and to reduce the miniaturization, large capacity, and high speed of electronic products, it is customary to multi-chip semiconductor packages into multiple chips (Multi Chip Module). MCM) in the form of 'this package can also reduce the size of the overall package and enhance the electrical function, and become the mainstream of a package, which is connected to at least two semiconductors on the die carrier of a single package. The wafer (semiconduct〇rchip) 'and the mother wafer and the chip carrier (c乜ipcarrier) are connected in a vertical stack. The stacked chip package structure has been found in U.S. Patent No. 5,7 7 7 , 3 4 5 and 5, 7 9 3, 1 0 8 , 5, 5 0 2, 2 8 9 , 6, 0 0 5, 7 7 8 and other conventional techniques. Figure 6A is a cross-sectional view of the package disclosed in U.S. Patent No. 5,7,7,3, 4,5, which is incorporated below the wafer holder 2 〇1 of a lead frame (1 eadframe) 20 A first chip 22 is adhered to the lower surface of the first wafer 2 1 , and a plurality of bonding pads 21 1 are respectively disposed under the first wafer 2 1 and the second wafer 2 2 . And the pad 221, the long pad 2 1 1 of the first wafer 2 1 is connected to the lead frame by a bonding wire ( 2 )

17567石夕品.ptd Page 7 12467754 V. Invention Description (2) 20 0 lead pin 2 0 2, and the first wafer 2 1 long pad 2 1 1 and the second wafer 2 2 pad 2 The 2 1 series is also connected by a bonding wire 23, so that the lead frame 20, the first wafer 2 1 and the second wafer 2 2 are electrically connected, and externally by the lead pin 20 of the lead frame 20 The device is electrically connected, and finally the entire package is coated with the encapsulant 24 to complete the encapsulation process. However, for such a package, in order to enable the second wafer 2 2 stacked on the upper layer to be electrically connected to the lead 2 0 2 of the lead frame 20, the first wafer 21 must be disposed to provide The long pad 2 1 1 of the jumper is such that the second wafer 2 2 can be jumped to the lead frame 20 by the bonding wire 2 3 by the long pad 2 1 1 on the first wafer 2 1 , such as As shown in FIG. 6B, the addition of a long pad 2 1 1 for jumpering on the first wafer 2 1 will increase the area thereof, resulting in difficulty in reducing the overall size, and the special design of the long pad 2 1 1 is not The design of conventional wafers will increase the cost of wafer processing and become a serious bottleneck in the development of multi-chip packages. Therefore, another multi-chip module, such as the U.S. Patent No. 6,0 0,7,78, which is shown in Fig. 7, is attached to a wafer carrier 50. a spacer 5 2 having a volume smaller than the first wafer 5 1 is attached to the surface 51 of the wafer carrier 50, and the spacer 5 2 is opposite to the spacer 5 2 A surface of the first wafer 51 is connected to a second wafer 53 having a volume equal to that of the first wafer 51. The area of the spacer 52 is smaller than that of the first wafer 51 and the second wafer 5. 3, the first wafer 51 and the second wafer 53 are electrically connected to the wafer carrier 50 through a plurality of bonding wires 54; however, in this structure, a spacer 5 is interposed between the two wafers. 2, and the thermal expansion coefficient of the spacer 52 is different from that of the germanium wafer

17567石夕品.ptd Page 8 12467754 V. Description of invention (3) ' ^ a~~-~ - η number mismatch caused by delamination caused by wafer connection: external t ΐ π:= stack, In addition to increasing the length of the wire, it is not conducive to the electrical = externally, and the height of the sealing member is increased, which is not conducive to the thinning of the package. Therefore, for the above-mentioned stacked wafer semiconductor package, the electrical capacity can be fully solved. The limitation of the layout, but also increases the number and thickness of the crystal, and the tendency to be thinner than the package, = as disclosed in the aforementioned U.S. Patent No. 5,502,28, The substrate is designed to facilitate jumpers, and may also be due to the substrate and the wafer. The difference in the coefficient of expansion (CTE) is too large to cause the contact between the substrate and the wafer, and the surface is delaminated, thereby causing damage to the wafer. Further, for such a stacked wafer semiconductor package, Adding a substrate between the wafers, both of which will increase in thickness, and when the encapsulation process covers the wafer and the wafer carrier by the encapsulant, the package will be excessive due to the excessive number of wafers stacked on each other. The mold flow formed by the colloid encounters too much mold flow resistance in the cavity, which causes uneven distribution, which leads to the occurrence of voids, and the package quality is degraded. Even if the chip package can solve the jumper electrical problem, it is obviously difficult to improve the structure or process problems such as the overall height is too high, the wire arc is too long, the thermal expansion coefficient is not matched, and the mold flow resistance is increased. A major impediment to multi-chip packaging technology; furthermore, these problems can be improved by changing the multi-wafer configuration, such as U.S. Patent No. 5,7 15,147, which is incorporated herein by reference. In a parallel manner to a plurality of multi-chip module of a wafer, based on a carrier (i s Shu and) 6 billion

17567石夕品.ptd

Page 9 12467754 V. Description of the Invention (4) The outer ring is provided with a plurality of internal pins (i η ner 1 ead ) 610, and a first wafer 61 and a second chip are disposed on the carrier 60. 6 2 and the circuit board 6 3, and the circuit board 64 is mounted on the internal pin 601, and is also in the first Q y •. .曰曰nb 1 and the second chip 6 2 above the device circuit board 65, a plurality of electrical connecting means are connected to the first s, the second chip 612 and the circuit boards 63, 64, 65, and the electric The connection structure is 66; this type of structural design can solve the problem that the overall height is too high = the system is laid flat and the first wafer 61 and the second wafer 62 are arranged side by side, but the water-filled area cannot be reached. The purpose of small volume packaging. W adds the overall seal, which means that the design of the existing package changes, as long as the design of the multi-chip is unchanged, it is difficult to develop a kind of stacked-type method. The whole #古_,诘,丨,# piece of cattle conductor package, with a degree of return, reduce the package area, and at the same time, the thermal expansion coefficient does not match and the mold flow is uneven and so on. The urgent need to solve the problem. 1 Temple asks 'I do it - R & D 【Inventive content】 The purpose of the present invention is to provide a height of ±4 fields that can reduce the height of the main track body: 曰y — *, Zeng Yi + conductor package X Semiconductor Package of Stacked Wafer and Its Manufacture It is yet another object of the present invention to provide a jumper function that is required to be used. A further object of the invention is to provide a kind of "Southern part" which can shorten the length of the welding line and the height of the line arc without the thumb 4 #J. Semiconductor package

1246754 V. SUMMARY OF THE INVENTION (5) A further object of the present invention is to provide a semiconductor package of a stacked wafer which avoids delamination due to mismatch in thermal expansion coefficients and a method of fabricating the same. It is still another object of the present invention to provide a semiconductor package of a stacked wafer which reduces the mold cavity flow resistance and reduces the occurrence of voids and a method of fabricating the same. To achieve the above and other objects, the present invention provides a stacked wafer semiconductor package structure comprising: a wafer carrier having a carrier surface; at least a first wafer attached to a carrier surface of the wafer carrier At least one spacer is attached to an opposite surface of the first wafer that is not connected to the wafer carrier, and the spacer has a slot; at least one second chip is received in the spacer a slot in the spacer, and is disposed on an opposite surface of the first wafer that is not connected to the wafer carrier; a plurality of bonding wires are electrically connected to the wafer carrier, the first wafer, and the spacer And a second wafer; and an encapsulant formed on the wafer carrier to cover the first wafer, the spacer, the second wafer, and the bonding wire. The method for manufacturing a stacked wafer semiconductor package of the present invention comprises the steps of: preparing a wafer carrier having an attachment surface; and attaching at least one first wafer to an attachment surface of the wafer carrier; Preparing at least one spacer, the spacer is provided with a slot, and the spacer is disposed on an opposite surface of the first wafer not connected to the wafer carrier; at least one second wafer is prepared, and The second wafer is placed on the opposite surface of the first wafer that is not connected to the wafer carrier, and the second wafer is received in the slot of the spacer; the wafer is electrically connected by a bonding wire. Piece, first wafer, spacer and second wafer; and formed on the wafer carrier

17567 石夕品.ptd Page 11 1246754 V. INSTRUCTION DESCRIPTION (6) A package of colloid to cover the first wafer, the spacer, the second wafer, and the bonding wire. The second chip is accommodated in the slot of the spacer, so that the second chip and the spacer are in the same layer structure, so that the second chip and the spacer are stacked on the top of the chip. A two-layer structure 'pays down the number of layers to reduce the overall package height, which in turn reduces mold flow resistance and reduces the generation of air holes. Furthermore, the second wafer is received in the groove of the spacer, so that the second wafer and the spacer are on the same horizontal plane, so that the electrical connection between the second wafer and the spacer is electrically connected to a plane. The connection is made to avoid the situation that the welding line is too long and the line arc height is too high, so that the length of the welding line and the height of the line arc are shortened, thereby reducing the overall package height and the surface of the crystal. The first and the eliminator are removed, the crystal is inside, the groove is the same as the plate of the phase, and the slab is expanded by the bulging surface. The quality is the same as the material. The quality of the film is the same as that of the two crystals. If the two crystals are the same as the two crystals, the shards of the shards of the shards can be removed. It is too bad and broken, and the number is like a stack of materials. The situation of being close to the living is not the same as that of the other party, and it is not easy to apply it to him. The fact that it is borrowed from the Ming Dynasty can be revealed by the Ming Dynasty. The real effect is made up of the skill and the taxi point. The person who uses it is the skill of the art.

] 7567石夕品.ptd Page 12 12467754 V. The specific embodiments of the invention (7) are implemented or applied, and the details in this specification can also be based on different viewpoints and applications without departing from the spirit of the invention. Various modifications and changes are made below. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention in any way. In the present invention, a first wafer, a second wafer, and a spacer are stacked on a chip carrier, and a groove is formed in the spacer to accommodate the second wafer in the slot. The second wafer and the spacer are located on the same layer in the stacked structure, and are stacked on the first wafer to form a two-layer structure, which will be respectively described in detail by the following embodiments. Referring to FIGS. 1A and 1B, the stacked wafer semiconductor package 1 of the present invention includes a wafer carrier 10 for electrically connecting to an external device; at least one is pasted on the wafer carrier 10; a first wafer 11; at least one spacer 1 2 adhered to the first wafer 1 1 , the spacer 1 2 is provided with a slot 1 2 a; at least one is pasted on the first wafer 1 1 The second wafer 13 is received in the slot 1 2 a of the spacer 12; a plurality of bonding wires 14 for electrically connecting, the bonding wire 14 is electrically The wafer carrier 10, the first wafer 1 1 , the spacer 1 2 and the second wafer 13 are connected to each other; and an encapsulant 15 for packaging, the encapsulant 15 is formed on the wafer carrier The first wafer 1 1 , the spacer 1 2 , the second wafer 13 , and the bonding wire 14 are coated on the 1 0. The above method for fabricating the stacked wafer semiconductor package 1 further includes: preparing a wafer carrier 10, above the wafer carrier 10

17567石夕品.ptd Page 13 1246754 V. Description of the Invention (8) The at least one first wafer 1 1 is adhered on the surface 10 a, so that the first wafer 11 is above the wafer carrier 10, The top surface of the first wafer 1 1 is adhered to a spacer 12 between the trenches 1 2 a, and a second wafer 1 3 is pasted over the first wafer 1 1 , and the second wafer 13 is filled. The wafer carrier 10, the first wafer 1 1 , the spacer 1 2 and the second are electrically connected by the bonding wire 14 according to the layout design of the spacer 1 2 . The wafer 13 is finally formed on the wafer carrier 10 by an encapsulant 15 to cover the first wafer 1 , the second wafer 13 and the bonding wire 14 are stacked and electrically connected. After the completion of the structure, the packaging process is completed. The slot 1 2 a is penetrated through the spacer 12 , and the area of the second wafer 13 is smaller than the slot 1 2 a of the spacer 12 , so that the second chip 13 can be accommodated. The first wafer 11 is disposed on the top surface of the first wafer 1 1 so as to be in direct contact with the top surface of the first wafer 1 1 , and due to the first The wafer 11 and the second wafer 13 are made of the same material, and the thermal expansion coefficients of the two are the same. Therefore, if the sealing member of the present invention is delaminated due to the mismatch of the thermal expansion coefficient of the contact interface, compared with the conventional structure. The probability of the phenomenon will be greatly reduced, and the first wafer 11 and the second wafer 13 will not be damaged by temperature. In FIG. 1A and FIG. 1B, a plurality of wire bonding pads 10b are disposed on the wafer carrier 10, and the top surface of the first wafer 11 has a working surface 1 1 a on the active surface 1 1 a upper ring is provided with a plurality of fresh pads (b ο nding pad ) 1 1 b, and the bonding wires 1 4 are connected to the bonding pads 1 1 b of the first wafer 1 1 and the bonding pads 10 b of the wafer carrier 10, The first wafer 11 is electrically connected to the wafer carrier 10; at the same time, the top mask of the spacer 12 has an active surface 1 2 b, and the upper ring thereof

7567石夕品.ptd Page 14 1246754 V. INSTRUCTION DESCRIPTION (9) A plurality of bonding pads 1 2 c are provided, and the area of the spacer 12 is smaller than the first wafer 1 1 ' to make the spacer! 2, after being stacked on the top surface of the first wafer 11 , the bonding wire 1 1 b of the first wafer 1 1 and the bonding pad 1 2 c ' of the spacer 1 2 are electrically connected to the first A wafer 11 and a spacer 1 2 are provided. Furthermore, the top mask of the second wafer 1 has an active surface 13 3 a, and a plurality of pads 13 b are disposed on the active surface 13 3 to accommodate the second wafer 13 in the opening of the spacer 1 2 . After the slot 1 2 a, the bonding pad 4 is connected to the bonding pad 1 3 b of the second wafer 3 and the bonding pad 1 2 c of the spacer 1 2 to electrically connect the second wafer 13 and the spacer 1 2, and because the second wafer cassette 3 is received in the slot 1 2 a of the spacer plate 2, the second wafer 13 is placed on the same level as the spacer plate 12, and is obtained on a plane. By making the connection, this design will shorten the connection length of the wire bond 4 and can eliminate the lack of high line arc height in the conventional connection mode, thereby greatly reducing the height of the overall package. The electrical connection design of the present invention can also be as shown in FIG. 2, so that the bonding pad 1 2C of the spacer 12 is electrically connected to the bonding pad 〇4 of the wafer carrier by the bonding wire 4 The spacer 12 can be directly electrically connected to the wafer carrier 1 ,, and can also achieve the jumper and telecommunication transmission efficiency of the present invention. Therefore, the partition 12 and the groove 1 2 a are designed by the present invention to accommodate the second crystal # i 3 in the slot! In 2a, it will greatly reduce the height of the whole package. It also reduces the length of the wire and the small package and enhances the electrical properties. In addition, due to its overall structure, it is a defect, and the turbulence resistance of the mesh is reduced. - comparison:: molded product Α ten τ, into a square; subsequent high-temperature process produces a popcorn phenomenon, and compared to the prior art, the wafer of the present invention

7567石夕品.ptd Page 15 1246754 V. INSTRUCTIONS (10) Stacking on each other, the thermal expansion coefficient is the same, so that the phenomenon that the wafer and the substrate are delaminated due to the mismatch of thermal expansion coefficient can be avoided. In the above-mentioned stacked wafer semiconductor package of the present invention, the wafer carrier 10 can have various designs, and can be any conventional wafer carrier. For example, in FIG. 3, the wafer carrier is further disclosed. The device 10 is a lead frame 10', and the lead frame 1' has a wafer holder 10 a ', and the first wafer 11 and the spacer 1 stacked thereon are provided. 2 and the younger> a wafer 1 3 is adhered to the wafer holder 10a' and then electrically connected to the main line 14 and finally packaged with the encapsulant 15 5, which can be externally connected by the lead frame 1 The device is electrically connected, which is a specific embodiment of the invention. Further, as shown in FIG. 4, the wafer carrier 1 is disclosed as a printed circuit board 10", and the printed circuit board is a laminated substrate (Bui 1 dip Substrate) or pressure. Laminated Substrate, having at least one wafer holder 10a" on the printed circuit board 1" and having a plurality of solder balls 10bn implanted on the bottom surface of the printed circuit board 1" The wafer holder is placed on the wafer holder, and the spacers 丨2 and the second wafer cassette 3 are stacked on the sheet 1 and the second wafer 丨3, and then the bonding wire 丨4 is performed. The second embodiment is a second embodiment of the present invention. The second embodiment of the present invention is shown in FIG. 5, which is electrically connected, and then encapsulated by a package of plastics, and is electrically connected to an external device by solder balls b π. The implementation of the multi-wafer stacking package is to first mount the first wafer ii above the crystal=carrier 1 , and then over the first wafer ii =: the spacer 1 2 and the second wafer 13 , and then the second The second surface of the wafer i 3 is stacked on the top surface of the second θ 1 16 , and then electrically connected by the bonding wire 14 to encapsulate the colloid 1 5 Finish

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Page 16 1246754 V. INSTRUCTION DESCRIPTION (11) Forming a package, which is a third embodiment of the present invention; or as shown in FIG. 5B, first mounting a first wafer 1 1 above the wafer carrier 10 The second wafer 13 is stacked on the top surface of the first wafer 1 1 , and the spacers 1 2 and the third wafers 16 are stacked on the top surface of the second wafer 13 , and then electrically connected by the bonding wires 14 . And encapsulating with the encapsulant 15 is a fourth embodiment of the multi-wafer stack of the present invention. The above-described embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application to be described later.

17567石夕品.ptd第第7页1246754 BRIEF DESCRIPTION OF THE DRAWINGS [Simplified Schematic] FIG. 1A is a cross-sectional view showing a semiconductor package of a stacked wafer of the present invention and a method for fabricating the same; A top view of a semiconductor package of a stacked wafer and a method for fabricating the same; FIG. 2 is a cross-sectional view showing another embodiment of the semiconductor package of the stacked wafer of the present invention and a method for manufacturing the same; A cross-sectional view of a semiconductor package of a stack of wafers of a wafer carrier and a method for fabricating the same; FIG. 4 is a second embodiment of a semiconductor package of a stack of wafers with a circuit board as a wafer carrier and a method for fabricating the same FIG. 5A is a cross-sectional view showing a third embodiment of a stacked package of a semiconductor package of the present invention and a multi-wafer stacked package of the same; FIG. 5B is a semiconductor package of the stacked wafer of the present invention; A cross-sectional view of a fourth embodiment of a multi-wafer stacked package of the method of manufacturing; FIG. 6A is a cross-sectional view of the semiconductor package disclosed in US Pat. No. 5,7,7,3, 4, 5; A top view of a semiconductor package disclosed in U.S. Patent No. 5,7, 7, 7, 4, and a sectional view of a semiconductor package disclosed in U.S. Patent No. 6,0,0,7,8,8 And Figure 8 is a cross-sectional view of the semiconductor package disclosed in U.S. Patent No. 5,7,155,147.

7567石夕品.ptd Page 18 12467754 1 Stacked wafer semiconductor package diagram simple description 10, 50 wafer carrier 10, 20 lead frame 1 οπ printed circuit board 10a, 1 la, 12b, 1; 3a function Face 10a, > 10 aM > 201 wafer holder 10b, 12c bond pad 10bM solder ball 1b 21 > 51, 6 1 first wafer lib, 13b pad 12a slot 12 spacer 13 , 22 > 53 ^ 62 second wafer 14, 23 ^ 54 ^ 66 bonding wire 15, 24 encapsulant 16 second wafer 202 pin 21 221 long fresh pad 511 surface 52 spacer 601 internal pin 60 carrier 63 ^ 64, 65 circuit board

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Claims (1)

1246754 6. Patent application scope 1. A stacked wafer semiconductor package, comprising: a wafer carrier having a bearing surface; at least one first wafer attached to a bearing surface of the wafer carrier; at least one a spacer plate is disposed on an opposite surface of the first wafer that is not connected to the wafer carrier, and a slit is formed on the spacer; at least one second chip is disposed in the spacer a plurality of bonding wires are electrically connected to the wafer carrier, the first wafer, the spacer, and the second wafer, and are disposed on the opposite surface of the first wafer not connected to the wafer carrier; And the encapsulant is formed on the wafer carrier to cover the first wafer, the spacer, the wafer, and the fresh wire. 2. The stacked wafer semiconductor package of claim 1, wherein the wafer carrier is a lead frame (1 e a d f r a m e ). 3. The stacked wafer semiconductor package of claim 1, wherein the wafer carrier is a printed circuit board. 4. The stacked wafer semiconductor package of claim 3, wherein the printed circuit board is a build-up substrate (B u i 1 d - u p Substrate). 5. The stacked wafer semiconductor package of claim 3, wherein the printed circuit board is a laminated substrate (L a m i n a t e d Substrate). 17567 石夕品.ptd Page 20 1246754 6. Patent application scope 6. The stacked wafer semiconductor package of claim 1, wherein the slot is through the spacer. 7. The stacked wafer semiconductor package of claim 1, wherein the spacer has an area smaller than the first wafer. 8. The stacked wafer semiconductor package of claim 1, wherein the second wafer has an area smaller than a slot of the spacer. 9. The stacked wafer semiconductor package of claim 1, wherein the spacer is a printed circuit board. 10. The stacked wafer semiconductor package of claim 1, wherein the carrier surface of the wafer carrier has a plurality of wire mats 0 1 1. As claimed in claim 1 A stacked wafer semiconductor package, wherein a plurality of solder pads are disposed on an opposite surface of the first wafer that is not attached to the wafer carrier. The stacked wafer semiconductor package of claim 1, wherein a plurality of bonding pads are disposed on an opposite surface of the spacer that is not attached to the first wafer. 1. The stacked wafer semiconductor package of claim 1, wherein the second wafer is not provided with a plurality of pads on the surface of the first wafer. 1 . A method of fabricating a stacked wafer semiconductor package, comprising the steps of: preparing a wafer carrier having an attachment surface; and attaching at least one first wafer to the wafer carrier 17567石夕品.ptd Page 21 12467754 VI. Application for patent coverage; preparation of at least one spacer, the spacer is provided with a slot, and the spacer is placed on the first wafer and the wafer ???the opposite surface of the carrier; the at least one second wafer is prepared, and the second wafer is placed on the opposite surface of the first wafer not connected to the wafer carrier, and the second wafer is accommodated The chip carrier, the first wafer, the spacer, and the wafer are electrically connected by a bonding wire, and an encapsulant is formed on the wafer carrier to cover the first wafer. , spacer, second wafer and bonding wire. The method of claim 14, wherein the wafer carrier is a lead frame. The method of claim 14, wherein the wafer carrier is a printed circuit board. The method of claim 16, wherein the printed circuit board is a build-up substrate. 18. The method of claim 16, wherein the printed circuit board is a laminated substrate. The method of claim 14, wherein the slotting system extends through the spacer. The method of claim 14, wherein the spacer has a smaller area than the first wafer. 2 1. The method of claim 14, wherein the second chip 17567石夕品.ptd Page 22 1246754 VI. Scope of Application The area size is smaller than the slot of the spacer. 2 2. The method of claim 14, wherein the spacer is a printed circuit board. The method of claim 14, wherein the carrier surface of the wafer carrier has a plurality of wire pads (f i n g e r ). The method of claim 14, wherein the first wafer is not attached to the wafer carrier, and a plurality of bonding pads are provided on the opposite surface of the wafer carrier. The method of claim 14, wherein the plurality of bonding pads are disposed on the opposite surface of the spacer that is not attached to the first wafer. The method of claim 14, wherein the second wafer is not provided with a plurality of pads on the surface of the first wafer. 2 7. A stacked wafer semiconductor package, comprising: a wafer carrier having a bearing surface; at least one first wafer attached to a bearing surface of the wafer carrier; at least one spacer And the first wafer is disposed on the opposite surface of the spacer, and the spacer is provided with a slot; the at least one second chip is received in the slot of the spacer, and And disposed on an opposite surface of the first wafer that is not connected to the wafer carrier; at least one third wafer is disposed on an opposite surface of the second wafer that is not connected to the first wafer; 17567石夕品.ptd Page 23 1246754 VI. Application for a patent range A plurality of bonding wires are used to electrically connect the wafer carrier, the first wafer, the spacer, the second wafer and the second wafer, and the encapsulant. Formed on the wafer carrier to cover the first wafer, the spacer, the second wafer, the third wafer, and the bonding wire. The stacked wafer semiconductor package of claim 27, wherein the wafer carrier is a lead frame (1 e a d f r a m e ). The stacked wafer semiconductor package of claim 27, wherein the wafer carrier is a printed circuit board. 3. The stacked wafer semiconductor package of claim 29, wherein the printed circuit board is a layered substrate (Bui 1 d - up Substrate) ° 1. The stacked chip semiconductor package of the ninth item, wherein the printed circuit board is a laminated substrate, wherein the stacked wafer semiconductor package of the second aspect of the patent application, wherein The slot extends through the spacer. 3. The stacked wafer semiconductor package of claim 27, wherein the spacer has an area smaller than the first wafer. The stacked wafer semiconductor package of claim 27, wherein the second wafer has an area smaller than the opening of the spacer. The stacked wafer semiconductor package of claim 27, wherein the spacer is a printed circuit board. 3 6. A stacked wafer semiconductor package as claimed in claim 27, 17567 石夕品.ptd Page 24 1246754 VI. Patent Application Range The carrier surface of the wafer carrier has a plurality of wire bonds. The stacked wafer semiconductor package of claim 27, wherein a plurality of solder bumps (b ο n d i n g p a d ) are disposed on an opposite surface of the first wafer that is not attached to the wafer carrier. The stacked wafer semiconductor package of claim 27, wherein a plurality of bonding pads are disposed on an opposite surface of the spacer that is not attached to the first wafer. The stacked wafer semiconductor package of claim 27, wherein the surface of the second wafer not attached to the first wafer is provided with a plurality of fresh slabs. 40. The stacked wafer semiconductor package of claim 27, wherein the third wafer is not provided with a plurality of pads on the surface of the second wafer. 4 1. A method of fabricating a stacked wafer semiconductor package, comprising the steps of: preparing a wafer carrier having an attachment surface; attaching at least one first wafer to an attachment surface of the wafer carrier Preparing at least one spacer, the spacer is provided with a slot, and the spacer is disposed on an opposite surface of the first wafer not connected to the wafer carrier; at least one second wafer is prepared, and Locating the second wafer on an opposite surface of the first wafer that is not attached to the wafer carrier 17567石夕品.ptd page 25 1246754 6. Patent application scope The second wafer is accommodated in the slot of the spacer; at least one third wafer is prepared, and the third wafer is placed on the second wafer An opposite surface of the first wafer; the wafer carrier, the first wafer, the spacer, the second wafer, and the third wafer are electrically connected by a bonding wire; and an encapsulant is formed on the wafer carrier The first wafer, the spacer, the second wafer, the third wafer, and the bonding wire are covered. 4 2. The method of claim 41, wherein the wafer carrier is a lead frame (1 e a d f r a m e ). 4: The method of claim 41, wherein the wafer carrier is a printed circuit board. 4: The method of claim 4, wherein the printed circuit board is a build-up substrate. 4: The method of claim 4, wherein the printed circuit board is a laminated substrate. 4: The method of claim 41, wherein the slotting system extends through the spacer. The method of claim 41, wherein the spacer has a smaller area than the first wafer. 4: The method of claim 41, wherein the second wafer has an area size smaller than a slot of the spacer. 4 9. The method of claim 41, wherein the spacer is a printed circuit board. 50. The method of claim 41, wherein the wafer carrier 17567 石夕品.ptd Page 26 1246754 VI. The patented range has a plurality of wire mats (f i n g e r ) on the load bearing surface. The method of claim 4, wherein a plurality of bonding pads are disposed on an opposite surface of the first wafer that is not attached to the wafer carrier. The method of claim 4, wherein a plurality of wire mats are disposed on an opposite surface of the spacer that is not attached to the first wafer. The method of claim 4, wherein a plurality of pads are provided on the surface of the second wafer that is not attached to the first wafer. The method of claim 4, wherein the third wafer is not attached to the second wafer with a plurality of pads. 5 5. A stacked wafer semiconductor package, comprising: a wafer carrier having a bearing surface; at least one first wafer attached to a bearing surface of the wafer carrier; at least one second wafer, And being disposed on an opposite surface of the first wafer not connected to the wafer carrier; at least one spacer is disposed on an opposite surface of the second wafer not connected to the first wafer, and the spacer The upper system is provided with a slot; at least one third chip is received in the slot of the spacer and is disposed on the opposite surface of the second wafer not connected to the first die; a plurality of bonding wires, Used to electrically connect the wafer carrier, the first wafer, the second wafer, the spacer, and the second wafer, and 17567 石夕品.ptd Page 27 1246754 VI. Application Patent The encapsulant is formed on the wafer carrier to cover the first wafer, the second wafer, the spacer, the third wafer and the bonding wire. The stacked wafer semiconductor package of claim 5, wherein the wafer carrier is a lead frame (1 e a d f r a m e ). The stacked wafer semiconductor package of claim 5, wherein the wafer carrier is a printed circuit board. 5 8 . The stacked wafer semiconductor package of claim 57, wherein the printed circuit board is a layered substrate (Bui 1 d - up Substrate) 〇 5 9 . The stacked-wafer semiconductor package of the fifth aspect, wherein the printed circuit board is a laminated substrate, and the stacked wafer semiconductor package of the fifth aspect of the patent application, wherein The slot extends through the spacer. The stacked wafer semiconductor package of claim 5, wherein the spacer has an area smaller than the second wafer. The stacked wafer semiconductor package of claim 5, wherein the third wafer has an area smaller than a slot of the spacer. 6. The stacked wafer semiconductor package of claim 5, wherein the spacer is a printed circuit board. The stacked wafer semiconductor package of claim 5, wherein the carrier surface of the wafer carrier has a plurality of wire bonds. [7] 567 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 A plurality of solder bumps (b ο ndingpad) are attached to the opposite surface. 6. The stacked wafer semiconductor package of claim 5, wherein the second wafer is not provided with a plurality of pads on the surface of the first wafer. The stacked wafer semiconductor package of claim 5, wherein the spacer is not provided with a plurality of bonding pads on the opposite surface of the second wafer. 6. The stacked wafer semiconductor package of claim 5, wherein the third wafer is not provided with a plurality of pads on the surface of the second wafer. 6 9. A method of fabricating a stacked wafer semiconductor package, comprising the steps of: preparing a wafer carrier having an attachment surface; attaching at least one first wafer to an attachment surface of the wafer carrier Preparing at least one second wafer, and attaching the second wafer to an opposite surface of the first wafer not attached to the wafer carrier; preparing at least one spacer, the spacer having a slot And the spacer is placed on the opposite surface of the second wafer that is not connected to the wafer; at least one third wafer is prepared, and the third wafer is placed on the second wafer The first wafer is attached to the opposite surface, and the 17567石夕品·ptd Page 29 1246754 VI. Patent application The third wafer is accommodated in the slot of the spacer; the wafer carrier, the first wafer, the second wafer, and the spacer are electrically connected by a bonding wire. And a third wafer; and forming an encapsulant on the wafer carrier to cover the first wafer, the second wafer, the spacer, the third wafer, and the bonding wire. 70. The method of claim 96, wherein the wafer carrier is a lead frame. The method of claim 96, wherein the wafer carrier is a printed circuit board. 7 2. The method of claim 71, wherein the printed circuit board is a build-up substrate. 7: The method of claim 71, wherein the printed circuit board is a laminated substrate. The method of claim 69, wherein the slotting system runs through the spacer. 7 5. The method of claim 96, wherein the spacer has a smaller area than the second wafer. The method of claim 69, wherein the third wafer has an area size smaller than a slot of the spacer. 7 7. The method of claim 96, wherein the spacer is a printed circuit board. The method of claim 96, wherein the carrier surface of the wafer carrier has a plurality of wire pads (f i n g e r ). 7 9 . The method of claim 96, wherein the first wafer is not 7567石夕品.ptd Page 30 1246754 VI. Scope of Application A plurality of bonding pads are provided on the opposite surface of the wafer carrier. The method of claim 69, wherein a plurality of pads are provided on a surface of the second wafer that is not attached to the first wafer. The method of claim 69, wherein a plurality of wire bond pads are disposed on an opposite surface of the spacer that is not attached to the second wafer. The method of claim 69, wherein a plurality of pads are provided on the surface of the third wafer that is not attached to the second wafer. 17567 Shi Xipin.ptd第31页