TW200522294A - Semiconductor package having stacked chip and a method for fabricating - Google Patents

Abstract

A semiconductor package having stacked chip and a method for fabricating the same are proposed. A semiconductor package includes a chip carrier having a carrier surface. At least one first chip is mounted on the carrier surface of the chip carrier. A spacer formed with a recess is used receive a second chip. Wires are bonded to be electrically connected the chip carrier, spacer, first chip and second chip. A resin body is formed to encapsulate the chip carrier, spacer, first chip, second chip and wires. By means of the recess of the spacer, the semiconductor package can be reduced in thickness and volume, and delaminate of the chips and uneven speed of the resin flow can be prevented.

Description

200522294 V. Description of the invention (1) [Technical field to which the invention belongs] A semiconductor package of a stacked wafer and a manufacturing method thereof, in particular-a semiconductive μ package of a stacked wafer capable of reducing the overall height of the semiconductor package and its System of law. [Previous technology] With the vigorous development of the electronics industry, electronic products are gradually moving towards the research and development direction of rural energy and high performance, 'to meet the integration and miniaturization of semiconductor packages' high integration sound and miniaturization. The package needs to be long and in order to improve the performance and capacity of a single semiconductor package, in order to comply with the trend of electronic products' miniaturization, large capacity and high speed, it is known that most of the half-body package is modularized with multiple chips M u 1 ti C hip Μdu 1 e; MC Μ), this package can also reduce the overall package size and improve electrical functions, and has become a mainstream package, which is based on a single package At least two semiconductor chips are mounted on the wafer carrier of the device, and each wafer and the chip carrier are connected in a vertical stack. Such a stacked chip package structure has been seen in U.S. Patent Nos. 5, 7 7 7, 3 4 5 and 5, 7 9 3, 108, 5, 502, 2 889, 6, 005, 7 7 8 etc. Knowing technology. ▲ Figure 6A is a cross-sectional view of a coating member disclosed in US Patent No. 5,7 7 7, 3 4 5 'It is a wafer holder 2 0 1 in a lead frame (1 ead ^ rame) 2 0 A first wafer 2 i is installed below, and a second wafer 22 is adhered below the first wafer 21, and a plurality of long welding pads are respectively arranged below the first wafer 21 and the second wafer 22 ( The bonding pad 21 1 and the bonding pad 221 are connected to the long bonding pad 21 1 of the first chip 21 and the lead frame through a bonding wire 2 3.

] 7567 石 夕 品 .ptd Page 7 200522294 V. Description of the invention (2) Guide pin 202 of 2 0, and the long pad 2 of the first-wafer 2 1 and the pad 2 of second-wafer 22 2 1 is also connected by welding wire 2 3, so that the lead frame 20, the first chip 21 and the second chip 22 can be electrically connected, and the lead frame 20 of the lead frame 2 0 is connected to the outside. The device is electrically connected, and finally the whole is encapsulated with encapsulant 2 4 to complete the encapsulation process. And for this type of package, the second chip 22, which is stacked on top, can be electrically connected to The lead pins 2 0 2 of the lead frame 20 must be provided on the first chip 2 1 with a long fresh patch 2 1 1 to provide a jumper, so that the second chip 2 2 can be used by the first chip 2 The long pad 2 on the 1 2 and the jumper 2 on the jumper 2 3 are shown in Figure 6B on the 0, but the long pad 2 for jumper is added on the first chip 21 [1 will increase The large area leads to the overall size. Dimensions are reduced and the special design of the long pad 21 L 1 is not like a traditional crystal. The design method of the chip will increase the manufacturing cost of the chip and become a serious bottleneck in the development of multi-chip packages. Therefore, another multi-chip module is shown in Figure 7: US Patent No. 6, 0, 05, Patent No. 7 7 No. 8 is that a-wafer 51 is placed on the--crystal moon carrier 50 0 ^ on the surface of the first wafer 5 1 opposite to the wafer carrier 5 0] l 1 Set--volume / J, the spacer ▲ (space) r:) 52 on the first wafer 51, and set the spacer 51 2 to the surface 51 1 -Λ 妾 of the first wafer 51 with a volume equivalent to The area size of the second wafer 53 of the first wafer 51 and the spacer 52 are smaller than those of the first wafer 51 and the second wafer 53, so that the first wafer 51 and the first wafer 53 can pass through a plurality of solder joints. Line 54 is electrically connected to the wafer carrier 50. However, in this structure, because a spacer 52 is placed between the two wafers, and the thermal expansion coefficient of the spacer 52 is extremely different from that of a silicon wafer

17567 Shi Xipin.ptd Page 8 200522294 V. Description of the invention (3) Large, it will cause delamination caused by mismatched thermal expansion coefficients and cause wafer damage, and this cumulative stacking is disadvantageous in addition to increasing the wire length In addition to the electrical connection, the height of the package is increased, which is not conducive to the development of package thinning. Therefore, for the aforementioned stacked chip semiconductor package, although the restrictions on the electrical layout can be fully addressed in the design, the number of layers and thickness of the chip stack are also increased, which is contrary to the trend of thinning the package, and Further, as disclosed in the aforementioned US Patent No. 5,502,289, the design of adding a substrate between the wafers to facilitate jumpers may also be because the coefficient of thermal expansion (CTE) between the substrate and the wafers is too large, and Delamination of the contact interface between the substrate and the wafer will cause damage to the wafer; Furthermore, for this type of stacked wafer semiconductor package, adding a substrate between each wafer will increase the thickness of the substrate. When the sealing process is used to encapsulate the wafer and the wafer carrier by the encapsulating gel, the number of the stacked wafers is too large, which causes the mold formed by the encapsulating gel to flow into the cavity. In the process, too much resistance to mold flow is encountered, which in turn causes uneven distribution, leading to the occurrence of air holes (v ο 1 d), which reduces the packaging quality. Therefore, even though these conventional stacked chip packages can solve the problem of jumper f characteristics, they are not suitable for structural or process problems such as the overall height is too high, the bond wire arc is too long, the thermal expansion coefficient does not match, or the mold flow resistance increases. Obviously, it is difficult to improve, and it is a major obstacle to multi-chip packaging technology. Moreover, these problems can be improved by changing the multi-chip configuration, such as US Patent No. 5,7 1 shown in Figure 8. Patent No. 5, 1 4 7 is a multi-chip module in which a plurality of chips are arranged side by side, and is connected to a carrier (1 s 1 and) 6 0

17567 硅 品 .ptd Page 9 200522294 V. Description of the invention (4) The outer ring is provided with a plurality of inner pins (inner 丨 ead) 6 0, and a first chip 6 is installed on the carrier 60. The second chip 6 2 and the circuit board 6 3 are provided with a circuit board 64 ′ on the internal pin 6 0 1, and a plurality of circuit boards 6 5 ′ are installed above the first chip 6 1 and the second chip 6 2. Electrically connect through (electrically connect i ng means) to connect the first chip ㊀ 丄 = 65, and the electrical connection is installed on a fresh line and side by side-crystal two: solve the overall height ... ask the stomach, then its The water loading area is also the same as that of the helmet and the chip-chip 62. The overall sealing of the chip 62 has increased the overall sealing. PB, π, + ...., / to achieve the purpose of small volume packaging. Whatever changes, as long as the existing package design, regardless of its structure, so what ;; the design of i is not difficult to take into account all the conventional problems to reduce its overall high-end two-chip semiconductor package To determine the coefficient of thermal expansion; t: the package area, together with the urgent need to improve the electrical field and solve the problem = and the non-uniformity of the mold flow, etc. This is the research and development of the invention. The stacked B μ 卩 provides a two-piece semiconductor package and a method for manufacturing the same, which can reduce the entirety of the semiconductor package. 4 #Using long solder pads: S's are providing a jumper function which is not available. 'Semiconductor package of stacked wafer and its double layer of the present invention, and can shorten the bonding wire length and its manufacturing method. & Aim and line That is to provide a semiconductor package of stacked chip at the arc height k without increasing the yield of the package.

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200522294 V. Description of the invention (5) The present invention provides a semiconductor package for a stacked wafer that can avoid delamination due to mismatched expansion coefficients and a method for manufacturing the same. 0 Another aspect of the present invention is In providing— > a semiconductor package of a stacked wafer capable of reducing encapsulation mold flow resistance and cavitation generation, and a method for manufacturing the same 0 In order to achieve the above and other aspects of the present invention, a structure system of a stacked wafer semiconductor package is provided At least one first wafer including a wafer carrier having a bearing surface is connected to the bearing surface of the wafer carrier. At least one spacer plate is connected to an opposite surface of the first wafer that is not connected to the wafer carrier. And at least one slot is provided on the partition plate. * The chip is accommodated in the slot. A plurality of bonding wires 5 are arranged in the slot of the partition and placed on the opposite surface of the first wafer which is not connected with the wafer carrier. The wires 5 are used to electrically connect the wafer carrier, the first wafer spacer and the second wafer. A wafer; and a packaging colloid formed on the wafer carrier to cover the first wafer, the spacer, the second wafer, and the bonding wire. The manufacturing method of the stacked wafer semiconductor package of the present invention includes the following steps: Preparation — Wafer carrier, which has an interface surface J. At least-the first wafer is placed on the interface surface of the wafer carrier to prepare at least one spacer plate. The spacer plate is provided with a slot and the spacer A plate is placed on the opposite surface of the first wafer that is not connected to the wafer carrier to prepare at least-'a second wafer and the second wafer is placed on the first wafer The second wafer is accommodated in the slot of the spacer plate on the opposite surface connected to the wafer carrier, and the wafer spacer, the first wafer spacer plate and the first wafer are linearly connected by welding, and the wafer carrier Form

17567 "Xipin.ptd Page 11 200522294 V. Description of the invention (6) Two encapsulants to cover the first wafer, the spacer, the second wafer and the bonding wires. The aforementioned second wafer is accommodated in the slot of the spacer plate, so that the second wafer and the spacer plate are in the same layer structure, and the second wafer and the spacer plate are stacked together above the first wafer to become ^ ^ The two-layer structure 'reduces the number of layers to reduce the overall package height, which can reduce the mold flow resistance and reduce the generation of air holes. Furthermore, the second wafer is accommodated in the slot of the spacer plate, so that the second wafer and the spacer plate are positioned on the same horizontal plane, so that the electrical connection between the second wafer and the spacer can be connected to one another. The connection is made on the plane, so as to avoid the situation that the bonding wire is too long and the arc height is too high, so as to shorten the bonding wire length and the arc height, thereby reducing the overall package height. The second wafer is accommodated in the slot of the spacer plate, so that the second wafer is directly mounted on the top surface of the first wafer, and the first wafer and the second wafer are the same material, and the thermal expansion of the two is The coefficient is the same to avoid the delamination phenomenon caused by the contact interface to damage the wafer. It is not necessary to avoid the stacking of non-homogeneous or non-approximate materials, which results in the difference in the thermal expansion coefficient between the two. Thermal stresses remain and damage the wafer. [Embodiment] The following is a description of specific embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be modified by other

17567 ^ 品 .ptd Page 12 200522294 V. The specific embodiment of the invention description (7) is implemented or applied. The details in this specification can also be based on different perspectives and applications without departing from the spirit of the present invention. Various modifications and changes. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way. The invention is to stack a first wafer, a second wafer, and a spacer on a chip carrier, and a slot is opened on the spacer to accommodate the second wafer in the slot, so that The second wafer and the spacer are located on the same layer in the stacked structure, and are stacked on the first wafer together to form a two-layer structure, which are described in detail in the following embodiments. Please refer to FIG. 1A and FIG. 1B. The stacked chip semiconductor package 1 of the present invention includes a chip carrier 10 for electrically connecting with an external device; at least one is stuck on the chip carrier 10 A first wafer 1 1; at least one spacer plate 12 glued above the first wafer 11, the spacer plate 12 is provided with a slot 1 2 a; at least one glued above the first wafer 11 The second wafer 1 3, and the second crystal moon 13 is housed in the slot 1 2a of the spacer 12; a plurality of bonding wires 14 for electrical connection, the bonding wires 1 4 are The above-mentioned wafer carrier 10, the first wafer 11, the spacer 12 and the second wafer 1 3 are electrically connected; and an encapsulating gel 15 for encapsulation is formed on the wafer carrier. The part 10 is covered with the first wafer 11, the spacer 12, the second wafer 13, and the bonding wire 14. The manufacturing method of the above-mentioned stacked wafer semiconductor package 1 further includes: preparing a wafer carrier 10, and working on the wafer carrier 10

17567 硅 品 .ptd Page 13 200522294 V. Description of the invention (8) Occupy at least one first wafer 11 on the surface 10a, so that the first wafer u is located above the wafer carrier 10, where A top surface of the first wafer i 1 is adhered with a partition 12 having a slot 12 a, and a second wafer 13 is adhered on the first wafer i ^, and the second wafer 13 is accommodated. Within the slot 1 2 a of the spacer plate 12, then the above-mentioned wafer carrier 10, the first wafer 11, the spacer plate i 2, and the second wafer are electrically connected with bonding wires according to the circuit layout design. 1 3. Finally, an encapsulating gel 15 is formed on the wafer carrier j 0 to cover the first wafer 1 and the spacer 1 2. The second wafer 丨 3 and the bonding wire 丨 4 are stacked and electrically connected. The structure is to complete the packaging process. The above-mentioned slot 12a is penetrated through the spacer plate 12, and the area size of the second wafer 13 is smaller than the slot 丨 2a of the spacer plate 2 so that the second wafer 13 can be accommodated in the spacer 12 On: (: 1 2 a Uchida ^ ^ Bu Jianjin sundial and erected on the top surface of the first wafer 11 to make the second wafer 13 3 Kyrgyzstan. Θ, ^ .. piece 1 JT is directly in contact with the top surface of the first chip 11 and it is located on the top surface of the first wafer. The photo of the thermal expansion coefficient of the two is the same as that of the first one. Therefore, the 13 film is of the same material. Contact interface 埶 ::: The probability of inventing the phenomenon will be greatly reduced. The delamination caused by the mismatch of the expansion coefficients is now A, 4 #, L1, 1st wafer 1 1 and 2nd wafer 1 3 will not be damaged by the temperature of the text. In Figures 1A and 1B, the chip 7? ≪ and should be humble, r λ, nu. A number of wire pads are provided above the carrier 10 ( finger) lOb, and the -θu, said sheet 1 1 top mask has an active surface 1 1 a, on the active surface 1 1 a is provided with a blessing plate, and A is provided with several bonding pads 1 1 b, get fresh line 1 4 Connect the pads 1 1 b of the sheet 1 1 to the pads 1 Ob of the wafer carrier 10, so that the first crystal H t + $, the main crystal · · e 士 # μ,-,. The sheet 1 1 is electrically connected to the wafer carrier 10, and on the same day, the top surface of the τ ′ 5 helical spacer plate 12 and the name 4 has an active surface 1 2 b, and the upper ring

17567 石 夕 品 .ptd page] 4 200522294 V. Description of the invention (9) A plurality of bonding pads 1 2 C are provided, and the area size of the spacer plate 12 is smaller than that of the first wafer 11 so that the spacer plate 1 2 is stacked on the top surface of the first wafer 1 1, and the bonding wire 14 can be connected to the bonding pad 1 1 b of the first wafer 11 and the bonding pad 1 2 c of the spacer 12 to electrically connect the first wafer 1 1 One wafer 11 and a spacer 12. Furthermore, the top surface of the second wafer 13 has an active surface 1 3 a, and a plurality of solder pads 1 3 b are provided on the active surface 1 3 a so that the second wafer 13 is accommodated in the spacer plate 1 2 After the slot 1 2 a is formed, the bonding wire 14 can be connected to the bonding pad 1 3 b of the second wafer 13 and the bonding pad 1 2 c of the spacer 12, and the second wafer 13 and the gap can be electrically connected. Plate 12, and the second wafer 13 is housed in the slot 12a of the spacer plate 12, so that the second wafer 13 and the spacer plate 12 are at the same level, so that The connection is made on a plane. This design will shorten the connection length of the bonding wire 14 and avoid the lack of excessive arc height in the conventional connection method, thereby greatly reducing the height of the overall package. The electrical connection design of the present invention may also be as shown in FIG. 2, so that the bonding pads 1 2 c of the spacer plate 12 can be bonded to the bonding pads 1 4 to be electrically connected to the bonding pads 1 0 b of the chip carrier 10. The spacer 12 can be directly and electrically connected to the chip carrier 10, and can also achieve the jumper and telecommunication transmission effects of the present invention. Therefore, by designing the spacer 12 and the slot 12a of the present invention, < to accommodate the second chip 13 in the slot 12a, the height of the overall package can be greatly reduced. It is also necessary to reduce the wire length and arc height to achieve the purpose of thin and small packages and improve electrical properties. In addition, because its overall height is reduced, the mold flow resistance relative to the packaging gel is reduced, and a better molding can be obtained. Quality, to avoid air holes caused by uneven mold flow, and to produce gas explosion (P 0pc 〇r η) in subsequent high-temperature processes. Compared with conventional technology, the wafer of the present invention

17567 Shi Xipin.ptd Page 15 200522294 V. Description of the invention (10) Stacking each other 孰 / ”Λ The same surge coefficient can avoid the delamination of the wafer and the substrate in the conventional structure due to the mismatch of the inflation coefficient. Phenomenon 0 In the stacked wafer semiconductor package of the present invention disclosed above, its wafer carrier 1 can have various design forms, and it can be any conventional wafer carrier such as that shown in FIG. 3- -Step reveals the wafer carrier: 1 0 is-a lead frame (1 e ad frai ne) 1 0, and the lead frame 10, has a wafer holder 10a 'on the first wafer 1: 1 and The spacer 1 stacked on it; the second chip 1 3 is glued on the wafer holder 1] a ′, and then electrically connected with the bonding wire 14, and then the package is completed with the encapsulation gel 15, which can be borrowed. Connected by lead frame 10 '1 Embodiment 4 As shown in FIG. 4, the wafer carrier is disclosed as follows: ί 0 is a printed circuit board (pr i .ntedci rcu i _ t 1 bo; ard) 1 01 1? And the printed circuit board 1 丨 0 ”Is a build-up substrate (Bu) i ld-i Sub: 5 t 1 rate:) or a laminated substrate (Lam i na1; ed Subs' tr; at is), on the printed circuit board: 1 01, There is at least one wafer holder 10an and a plurality of solder balls 10bM are planted on the bottom surface of the printed circuit board 10 ''. The first wafer 11 above can be installed on the wafer holder 1C) aM 5 Repeat the foregoing steps to stack the spacer 12 and the second a-chip 13 on the first wafer 11 and then electrically connect with the bonding wire 14 and then complete the packaging with the packaging gel 15 to obtain the solder ball. 1 0 b 丨 丨 This is the second specific embodiment of the present invention for electrical connection with external devices. 0 Please refer to Figure 5A for the implementation of the multi-chip stack package 7 series Above the wafer carrier 10, the first-wafer 11 is first installed, and then stacked on the first wafer 11-& n. S and the spacer 12 and the second wafer 1-5, and then on the top surface of the second wafer 13 Stacked first — a aa piece 1 6 i, electrical connection is made by bonding wire 14 after the absence and encapsulation gel 1 5 is completed

] 7567 石 夕 品 .ptd Page 16 200522294 V. Description of the invention (11) The package is the third specific embodiment of the present invention; or as shown in FIG. 5B, it is above the wafer carrier 10 The first wafer 11 is installed, and the second wafer 13 is stacked on the top surface of the first wafer 11 and the spacer 12 and the third wafer 16 are stacked on the top surface of the second wafer 13. The bonding wires 14 are electrically connected and the encapsulation is completed with the encapsulant 15, which is the fourth specific embodiment of the multi-chip stacking of the present invention. The above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application mentioned later.

17567 Shi Xipin.ptd Page 17 200522294 Brief Description of Drawings * [Simplified Description of Drawings] Figure 1A is a cross-sectional view of a semiconductor package and a method for manufacturing the stacked wafer according to the present invention; Figure 1B is the present invention Top view of a semiconductor package of a stacked wafer and a manufacturing method thereof, and FIG. 2 is a sectional view of another embodiment of the semiconductor chip package of the stacked wafer and a manufacturing method of the bonding wire connection thereof; FIG. The lead frame is a cross-sectional view of a semiconductor package of a stacked wafer of a wafer carrier and a manufacturing method thereof; φ FIG. 4 is a second view of the semiconductor package of the stacked wafer of the present invention using a circuit board as a wafer carrier and a manufacturing method thereof Sectional view of implementation; FIG. 5A is a cross-sectional view of a third embodiment of a stacked-chip semiconductor package of the present invention and a multi-chip stacked package of the manufacturing method thereof; FIG. A cross-sectional view of a fourth embodiment of a multi-chip stack package manufactured by the method; FIG. 6A is a cross-sectional view of a semiconductor package disclosed in US Patent Nos. 5, 7 7 7, 3 4 5; 6 Figure B is a top view of a semiconductor < package disclosed in US Patent No. 5, 7 7 7, 3 4 5; _ Figure 7 is disclosed in US Patent No. 6, 0 0 5, 7 7 8 A cross-sectional view of a semiconductor package; and FIG. 8 is a cross-sectional view of the semiconductor package disclosed in US Patent Nos. 5,7,15,147.

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Claims (1)

200522294 VI. Application Patent Scope 1. A stacked wafer semiconductor package comprising: a wafer carrier having a bearing surface; at least one first wafer connected to the bearing surface of the wafer carrier; at least one A spacer plate is connected on the opposite surface of the first wafer which is not connected to the wafer carrier, and a slot is provided on the spacer plate; at least one second wafer is provided on the opening of the spacer plate. Inside the groove and placed on the opposite surface of the first wafer that is not connected to the wafer carrier; a plurality of bonding wires are used to electrically connect the wafer carrier, the first wafer, the spacer plate and the first Two wafers; and a packaging colloid formed on the wafer carrier to cover the first wafer, the spacer, the second wafer and the bonding wires. 2. For example, the stacked wafer semiconductor package according to the first patent application scope, wherein the wafer carrier is a lead frame (1 e a d f r a m e). 3. The stacked chip semiconductor package according to item 1 of the patent application scope, wherein the wafer carrier is a printed circuit board. < 4. If the stacked chip semiconductor package of item 3 of the patent application scope, in which, the printed circuit board is a build-up substrate (B ui 1 d-up Substrate) 0 5. If the scope of patent application The stacked wafer semiconductor package of item 3, wherein the printed circuit board is a laminated substrate 17567 Shi Xipin.ptd Page 20 200522294 17567 Shi Xipin.ptd Page 21 200522294 6. Apply for a patent; prepare at least one spacer plate, the spacer plate is provided with a slot, and the spacer plate is placed on the first wafer without the wafer The carrier is placed on the opposite surface; at least one second wafer is prepared, and the second wafer is placed on the opposite surface where the first wafer is not connected to the wafer carrier, so that the second wafer is accommodated. In the slot of the spacer; electrically connecting the wafer carrier, the first wafer, the spacer, and the first wafer with bonding wires; and forming a sealing gel on the wafer carrier to cover the first Wafers, spacers, dier wafers and fresh wires. 15. The manufacturing method according to item 14 of the scope of patent application, wherein the wafer carrier is a lead frame (1 e a d f r a in e). 16. The manufacturing method according to item 14 of the scope of patent application, wherein the wafer carrier is a printed circuit board. 17. The manufacturing method according to item 16 of the scope of patent application, wherein the printed circuit board is a build-up substrate. 18. The manufacturing method according to item 16 of the scope of patent application, wherein the printed circuit board is a laminated substrate (Laminated Substrate). _. The manufacturing method according to item 14 of the patent application scope, wherein the slot is through the partition plate. 20. The manufacturing method according to item 14 of the scope of patent application, wherein the area size of the spacer plate is smaller than that of the first wafer. 2 1. The manufacturing method of item 14 in the scope of patent application, wherein 17567 Shi Xipin. Ptd Page 22 200522294 VI. Scope of patent application The area size is smaller than this 2. Such as the first printed circuit board with patent application scope. 2 3. If the patent application scope is attached to the bearing surface 2 4. If the patent application scope is attached to the wafer carrier (bonding pad). 2 5. Slotting of spacers as in the scope of patent application. 14. The manufacturing method of item 14, wherein the spacer plate is 26 for the first wafer connection. If the first half of the scope of the patent application is connected to the first wafer, 27. At least one of the wafer-type wafer carrier On the first surface; at least a phase slotted spaced by the carrier; at least a second and connected to the first surface; at least a third method for manufacturing a plate-to-crystal crystal 14 item, wherein the wafer The carrier has a plurality of welding pads. The method according to item 14, wherein a plurality of bonding pads are provided on the opposite surface where the first wafer is not disposed. The method according to item 14, wherein the spacers are not provided with a plurality of bonding pads on the opposite surface. The method according to item 14, wherein a plurality of pads are provided on the surface of the second wafer. The conductor package includes: a carrier surface; a sheet connected to the carrier of the wafer carrier, connected to the first wafer and not on the surface of the wafer, and a sheet is provided on the spacer plate; Is located in the slot of the partition plate, and the opposite watch piece that the wafer is not connected to the wafer carrier is placed on the first surface; a piece is not connected to the first surface; 17567 石 夕 品 .ptd page 23 200522294 VI. The scope of the patent application is a plurality of bonding wires, which are used to electrically connect the chip carrier, the first chip, the spacer, the second chip and the third chip; and the packaging gel, It is formed on the wafer carrier to cover the first wafer, the spacer, the second wafer, the third wafer and the bonding wires. 28. The stacked chip semiconductor package according to item 27 of the patent application scope, wherein the chip carrier is a lead frame (1 e a d f r a m e). 29. The stacked chip semiconductor package according to item 27 of the patent application scope, wherein the wafer carrier is a printed circuit board. 30. If the stacked chip semiconductor package of item 29 in the patent application scope is repaired, the printed circuit board is a build-up substrate (B u i 1 d-u Substrate). 31. The stacked chip semiconductor package according to item 29 of the scope of patent application, wherein the printed circuit board is a laminated substrate (L aminated Substrate) o 3 2. The stack according to item 27 of the scope of patent application A chip semiconductor package, wherein the slot is formed through the spacer. 33. The stacked chip semiconductor package according to item 27 of the patent application scope, wherein the area size of the spacer is smaller than the first wafer. 34. The stacked chip semiconductor package according to item 27 of the patent application scope, wherein the area dimension of the second wafer is smaller than the slot of the spacer plate. 35. The stacked chip semiconductor package according to item 27 of the patent application scope, wherein the spacer is a printed circuit board. 3 6. If the stacked chip semiconductor package No. 27 of the patent application scope, 17567 碎 品 .ptd Page 24 200522294 6. Scope of patent application Among them, the wafer carrier has a plurality of bonding wires 焊 (finger) on its bearing surface. 37. The stacked wafer semiconductor package according to item 27 of the patent application scope, wherein a plurality of zinc rhenium (b ο n d i n g p a d) is provided on an opposite surface of the first wafer which is not connected with the wafer carrier. 38. The stacked chip semiconductor package according to item 27 of the patent application scope, wherein a plurality of bonding pads are provided on an opposite surface of the spacer plate not connected to the first wafer. 39. The stacked chip semiconductor package according to item 27 of the patent application scope, wherein a plurality of bonding pads are provided on a surface where the second wafer is not connected to the first wafer. 40. The stacked chip semiconductor package according to item 27 of the patent application scope, wherein a plurality of bonding pads are provided on a surface where the third wafer is not in contact with the second wafer. 4 1. A method for manufacturing a stacked wafer semiconductor package, comprising the following steps: preparing a wafer carrier having an attachment surface; placing at least one first wafer on an attachment table of the wafer carrier; Preparing at least one spacer plate, the spacer plate is provided with a slot, and the spacer plate is placed on the opposite surface of the first wafer not connected with the wafer carrier; preparing at least one second wafer And placing the second wafer on an opposite surface of the first wafer that is not connected to the wafer carrier, so that ] 7567 石 夕 品 .ptd Page 25 200522294 VI. Application scope The second wafer is accommodated in the slot of the spacer; at least one third wafer is prepared, and the third wafer is placed in the second The wafer is not on the opposite surface of the first wafer; the wafer carrier, the first wafer, the spacer, the second wafer and the second wafer are electrically connected with a bonding wire, and a package is formed on the wafer carrier. The colloid covers the first wafer, the spacer, the first wafer, the second wafer, and the fresh wire. 42. The manufacturing method according to item 41 of the scope of patent application, wherein the wafer carrier is a lead frame (1 e a d f r a m e). _. The manufacturing method according to item 41 of the scope of patent application, wherein the wafer carrier is a printed circuit board. 4 4. The manufacturing method according to item 43 of the scope of patent application, wherein the printed circuit board is a build-up substrate. 4 5. The manufacturing method according to item 43 of the scope of patent application, wherein the printed circuit board is a laminated substrate (Laminated Substrate). 46. The manufacturing method according to item 41 of the scope of patent application, wherein the slot is formed through the partition plate. 47. The manufacturing method according to item 41 of the scope of patent application, wherein the area size of the spacer plate is smaller than the first wafer. For example, the manufacturing method of item 41 in the scope of patent application, wherein the area dimension of the second wafer is smaller than the slot of the spacer plate. 49. The manufacturing method according to item 41 of the scope of patent application, wherein the spacer board is a printed circuit board. 50. The manufacturing method according to item 41 of the scope of patent application, wherein the wafer carrier 17567 Shi Xipin. Ptd Page 26 200522294 VI. The scope of patent application has a plurality of welding wires 塾 (f 1 n g e r) on the bearing surface. 51. The manufacturing method according to item 41 of the scope of patent application, wherein a plurality of bonding pads are provided on the opposite surface of the first wafer which is not connected with the wafer carrier. 5 2. The manufacturing method according to item 41 of the scope of patent application, wherein a plurality of bonding pads are provided on the opposite surface of the spacer plate not connected to the first wafer. 53. The manufacturing method according to item 41 of the scope of patent application, wherein a plurality of bonding pads are provided on a surface where the second wafer is not connected to the first wafer. 54. The manufacturing method according to item 41 of the scope of patent application, wherein a plurality of bonding pads are provided on a surface where the third wafer is not connected to the second wafer. 5 5. A stacked wafer semiconductor package comprising: a wafer carrier having a carrier surface; at least one first wafer connected to the carrier surface of the wafer carrier; at least one second wafer, On the opposite surface where the first wafer is not connected with the wafer carrier; at least one spacer plate is connected on the opposite surface where the second wafer is not connected with the first wafer, and the spacer plate The upper part is provided with a slot; at least one third chip is accommodated in the slot of the spacer plate, and is placed on the opposite surface of the second chip which is not connected with the first chip; a plurality of bonding wires, It is used to electrically connect the wafer carrier, the first wafer, the second wafer, the spacer and the second wafer, and 17567 Shi Xipin.ptd Page 27 200522294 VI. Scope of Patent Application The encapsulating gel is formed on the wafer carrier to cover the first wafer, the second wafer, the intermediate 1¾ board, the second wafer and the fresh wire. 56. The stacked chip semiconductor package according to item 55 of the patent application scope, wherein the chip carrier is a lead frame. 57. The stacked wafer semiconductor package according to item 55 of the patent application scope, wherein the wafer carrier is a printed circuit board. 58. The stacked chip semiconductor package according to item 57 of the scope of patent application, wherein the printed circuit board is a build-up substrate (Bui 1 d-up Substrate). The stacked chip semiconductor package, wherein the printed circuit board is a laminated substrate (L amina ΐ ed Substrate) ο 6 〇 As for the stacked chip semiconductor package No. 55 of the scope of patent application, wherein, the Slotting runs through the spacer. 61. The stacked wafer semiconductor package according to item 55 of the patent application scope, wherein the area size of the spacer is smaller than that of the second wafer. 62. The stacked wafer semiconductor package according to claim 55, wherein the area of the third wafer is smaller than the slot of the spacer. ft. A stack-type chip semiconductor package according to item 55 of the application, wherein 'the spacer is a printed circuit board. 64. The stacked chip semiconductor package according to claim 55, wherein the wafer carrier has a plurality of bonding wires on its bearing surface. 17567 碎 品 .ptd Page 28 200522294 VI. Application for patent scope 6 5. For example, for the stacked wafer semiconductor package with the scope of patent application No. 55, wherein the first wafer is not on the opposite surface of the wafer carrier The upper system is provided with a plurality of welding pads (b ο ndingpad). 66. The stacked chip semiconductor package according to item 55 of the patent application scope, wherein a plurality of bonding pads are provided on a surface on which the second wafer is not connected to the first wafer. 67. The stacked chip semiconductor package according to item 55 of the patent application scope, wherein a plurality of bonding pads are provided on an opposite surface of the spacer plate not connected to the second wafer. 68. The stacked chip semiconductor package according to item 55 of the patent application scope, wherein a plurality of bonding pads are provided on a surface where the third wafer is not connected to the second wafer. 6 9. A method for manufacturing a stacked wafer semiconductor package, comprising the following steps: preparing a wafer carrier having an attachment surface; placing at least one first wafer on the attachment surface of the wafer carrier Preparing at least one second wafer, and placing the second wafer on an opposite surface of the first wafer which is not connected to the wafer carrier, preparing at least one spacer plate, and an opening plate is provided on the spacer plate; And place the xuan spacer on the opposite surface where a wafer is not connected to the first wafer; prepare at least a third wafer, and place the third wafer on the second wafer On the opposite surface to the first wafer, so that the ] 7567 石 夕 品 .ptd Page 29 200522294 VI. Patent application scope The third chip is accommodated in the slot of the spacer; the wafer carrier, the first wafer, the second wafer, and the spacer are electrically connected by a bonding wire. A plate and a third wafer; and forming an encapsulating gel on the wafer carrier to cover the first wafer, the second wafer, the spacer, the third wafer and the bonding wire. 70. The manufacturing method according to item 69 of the patent application scope, wherein the wafer carrier is a lead frame (1 e a d f r a m e). 7 1. The manufacturing method according to item 69 of the patent application scope, wherein the wafer carrier is a printed circuit board. _. The manufacturing method according to item 71 of the scope of patent application, wherein the printed circuit board is a build-up substrate. 7 3. The manufacturing method according to item 71 of the scope of patent application, wherein the printed circuit board is a laminated substrate (Laminated Substrate). 74. The method according to item 69 of the scope of patent application, wherein the slot is formed through the partition plate. 75. The manufacturing method according to item 69 of the patent application scope, wherein the area size of the spacer plate is smaller than that of the second wafer. 76. The manufacturing method according to item 69 of the patent application scope, wherein the area size of the third wafer is smaller than the slot of the spacer plate. The manufacturing method according to item 69 of the patent application range, wherein the spacer board is a printed circuit board. 78. The manufacturing method according to item 69 of the scope of patent application, wherein the wafer carrier has a plurality of bonding wires 塾 (f i n g e r) on the bearing surface. 7 9. If the method of applying for the scope of item 69 of the patent, wherein the first wafer is not 17567 Shi Xipin.ptd Page 30 200522294 17567 Shi Xipin.ptd Page 31