TWI495071B - 具有穿透基板互連之半導體 - Google Patents

具有穿透基板互連之半導體 Download PDF

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TWI495071B
TWI495071B TW098117132A TW98117132A TWI495071B TW I495071 B TWI495071 B TW I495071B TW 098117132 A TW098117132 A TW 098117132A TW 98117132 A TW98117132 A TW 98117132A TW I495071 B TWI495071 B TW I495071B
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metal
metal wiring
forming
semiconductor device
conductive
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TW201005907A (en
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Kyle Kirby
Kunal Parekh
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Micron Technology Inc
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Description

具有穿透基板互連之半導體
本揭示案大體而言係關於半導體裝置。詳言之，本揭示案係關於半導體裝置中之導電互連。
在製造半導體裝置期間，使用一基底材料晶圓(諸如，晶態矽)來形成電組件。形成半導體裝置之製程步驟通常為添加或減去步驟。此等步驟可包括(但不限於)生長材料、沈積材料、植入離子、平坦化表面及蝕刻材料。在晶圓上執行此等製程，該晶圓接著經分割成獨立半導體晶粒。每一晶粒包括一作用表面或頂部表面(在該表面上執行該等製程步驟以形成電裝置)及一背部表面。
在分割之後，可封裝半導體晶粒以用於其他裝置(諸如，消費型電子產品)中。已使用若干方法來形成與半導體作用表面之電連接(諸如，線接合及球接合)。作為一實例，一種用於封裝半導體晶粒之過程包括：(a)在半導體晶圓上形成晶粒；(b)切割晶圓，以分離或分割晶粒；(c)將個別晶粒附著至插入式基板；(d)將晶粒之作用表面之導電接合襯墊線接合至插入式基板之端子；及(e)用合適模壓化合物囊封晶粒。
回應於針對給定佔據面積增加半導體裝置之密度的期望，半導體製造商已致力於開發將一或多個裝置堆疊於另一裝置之上之方式。已描述了用於將半導體晶粒電連接於一起之不同方法。此等方法可包括形成背側導電互連位置。在美國專利第6,582,992、6,903,443、6,962,867和7,091,124號中描述背側互連之一些實例。
舉例而言，第7,091,124號專利描述形成穿透一晶粒及該晶粒之作用表面上的一接合襯墊至該晶粒之一背側的導通孔或通路。第6,962,867號專利描述一種包括一或多個導通孔之半導體基板，該一或多個導通孔中形成有導電材料且自半導體基板之作用表面延伸至背部表面。一種描述於第6,903,443號專利中的用於製造半導體組件及互連之方法包括以下步驟：提供一基板(諸如，半導體晶粒)；藉由雷射鑽蝕穿透基板之導通孔，在基板之相對側上形成外部接觸；及在導通孔中形成導電部件。第6,582,992號專利描述形成於晶粒之邊緣上的充當用於堆疊晶粒封裝之層間導體之導電凹槽。
在大體上完成半導體處理之後形成導通孔可被稱為後導通孔製程。相比而言，已進行了一些開發工作以在整合處理之前形成導通孔，即先導通孔製程。舉例而言，在Kurita等人的「2007年電子組件及技術會議」(「2007 Electronic Components and Technology Conference」)第821-829頁之「A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology」中揭示了多晶矽導通孔製程。該論文描述使用高度摻雜多晶矽作為用於DRAM晶粒中之穿透矽導通孔之填充材料的先導通孔製程。在先導通孔製程中，在DRAM裝置製程之前進行矽基板蝕刻及填充。該論文指示，選擇多晶矽作為填充材料可防止在隨後之裝置製程中發生金屬原子污染及溫度限制。如該論文中所描述，蝕刻進入至矽基板中之一渠溝且該渠溝側壁與熱氧化物隔離。藉由化學氣相沈積(CVD)沈積多晶矽且使用化學機械研磨(CMP)平坦化矽表面以移除頂部表面處之過量層。接著在晶圓上進行DRAM裝置製程。
出於對彼等熟習此項技術者而言在閱讀並理解本說明書後將變得顯而易見之原因，在此項技術中需要為半導體裝置提供背側導電互連位置之替代方法及裝置。
在當前實施例之以下詳細描述中，參看隨附圖式，該等圖式形成本文之一部分且在其中以說明方式展示可實踐該等實施例之特定實施例。以足夠細節來描述此等實施例以使熟習此項技術者能夠實踐本發明，且應理解，可利用其他實施例，且可在不脫離本揭示案之範疇的情況下進行製程、化學或電改變。前文及以下描述中使用之術語晶圓及基板包括任何基底半導體結構。此外，當在以下描述中引用晶圓或基板時，可能已利用了先前製程步驟在基底半導體結構中形成區域/接面。此外，定向參考(例如，上部、下部、頂部、底部及側面)是彼此間相對的且不需要理解為絕對方向。以下詳細描述因此不以限制性意義來理解。
本揭示案描述將金屬導電互連併入至積體電路之製造過程中之半導體製程。如下文中較詳細解釋，該等製程允許在製造半導體期間形成填充有金屬之導通孔。在電晶體形成之後且在製造金屬佈線層之前形成並填充導通孔。藉由本發明所揭示之實施例達成了眾多益處，包括間距較緊密之導通孔的形成、比多晶矽互連低的電阻及至半導體製造操作中之改良型整合。
參看圖1中所說明之簡化半導體裝置100之橫截面表示，該半導體包括一前側102及一背側104。如熟習此項技術者已知，在基板108上及/或基板108中(通常在該半導體基板之頂側或作用側上)製造電子裝置106。如下文詳細描述，在半導體製造過程中，在形成一些電子裝置106(諸如，電晶體)之後但在製造一些金屬佈線層(metal routing layer)112及114之前的某時間，製造進入至基板108中之一金屬互連110。一些半導體裝置(諸如，動態隨機存取記憶體(DRAM))包括多個金屬佈線層。此等層通常被稱為金屬1至金屬N，其中金屬1為形成之第一金屬層。因為金屬互連在基板之作用區域116下方延伸，所以可藉由移除半導體裝置之背部表面118的一部分來接入該金屬互連。應注意，金屬互連110之頂部區域120終止於一位於金屬N層114之平面下方的水平面中。經由半導體基板108(在移除區118之後)暴露金屬互連之底部區域122，以提供穿透該基板之一電路徑。圖1之說明已經簡化而集中於金屬互連相對於佈線層之位置。熟習此項技術者將瞭解，半導體裝置包括本文中尚未說明或描述之額外電路及製程製造步驟。
參看圖2至圖14，描述根據本發明之實施例之整合過程。圖2說明製造於矽基板201上之製程中半導體裝置200之橫截面。該裝置包括具有閘極204及源極/汲極植入區域206之電晶體202。垂直接觸件210延伸穿透多個材料層(諸如，介電質層212、214、216及218)，以提供與源極/汲極植入區域206之電互連。出於理解本發明之目的，不需要電晶體、多個介電質層及接觸件之細節。此外，本發明並不限於特定半導體裝置。舉例而言，所說明之電晶體202為平面電晶體且本發明之實施例同等適用於具有垂直或三維電晶體之裝置中。在一項實施例中，半導體裝置為揮發性記憶體(諸如，動態隨機存取記憶體(DRAM))，且該等電晶體可為用於接入電荷儲存節點之接入電晶體(諸如，電容器(未說明))。
在形成電晶體之後的製造點處，將一低介電常數障壁及蝕刻終止薄膜220(諸如，來自Applied Materials,Inc.(Santa Clara,Ca.)之BLOkTM 材料)沈積於裝置之頂部表面上。參看圖3，使用熟知光阻製程來沈積、圖案化並選擇性移除光阻材料224，以提供一開口230。因為經圖案化之開口將用於形成導電導通孔，所以開口之幾何形狀並不重要。大體而言，自上方觀看之形狀(平面圖)可為圓形、橢圓形、方形、菱形、矩形或任何其他適當多邊形。
參見圖4，接著執行蝕刻製程以選擇性移除位於光阻224與矽基板201之間的材料層。參見圖5，亦經由蝕刻移除矽基板201之一部分，以形成進入至矽基板中之導通孔234。可以多個步驟完成該蝕刻操作。舉例而言，若在光阻224與矽201之間的中間層為氧化層，則可執行氧化蝕刻以暴露矽基板201，且接著可執行矽蝕刻。可使用任何合適蝕刻製程，包括(但不限於)：乾式蝕刻「Bosch」型式'穩定狀態型式、低溫矽蝕刻、雷射切除、粒子噴砂、濕式蝕刻及微放電機械加工。在一項實施例中，導通孔之橫截面寬度為大約10μm且矽蝕刻之深度在50μm與100μm之間。因而，在一些實施例中，可需要約5:1至10:1之縱橫比。然而，實際縱橫比將視正製造之特定半導體裝置而定。導通孔234延伸至矽基板中達低於基板之頂部之作用區域的深度。可將作用區域視為矽基板的含有電路特徵之區域(諸如，摻雜植入區域)及塊狀矽基板的為進行半導體裝置之適當操作所需之區域。
如圖6中所說明，移除光阻層224，且在移除光阻之後將氧化層240沈積於障壁層220上並至經蝕刻之導通孔234中。氧化層在待形成於導通孔中之金屬互連與矽基板201之間提供一介電質層或絕緣層。在氧化物240上形成一第二障壁層244(諸如，Ta、W、TiN或TiW或其他合適材料)且接著沈積一金屬晶種層250。在一項實施例中，該金屬晶種層為銅晶種層，而在另一實施例中，該晶種層為鎢或其他合適材料。出於描述本發明之目的，實施方式將描述一種將銅用作金屬之裝置。本文中所使用之術語金屬包括具有重疊導電帶及價能帶之材料，包括(但不限於)週期表中之金屬及其合金。熟習此項技術者獲益於當前描述將瞭解，本發明並不限於銅實施例。可使用諸如CVD(化學氣相沈積)、PVD(物理氣相沈積)、傳電(electro graphing)或電鍍之技術在障壁上形成晶種層。在一項實施例中，晶種層具有處於2k至6k埃之範圍中之一般厚度。
在沈積晶種層250之後，製造一電鍍遮罩252，如圖7中所說明。移除形成於經蝕刻之導通孔中之任何電鍍遮罩材料，以暴露導通孔234中之晶種層。可使用負光阻或正光阻來圖案化電鍍遮罩。咸信，可自導通孔更完全地移除負光阻材料。可將其他表面電鍍抑止劑用作電鍍遮罩。舉例而言，可使用壓印材料或濺鍍層(諸如，Ti)。
接著，執行一電鍍製程以用固體金屬254填充導通孔，如圖8中所展示。舉例而言，執行一銅電鍍製程以填充導通孔。在一項實施例中，使用一電化學沈積(ECD)電鍍製程。可使用其他電鍍製程及材料，諸如CVD、PVD、無電極(化學或自催化)、奈米粒子或導電聚合物。
視導通孔之縱橫比而定，電鍍製程可能需要經熟習此項技術者最佳化以避免及/或減少金屬中空隙之產生。應注意，電鍍遮罩層252將電鍍製程限制於暴露於導通孔中之晶種層。亦即，晶種層之在導通孔外之水平區域保持經選擇性地覆蓋，以防止電鍍。
參見圖9，在移除電鍍遮罩252之後，執行平坦化製程以移除垂直地延伸於介電質層240上方的受保護之晶種層250及經電鍍之金屬254。舉例而言，可執行一化學機械平坦化(CMP)操作，該操作停止於氧化層240上。在平坦化操作之後，可形成一可選覆蓋層260，如圖10中所說明。該覆蓋層可為用以防止金屬漂移之氧化層或另一障壁層。此覆蓋層尤其可用於幫助含有金屬254並避免污染後續處理操作中所使用之製造設備。舉例而言，已知銅係極易移動的且一旦製程設備暴露於銅，其未來使用便通常限制於使用銅之操作中。
在圖11中，多個操作經說明為在製程點處已完成。具體言之，藉由以下操作在裝置上執行鑲嵌製程：圖案化光阻(未圖示)；蝕刻以選擇性地暴露接觸件210；在經蝕刻之開口中形成一金屬1佈線層300；及將該金屬1層平坦化至覆蓋層260之平面。可使用第二晶種層來製造金屬1層。在此項實施例中，金屬互連254之頂部區域通常與金屬1層300處於同一水平面中。參看圖12，在形成金屬1層之後形成一介電質層310。接著，蝕刻該介電質層之部分以形成開口312，以暴露金屬1佈線層300及金屬互連254之接觸區域。與金屬1及金屬互連之接觸開口的大小、形狀及數目可基於積體電路裝置之需要而改變。如所說明，一項實施例可包括用於與金屬互連接觸之多個開口。
參看圖13，已形成金屬2佈線層320。應瞭解，為了形成金屬2層，形成一晶種層(未圖示)、電鍍該晶種層以填充形成於介電質層310中之凹口、並執行一平坦化操作以移除過量金屬。可將金屬互連254之頂部區域描述為處於低於金屬2層320之主水平面的水平面中。亦即，雖然金屬2層接觸金屬互連，但介電質區域使金屬2佈線層之主水平面與導體垂直地分離。
可在金屬2層上方執行額外製程步驟(未圖示)，包括形成額外介電質層及金屬佈線層。使用為熟習此項技術者已知之技術(諸如，藉由背面研磨)來薄化半導體基板，以暴露金屬互連254之下部區域340，見圖14。因此，已形成一半導體裝置，其具有一頂側及一背側。第一金屬層300位於頂側與背側之間，且第二金屬層320位於第一金屬層與頂側之間。金屬互連254穿透半導體裝置之部分垂直地延伸至背側，且金屬互連之頂部區域垂直地位於含有第二金屬層320之一水平面下方。
在一項實施例中，可藉由以下操作製造半導體裝置：蝕刻進入至半導體基板中之一導通孔；用一金屬材料填充該導通孔；在填充該導通孔之後，形成一金屬佈線層；及移除該半導體基板之底部的一部分，以暴露填充有金屬之導通孔之底部區域。其他實施例可包括製造一電晶體，該電晶體具有一閘極及延伸至矽基板之頂部區域中之源極/汲極植入區域。在該電晶體上方形成一介電質層，且接著形成穿透該介電質層並進入至矽基板中而與電晶體橫向相鄰之一導通孔。該導通孔垂直地延伸於電晶體之源極/汲極植入區域下方。在經蝕刻之導通孔中形成一第一介電質層，且接著在形成該第一介電質層之後形成一金屬晶種層。在晶種層之位於導通孔外之選定區域上方形成一阻擋層，且電鍍該晶種層的經暴露之區域以用金屬填充導通孔並形成一金屬插塞。移除該阻擋層及未經電鍍之晶種層，且在該金屬插塞上方形成一第二介電質層。接著在第二介電質區域上方形成一金屬佈線層，以使得該金屬佈線層經由該第二介電質層接觸該金屬插塞，以形成一電連接。
熟習此項技術者獲益於本揭示案將瞭解，可在不偏離本發明之情況下修改上文所描述之製程步驟。亦即，可進行製程整合改變以適應於製造商之設備、半導體裝置參數及製程相關問題。
參看圖15至圖16，說明替代實施例。在此等實施例中，使用用於形成金屬佈線層之鑲嵌製程能夠直接在金屬1層與金屬互連之間得到直接電接觸。舉例而言，如圖15中所展示，蝕刻操作暴露了金屬互連254並移除了在晶種層250之垂直側上的障壁層，以使得金屬1層410接觸該互連。在平坦化之後，金屬1層整體連接至金屬互連。或者，蝕刻操作可暴露金屬互連254並移除在該互連之垂直側及頂側上的障壁層，以使得金屬1層400在頂部表面上接觸互連254，見圖16。
本發明之替代實施例包括在形成金屬佈線層之後但在形成最終金屬佈線層之前形成金屬互連。此外，可在形成金屬層之間形成金屬互連。亦即，本發明並不限於一個金屬互連形成操作。
本發明之實施例並不限於兩個金屬佈線層。此外，可將金屬佈線層中之任何、一些或全部之一部分電連接至金屬互連。亦即，半導體裝置可包括各自經指定用於不同操作目的之數百個金屬互連。因此，互連之電路徑可能且極有可能將不同。
圖17說明一可包括球形接合襯墊位置510的再分布層500，其在暴露金屬互連254之後形成於半導體基板之背面 或底部上。該再分布層形成與互連之電接觸及實體接觸。用於薄化半導體晶圓並形成再分布層之製造過程為此項技術中熟知的。因而，本文未提供詳細描述。
雖然本文中已說明且描述了特定實施例，但一般熟習此項技術者將瞭解，經計劃以達成相同目的之任何配置可替代所展示之特定實施例。對於一般熟習此項技術者而言，本揭示案之許多調適將顯而易見。因此，本申請案意欲涵蓋本揭示案之任何調適或變化。
100‧‧‧半導體裝置
102‧‧‧前側
104‧‧‧背側
106‧‧‧電子裝置
108‧‧‧基板
110‧‧‧金屬互連
112‧‧‧金屬佈線層
114‧‧‧金屬佈線層
116‧‧‧作用區域
118‧‧‧半導體裝置之背部表面/區
120‧‧‧金屬互連之頂部區域
122‧‧‧金屬互連之底部區域
200‧‧‧半導體裝置
201‧‧‧矽基板
202‧‧‧電晶體
204‧‧‧閘極
206‧‧‧源極/汲極植入區域
210‧‧‧接觸件
212‧‧‧介電質層
214‧‧‧介電質層
216‧‧‧介電質層
218‧‧‧介電質層
220‧‧‧低介電常數障壁及蝕刻終止薄膜/障壁層
224‧‧‧光阻材料
230‧‧‧開口
234‧‧‧導通孔
240‧‧‧氧化層/氧化物/介電質層
244‧‧‧第二障壁層
250‧‧‧金屬晶種層
252‧‧‧電鍍遮罩/電鍍遮罩層
254‧‧‧金屬互連/固體金屬/經電鍍之金屬
260‧‧‧覆蓋層
300‧‧‧金屬1佈線層/第一金屬層
310‧‧‧介電質層
312‧‧‧開口
320‧‧‧金屬2佈線層/第二金屬層
340‧‧‧金屬互連254之下部區域
410‧‧‧金屬1層
500‧‧‧再分布層
510‧‧‧球形接合襯墊位置
圖1為根據本發明之一項實施例的簡化半導體裝置之部分橫截面表示；圖2至圖14為根據本發明之實施例的簡化製程中半導體之部分橫截面視圖；圖15至圖16為根據本發明之實施例的簡化製程中半導體之部分橫截面視圖；及圖17說明根據本發明之一實施例的具有一再分布層之簡化製程中半導體之部分橫截面視圖。
200．．．半導體裝置
201．．．矽基板
202．．．電晶體
204．．．閘極
206．．．源極/汲極植入區域
210．．．接觸件
212．．．介電質層
214．．．介電質層
216．．．介電質層
218．．．介電質層
220．．．低介電常數障壁及蝕刻終止薄膜/障壁層
240．．．氧化層/氧化物/介電質層
244．．．第二障壁層
250．．．金屬晶種層
254．．．金屬互連/固體金屬/經電鍍之金屬
260．．．覆蓋層
400．．．金屬1層

Claims (17)

  1. 一種具有一頂側及一背側之半導體裝置，其包含：一矽基板，其具有一頂部側及一底部側；一第一介電質結構，其鄰近於該矽基板之該頂部側；一第一金屬佈線結構，其位於該第一介電質結構處，該第一金屬佈線結構至少部分地位於該第一介電質結構中；一第二金屬佈線結構，其位於該第一金屬佈線結構與該半導體裝置之該頂側之間；一導電互連，其穿過該半導體裝置之一部分垂直延伸至該半導體裝置之該背側，其中該導電互連之一頂部區域係垂直地位於包含該第二金屬佈線結構之一水平平面的下方；一第二介電質結構，其至少具有大體對應於該第一金屬佈線結構的一第一開口、大體對應於一導電互連的一第二開口以及一第三開口；以及在該第一開口中的一第一導電部份、在該第二開口中的一第二導電部份以及在該第三開口中的該第二金屬佈線結構；其中該導電互連及該第一及第二金屬佈線結構並非同時形成。
  2. 如請求項1之半導體裝置，其中該第一金屬佈線結構與該導電互連形成一導電接觸。
  3. 如請求項1之半導體裝置，其中該第二金屬佈線結構與 該導電互連形成一導電接觸。
  4. 如請求項1之半導體裝置，其進一步包含形成於該半導體裝置之該背側上之一導電再分布層，其中該導電再分布層電耦接至該導電互連。
  5. 一種具有一頂側及一背側之半導體裝置，其包含：一矽基板，其具有一頂部側及一底部側；主動電路，其製造於該矽基板之該頂側上且包括：至少第一及第二金屬佈線結構，其中一第一金屬佈線結構係位於在該半導體裝置之該頂側及該背側之間的一第一介電質結構處，該第一金屬佈線結構係至少部分地位於該第一介電質結構中，且其中一第二金屬佈線結構係位於該第一金屬佈線結構與該半導體裝置之該頂側之間；一第二介電質結構，其至少具有大體對應於該第一金屬佈結構之一第一開口、大體對應於一導電互連之一第二開口以及一第三開口；一導電互連，其穿透該矽基板垂直地延伸至該半導體裝置之該背側，使得該第一及第二金屬佈線結構中之至少一者位於在該導電互連之一頂部區域上方的一水平平面中；一外部電互連，其在該矽基板之該底側處耦接至該導電互連；以及其中該導電互連及該第二及第二金屬佈線結構並非同時形成。
  6. 如請求項5之半導體裝置，其中該外部電互連包含形成於該矽基板之該底側上之一導電再分布層，其中該導電再分布層電耦接至該導電互連。
  7. 如請求項6之半導體裝置，其中該導電再分布層包含一導電球形接合襯墊。
  8. 如請求項5之半導體裝置，其中該導電互連具有一約5：1至10：1之長寬比。
  9. 如請求項5之半導體裝置，其中該第一及第二金屬佈線結構中之一者具有一與該導電互連之電連接。
  10. 一種製造一半導體裝置之方法，其包含：蝕刻進入至一半導體基板中之一導通孔：用一金屬材料填充該導通孔；在填充該導通孔之後，在該導通孔上方的一第一介電質結構處形成一第一金屬佈線結構，該第一金屬佈線結構至少部分地位於該第一介電質結構中；形成一第二金屬佈線結構；形成一第二介電質結構，其至少具有大體對應於該第一金屬佈線結構之一第一開口、大體對應於該導通孔之一第二開口以及大體對應於一第二金屬佈線結構之一第三開口；以及移除該半導體基板之一底部之一部分，以暴露該填充有金屬之導通孔之一底部區域。
  11. 如請求項10之方法，其中用一金屬材料填充該導通孔包含： 形成一金屬晶種層；選擇性地覆蓋該金屬晶種層之一部分，以使得位於該導通孔內之該金屬晶種層保持暴露；及電鍍該經暴露之金屬晶種層。
  12. 如請求項10之方法，其進一步包含在該半導體基板之該底部上形成一金屬再分布層，以使得在該填充有金屬之導通孔與該再分布層之間形成一電連接。
  13. 如請求項10之方法，其進一步包含形成一第二金屬佈線結構發生在形成該金屬佈線結構之後，其中該第二金屬佈線結構形成一與該填充有金屬之導通孔的電接觸。
  14. 一種製造一半導體裝置之方法，其包含：蝕刻進入至一半導體基板中之一導通孔：用一介電質層使該導通孔絕緣；用銅填充該經絕緣之導通孔；在填充該導通孔之後至少形成一第一金屬佈線結構及一第二金屬佈線結構，其中該第一金屬佈線結係位於在該導通孔上方之一第一介電質結構，該第一金屬佈線桔構係至少部分位於該第一介電質結構中；形成一第二介電質結構，其至少具有大體對應於該第一金屬佈線結構之一第一開口、大體對應於該導通孔之一第二開口以及大體對應於該第二金屬佈線結構之一第三開口，且其中該第一及第二金屬佈線結構中之至少一者與該填充有銅之導通孔形成一實體接觸；移除該半導體基板之一底部之一部分，以暴露該填充 有銅之導通孔之一底部區域；及在該半導體基板之該底部上形成一金屬再分布層，以使得在該經暴露的填充有銅之導通孔與該再分布層之間形成一實體接觸。
  15. 如請求項14之方法，其中用銅填充該導通孔包含：形成一銅晶種層；選擇性地覆蓋該銅晶種層之一部分，以使得位於該經絕緣之導通孔內的該銅晶種層保持暴露；及電鍍該經暴露之銅晶種層。
  16. 一種製造一半導體裝置之方法，其包含：製造一電晶體，該電晶體具有一閘極及延伸至一矽基板之一頂部區域中之源極/汲極植入區域；在該電晶體上方形成一第一介電質結構；形成穿透該第一介電質結構垂直地延伸至該電晶體之一接觸件；蝕刻穿透該第一介電質結構並進入至該矽基板中而與該電晶體橫向相鄰之一導通孔，其中該導通孔垂直地延伸於該源極/該汲極植入區域下方；在該經蝕刻之導通孔中形成一第二介電質結構；在該第二介電質結構之後形成一金屬晶種層；在該晶種層之位於該導通孔外之選定區域上方形成一阻擋層；電鍍該晶種層之經暴露之區域，以用金屬填充該導通孔並形成一金屬插塞； 移除該阻擋層及未經電鍍之晶種層；在該第二介電質結構上形成一第一金屬佈線結構，該第一金屬佈線桔構係至少部分地位於該第二介電質結構中；在該金屬插塞上方形成一第三介電質結構，該第三介電質結構具有大體對應於該第一金屬佈結構之一第一開口、大體對應於該金屬插塞之一第二開口以及一第三開口；在該第三介電質結構處形成一第二金屬佈線結構，以使得該第二金屬佈線結構經由該第三介電質結構接觸該金屬插塞，以形成一電連接；移除該矽基板之一底側之一部分，以暴露該金屬插塞之一底部；及在該矽基板之該底部上形成一金屬再分布層，以使得在該金屬插塞與該再分布層之間形成一電連接。
  17. 如請求項16之方法，其中該金屬插塞包含銅。
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