TWI481033B - 半導體裝置及其製造方法及鰭式場效電晶體裝置 - Google Patents
半導體裝置及其製造方法及鰭式場效電晶體裝置 Download PDFInfo
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Description
本發明係有關一種半導體裝置的製造方法，特別是一種鰭式場效電晶體裝置的製造方法。
為追求更高的裝置密度、較高的性能及較低的花費，半導體產業已進展至奈米科技製程節點。在進展的同時，製造及設計中的問題所造成的挑戰，導致了立體設計的發展，例如鰭式場效電晶體(finFET)裝置。常見的鰭式場效電晶體裝置是以一從基板延伸的薄鰭(或類似鰭的構造)來製作。鰭通常包括矽且形成電晶體裝置的主體。電晶體的通道形成於此垂直的鰭當中。提供一閘極於鰭上方(例如包圍鰭)。此類的閘極可提供較好的通道控制。鰭式場效電晶體裝置的其他優點包括減少的短通道效應及較高的電流。然而，對於傳統的鰭式場效電晶體裝置，高寄生電阻(parasitic resistance)可對鰭式場效電晶體裝置的汲極電流量造成不良影響。
因此，雖然目前製造鰭式場效電晶體裝置的方法對於預想的意圖來說通常都適當，但仍不能在各方面都令人滿意。
本發明係有關一種半導體裝置，包括：一半導體層，設置於一基板上方，其中該半導體層具有一鰭結構；一閘極結構，設置於該鰭結構上方，該閘極結構具有一閘極介電層及一閘極電極層，其中該閘極結構包圍該鰭結構的一部分；及源/汲極區域，設置於該鰭結構之中；其中一橫跨該鰭結構的摻雜輪廓為不均勻的，且其中該鰭結構被該閘極結構包圍的該部分之一第一區域比該鰭結構的其餘部分具有一較低的摻雜濃度。
本發明亦有關一種半導體裝置的製造方法，包括：形成一半導體層於一基板上；圖案化該半導體層使其成為一鰭結構；形成一閘極介電層及一閘極電極層於該鰭結構上方；圖案化該閘極介電層及該閘極電極層以形成一閘極結構，形成方式為使該閘極結構包圍該鰭結構的一部分；及實施複數個植入製程以在該鰭結構中形成源/汲極區域，該複數個植入製程的實施方法為使一橫跨該鰭結構的摻雜輪廓為不均勻的，且其中該鰭結構被該閘極結構包圍的該部分之一第一區域比該鰭結構的其餘部分具有一較低的摻雜濃度。
本發明更有關一種鰭式場效電晶體裝置，包括：一鰭結構，形成於一基板上方，該基板包括下列其中之一：一矽材料及一絕緣材料；一閘極，其形成方式為至少部分包圍該鰭結構的一段；及源/汲極區域，形成於該鰭結構之中；其中：該鰭結構包括一第一部分、一第二部分及一第三部分；該第一部分完全被該閘極包圍；該第二部分至少部分被該閘極包圍且起比該第一部分具有一較高的摻雜濃度；及該第三部分不被該閘極包圍且比起該第二部分具有一較高的摻雜濃度。
可理解的是，以下的揭露提供許多不同的實施例或範例以實施本發明不同的特徵。將在以下敘述元件及設置的特定範例以簡化本揭露，但僅為範例且不據限定性。例如在以下敘述中，第一特徵於第二特徵上或上方之形成可包括具有額外特徵形成於第一、第二特徵之間的實施例，使第一、第二特徵可不直接接觸。另外，本揭露可在各類範例中重複元件編號及/或字母。如此的重複是為了簡明起見，且不表示所討論的各類實施例及/或設置之間有關係。再者，為簡明起見，各類特徵可被畫成任意尺寸。
根據於本發明不同層面，第1圖為鰭式場效電晶體裝置的製造方法10之流程圖。方法10始於步驟12，其中一半導體層形成於一基板上。方法10繼續進行步驟14，其中圖案化半導體層使其具有一鰭結構。方法10繼續進行步驟16，其中一閘極介電層及一閘極電極層形成於鰭結構上方。方法10繼續進行步驟18，其中圖案化閘極介電層及閘極電極層使閘極結構包圍鰭結構的一部分。方法10繼續進行步驟20，其中實施複數個植入製程以形成源/汲極區域於鰭結構中、閘極結構的任一側。複數個植入製程的實施方式使得橫跨鰭結構的摻雜輪廓(doping profile)為不均勻(non-uniform)的。比起鰭結構的其餘部分，位於閘極結構正下方的鰭結構的一部分具有一較低的摻雜濃度。
鰭式場效電晶體裝置的使用在半導體產業越來越受歡迎。參見第2圖，其為一範例鰭式場效電晶體裝置50的透視示意圖。鰭式場效電晶體裝置50為一建於基板上的非平面多閘極電晶體(non-planar multi-gate transistor)。一類似鰭的薄矽結構(稱為鰭)形成鰭式場效電晶體裝置50的主體。鰭式場效電晶體裝置50的閘極60包圍此鰭。Lg表示閘極60的一長度(或寬度，視其觀點而定)。鰭式場效電晶體裝置50的源極70及汲極80形成在鰭狀物位於閘極60兩側的延伸部分。鰭本身當作一通道。鰭式場效電晶體裝置50有效的通道長度取決於鰭的大小。
相較於傳統的金氧半場效電晶體(也被稱作平面裝置)，鰭式場效電晶體裝置提供數個優點。這些優點可包括較高的晶片面積效率、增進的載子流動性及可使用與平面裝置製程相容的製程。因此，較佳可在積體電路晶片的設計中，於整個或一部分的積體電路晶片使用鰭式場效電晶體裝置。
然而，傳統鰭式場效電晶體裝置可具有均勻的通道輪廓並且因此可具有高寄生電阻的問題，其可對汲極80電流大小造成不良影響。在此，本發明的各層面包括形成一具有不均勻通道輪廓及因此降低的寄生電阻。因此，根據本發明製造的鰭式場效電晶體裝置具有增進的汲極電流。以下的示意圖顯示一鰭式場效電晶體裝置在製程中不同階段之各類剖面圖及上視圖。為清楚說明起見，第2圖所示的立體軸X、Y、Z對應於之後示意圖的軸。X、Y、Z軸也可分別被稱為X、Y、Z方向。
參見第3A、3B、3C圖，第3A圖為一鰭式場效電晶體裝置100在Y-Z平面的剖面示意圖，第3B圖為一鰭式場效電晶體裝置100在X-Z平面的剖面示意圖，第3C圖為一鰭式場效電晶體裝置100在X-Y平面的上視示意圖。鰭式場效電晶體裝置100具有基板110。在一實施例中，基板110具有一介電材料，例如二氧化矽。基板110具有厚度120。在一實施例中，厚度120約為4-30 nm。
半導體層130形成於基板110上。在一實施例中，半導體層130具有一結晶矽材料。應理解的是，在其他實施例中，半導體層130可包括其他合適材料。實施一植入製程140於半導體層130上以植入複數個摻雜離子至半導體層130。在一實施例中，摻雜離子包括一n型材料，例如As或P。在實施植入製程140後，摻雜濃度約為1x1017
至5x109
離子/立方公分(ions/cm3
)。在其他實施例中，摻雜離子可包括一p型材料，例如B，且摻雜濃度可為不同。
參見第4A-4C圖，圖案化半導體層130形成一鰭結構150。鰭結構150以伸長的形狀沿著X方向延伸，如第4B、4C圖所示。如前述，鰭結構150當作鰭式場效電晶體裝置100的導電通道。鰭結構150在Y方向上具有一鰭寬度160。在一實施例中，鰭寬度160約為2-15 nm。
參見第5A-5C圖，形成閘極介電層170於鰭結構150周圍，而閘極電極層180形成於閘極介電層170之上。閘極介電層170及閘極電極層180可個別利用一本技藝已知製程例如化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、上述組合或另一合適製程來形成。在一實施例中，閘極介電層170包括一HfO2
材料且具有約為1-3 nm的厚度(以Z方向測量)。在一實施例中，閘極電極層180包括一TiN材料且具有約為1-20 nm的厚度(以Z方向測量)。
參見第6A-6C圖，圖案化閘極電極層180及閘極介電層170以形成一閘極結構200。閘極結構200以伸長的形狀沿著Y方向延伸，如第6A、6C圖所示。閘極結構200包圍鰭結構150的一部分。根據於一實施例，鰭結構150被閘極結構200包圍的部分構成一導電通道區域205。閘極結構200在X方向具有一寬度210，如第6A、6C圖所示。在一實施例中，寬度210約為2-15 nm。
閘極結構200形成之後，實施一植入製程220以植入摻雜離子於鰭結構150(圖案化之半導體層130)位於閘極結構200任一側或兩側上的部分，由此形成源/汲極區域230、231。摻雜離子與植入製程140中使用的摻雜離子具有同樣的摻雜電性。舉例來說，在植入製程140使用n型摻雜離子的實施例中，植入製程220也同樣使用n型摻雜離子。在一實施例中，植入製程220比起植入製程140具有較高的摻雜濃度，且因此源/汲極區域230、231的摻雜濃度高於通道區域205(閘極結構200包圍的鰭結構150的部分)。在一實施例中，源/汲極區域230、231的摻雜濃度約為1x1018
-1x1020
離子/立方公分(ions/cm3
)。
參見第7A-7C圖，閘極間隙物240、241包圍閘極結構200的長邊形成。也就是說，閘極間隙物240、241以伸長的方式沿著Y方向延伸。源/汲極區域230、231可藉由在閘極結構200上沉積間隙物材料，且在之後於間隙物材料上實施一圖案化製程(例如一蝕刻製程)。間隙物材料可包括介電材料。在一實施例中，間隙物材料包括氧化矽或氮化矽。閘極間隙物240、241分別在X方向具有一寬度250。在一實施例中，寬度250約為2-20nm。
在形成閘極間隙物240、241之後，實施一植入製程260以植入摻雜離子於鰭結構150未被間隙物240、241或閘極結構200覆蓋的部分中。植入製程260為源/汲極區域230、231的形成製程中的一部分。摻雜離子具有與植入製程140、220中所使用之摻雜離子同樣的電性。舉例來說，在植入製程140、220使用n型摻雜離子的實施例中，植入製程260也同樣使用n型摻雜離子。在一實施例中，植入製程260比起植入製程220具有較高的摻雜濃度，且因此源/汲極區域230、231不位於閘極間隙物240、241下方的部分的摻雜濃度高於源/汲極區域230、231位於閘極間隙物240、241下方的部分的摻雜濃度。在一實施例中，源/汲極區域230、231不被閘極結構200或閘極間隙物240、241覆蓋的部分的摻雜濃度約為1x1020
-1x1021
離子/立方公分。
可理解的是，在另一實施例中，磊晶成長製程可取代植入製程260。再者，可接著實施一活化退火製程，其中可具有約為900-1050℃的溫度且少於約1秒。
根據上述討論，可知鰭結構150具有一不均勻的摻雜輪廓。因為上述各類的植入製程，摻雜濃度隨著更接近位於閘極結構200正下方的中心而下降(雖然不一定是
線性下降)。為提供一更清楚的說明，第8圖提供一更詳細的第7B圖的剖面示意圖(於X-Z平面)。
參見第8圖，鰭結構150包括三個分別標示為N0、N1、N2的區域。N0區域位於閘極結構200中心下方且具有最低的摻雜濃度。N1區域包括兩部分且位於N0區域的相反側。N1區域比N0區域具有較高的摻雜濃度。在一些實施例中，N1區域包括輕源/汲極(LDD)區域。N2區域包括兩部分且位於N1區域的相反側。N2區域比N0、N1區域具有較高的摻雜濃度。在一些實施例中，N2區域包括源/汲極(S/D)區域。應注意的是N0、N1、N2區域可不完全與閘極結構200的側壁或閘極間隙物240、241的邊角對齊。舉例來說，N2區域可延伸於閘極間隙物240、241下方，而N1區域可延伸於閘極介電層170下方。
N0區域具有一寬度270，N1區域具有一寬度280，而N1區域具有一與閘極結構200重疊的距離290。寬度270、280及距離290皆為在X方向測量所得。在一實施例中，寬度270約為閘極結構200的寬度210的1/4-7/8(同樣顯示於第6B、6C圖中)。在一實施例中，距離290約為閘極結構200的寬度210的1/16-3/8。可理解的是，重疊距離290與電晶體的臨界電壓Vt
相關。隨著距離290改變，臨界電壓Vt
也會改變。在這種方式下，臨界電壓Vt
為可調變的。
在一實施例中，N0區域的摻雜濃度小於約2x1018
離子/立方公分。在一實施例中，N1區域的摻雜濃度大於約1x1019
離子/立方公分。在一實施例中，N2區域的摻雜濃度大於約1x1020
離子/立方公分。
根據本揭露的各層面所實施的互補式金氧半導體裝置可在同樣的晶片上具有n-FET及p-FET。對於n-FET，閘極結構的功函數接近導電帶邊緣。對於p-FET，閘極結構的功函數接近價帶邊緣。
第9圖為鰭結構150不同區域的摻雜濃度變化圖表300。圖表300為一摻雜濃度(Y軸)相對於位置(X軸)的圖表。應注意的是，接下來圖式中摻雜濃度的Y軸將不同於之前討論的Y方向。測量摻雜濃度是以離子/立方公分為單位。測量位置是以奈米為單位。閘極結構200的中心(第8圖)具有位置0。閘極結構200中心的左邊區域具有負單位，而閘極結構200中心的右邊區域具有正單位。如圖表300所示，摻雜濃度隨著位置越來越靠近閘極結構200的中心而減少，且隨著遠離閘極結構200的中心而增加。
第9圖中也顯示了上述N0、N1、N2大致的邊界，並以虛線表示。在此所示的實施例中，可看到N0區域的摻雜濃度在三個區域中為最低的，且為7.3x1017
離子/立方公分或更低；N2區域的摻雜濃度在三個區域中為最高的，且為7.7x1019
離子/立方公分或更高；N1區域的摻雜濃度介於三個地區摻雜濃度的中間，且為7.3x1017
-7.7x1019
離子/立方公分。同樣地，第9圖顯示在此討論的鰭式場效電晶體裝置的不均勻的摻雜輪廓。
雖然摻雜濃度改變，摻雜離子電性在N0、N1、N2區域中皆相同。在一實施例中，N0、N1、N2區域皆為n型摻雜。在另一實施例中，N0、N1、N2區域皆為p型摻雜。
鰭式場效電晶體裝置的閘極長度Lg同樣顯示於第9圖中。在一實施例中，閘極長度Lg與閘極結構200的寬度210(如第8圖所示)相等。如第9圖所示，閘極長度Lg延伸超過N0區域且進入N1區域。此也與第8圖中所示的一致。
第3-8圖顯示一鰭式場效電晶體裝置的製造方法的流程圖，其利用一覆矽絕緣體(silicon-on-insulator,SOI)方法。第10-14圖為根據一替代實施例中製造的鰭式場效電晶體裝置100A各類剖面圖及上視圖，在此實施例中，包括利用一塊狀矽而非覆矽絕緣體方法。為求清楚一致，在第10-14圖中，與第3-8圖中相似的元件將具有與第3-8圖中相似元件一樣的元件標號。
參見第10A-10C圖，半導體層130形成於基板110上。在此，基板110A包括一摻雜矽材料(doped silicon material)而非一介電材料，例如一p型摻雜矽材料。基板110A的摻雜電性與半導體層130的摻雜電性相反。基板110A在一n-FET裝置中為一p型基板，而在一p-FET裝置中為一n型基板。
參見第11A-11C圖，圖案化半導體層130使其成為一伸長的鰭結構150。不同於先前第4圖所示之實施例，此圖案化製程也移除了基板110A的一部分，如第11A圖所示。在此之後，一絕緣材料400形成於鰭結構150兩側上基板110A被移除的部分的位置。絕緣材料400可包括一介電材料，例如一氧化矽材料。
參見第12A-12C圖，閘極電極層180及閘極介電層170形成於鰭結構150上方。參見第13A-13C圖，圖案化閘極電極層180及閘極介電層170以形成閘極結構200。閘極結構200包圍鰭結構150。在形成閘極結構200之後，實施一植入製程220以形成源/汲極區域230、231。參見第14A-14C圖，閘極間隙物240、241形成於閘極結構200長側的周圍。接著，實施植入製程260以進一步定義源/汲極區域230、231。可在之後實施一活化退火製程。如上述有關第3-8圖的實施例，第10-14圖所示的實施例也具有類似第9圖中所示的不均勻的摻雜輪廓。
第15圖包括數個圖表330-332，其為根據於本揭露各層面的功函數及通道劑量最佳化的說明示意圖。在一實施例中，一在Ion
(通電電流或汲極電流)及Ioff
(斷電電流或漏電流)之間的最佳化點(optimized point)具有一約為0至-2x1019
的相關通道劑量。
以下的表1列出本揭露的一些實施例與其他裝置之間的不同。這些其他裝置可包括傳統的鰭式場效電晶體裝置或傳統的無接面電晶體(junction-less transistors)及改良的無接面電晶體。可理解的是，表1的不同僅為範例且不具有限定性。可有額外的相異之處，但為了簡明起見，並未在表1列出。
根據表1，本揭露的一些實施例具有：
- 一n型功函數約為4.1-4.65 V；
- 一n型通道具有一低摻雜濃度；
- 一n型LDD區域，其比起通道具有一較高的摻雜濃度；及
- 一n型S/D區域，其比起LDD區域具有一較高的摻雜濃度。
任何其他裝置皆不具有以上性質的組合。舉例來說，傳統鰭式場效電晶體裝置具有一相反電性摻雜的通道，而傳統無接面電晶體具有比起在此的實施例較高的摻雜濃度，及一未被摻雜的LDD區域。可參見上面的表1以找到其他的相異之處。
第16圖為另一圖表350，其顯示根據於本發明實施例之裝置相對於上述表1所列出的其他裝置的Ion
及Ioff
的表現。圖表350包括複數個抽樣點，其中一些抽樣點表示本揭露之實施例的Ion
及Ioff
的表現，而其他抽樣點表示其他裝置Ion
及Ioff
的表現。舉例來說，抽樣點500及501代表本揭露的實施例，而抽樣點410及411代表其他裝置。可看到抽樣點500及501比起抽樣點410及411具有較好的Ion
及Ioff
表現。換句話說，抽樣點500及501具有好的Ion
電流且仍能維持低的漏電流(Ioff
電流)。
應理解的是，雖然上面討論的圖示僅顯示單個鰭式場效電晶體裝置，然而，可於單個晶圓或晶片上製造複數個類似的鰭式場效電晶體裝置。例如，一互補式金氧半導體包括n-FET裝置及p-FET裝置。n-FET裝置及p-FET裝置皆可以上述製程流程製造。在一實施例中，一n-FET裝置的閘極的功函數較接近一導電帶邊緣，而一p-FET裝置的閘極的功函數較接近一價帶邊緣。
在此敘述的本揭露的各實施例提供數個優點，應理解的是其他實施例可提供其他優點，而任一實施例並不一定要具有特定的優點。具有不均勻的橫跨鰭式場效電晶體裝置150的摻雜輪廓的一優點是降低的寄生電阻，因此比傳統裝置具有更高的汲極電流。在一些實施例中，汲極電流可增加至少20%，而在同時漏電流及通道劑量與傳統裝置相當。
本揭露更廣義的形式包括一種半導體裝置。半導體裝置包括：一半導體層，設置於一基板上方，其中半導體層具有一鰭結構；一閘極結構，設置於鰭結構上方，閘極結構具有一閘極介電層及一閘極電極層，其中閘極結構包圍鰭結構的一部分周圍；及源/汲極區域，設置於
鰭結構之中；其中一橫跨鰭結構的摻雜輪廓為不均勻的，且其中鰭結構被閘極結構包圍的部分之一第一區域比鰭結構的其餘部分具有一較低的摻雜濃度。
本揭露另一廣義的形式包括一鰭式場效電晶體裝置。鰭式場效電晶體裝置包括：一鰭結構，形成於一基板上方，基板包括下列其中之一：一矽材料及一絕緣材料；一閘極，其形成方式為至少部分包圍鰭結構的一段；及源/汲極區域，形成於鰭結構之中；其中：鰭結構包括一第一部分、一第二部分及一第三部分；第一部分完全被閘極包圍；該第二部分至少部分被閘極包圍且起比第一部分具有一較高的摻雜濃度；及第三部分不被閘極包圍且比起第二部分具有一較高的摻雜濃度。
而本發明又一廣義的形式包括一半導體裝置的製造方法。製造方法包括：形成一半導體層於一基板上；圖案化半導體層使其成為一鰭結構；形成一閘極介電層及一閘極電極層於鰭結構上方；圖案化閘極介電層及閘極電極層以形成一閘極結構，形成方式為使閘極結構包圍鰭結構的一部分；及實施複數個植入製程以在鰭結構中形成源/汲極區域，複數個植入製程的實施方法為使一橫跨鰭結構的摻雜輪廓為不均勻的，且其中鰭結構被閘極結構包圍的部分之一第一區域比鰭結構的其餘部分具有一較低的摻雜濃度。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更
動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧製造方法
12、14、16、18、20‧‧‧步驟
50、100‧‧‧鰭式場效電晶體裝置
60‧‧‧閘極
Lg‧‧‧閘極60的一長度
80‧‧‧汲極
X、Y、Z‧‧‧軸或方向
110、110A‧‧‧基板
120‧‧‧厚度
130‧‧‧半導體層
140、220、260‧‧‧植入製程
150‧‧‧鰭結構
160‧‧‧鰭寬度
170‧‧‧閘極介電層
180‧‧‧閘極電極層
200‧‧‧閘極結構
205‧‧‧導電通道區域
230、231‧‧‧源/汲極區域
240、241‧‧‧閘極間隙物
210、250、270、280‧‧‧寬度
290‧‧‧距離
N0、N1、N2‧‧‧區域
300、350‧‧‧圖表
400‧‧‧絕緣材料
500、501、410、411‧‧‧抽樣點
第1圖為根據於本揭露一些層面的一鰭式場效電晶體裝置的製造方法之流程圖。
第2圖為一範例鰭式場效電晶體裝置50的透視示意圖。
第3A~3C、4A~4C、5A~5C、6A~6C、7A~7C、8圖為根據於本揭露一實施例之鰭式場效電晶體裝置在不同製程階段的局部剖面圖及上視示意圖。
第9圖為一摻雜濃度相對於位置的圖表。
第10A~10C、11A~11C、12A~12C、13A~13C、14A~14C圖為根據於本揭露另一實施例之鰭式場效電晶體裝置在不同製程階段的局部剖面圖及上視示意圖。
第15A~15C圖包括數個說明功函數及通道劑量最佳化的圖表。
第16圖包括一根據於一實施例說明一裝置Ion
及Ioff
的表現的圖表。
Lg．．．閘極60的一長度
300．．．圖表
N0、N1、N2．．．區域
X、Y．．．軸或方向
Claims (7)
- 一種半導體裝置，包括：一半導體層，設置於一基板上方，其中該半導體層具有一鰭結構；一閘極結構，設置於該鰭結構上方，該閘極結構具有一閘極介電層及一閘極電極層，其中該閘極結構包圍該鰭結構的一部分；及源/汲極區域，設置於該鰭結構之中；其中一橫跨該鰭結構的摻雜輪廓為不均勻的，且其中該鰭結構被該閘極結構包圍的該部分之一第一區域比該鰭結構的其餘部分具有一較低的摻雜濃度，其中該鰭結構包括該第一區域、一第二區域及一第三區域，且其中：該第一區域具有一第一摻雜濃度；該第二區域鄰近該第一區域且部分被該閘極結構包圍且具有一比該第一摻雜濃度更高的第二摻雜濃度；及該第三部分鄰近該第二區域但不被該閘極結構包圍且具有一比該第二摻雜濃度更高的第三摻雜濃度，及其中該第一、第二及第三區域皆具有同樣的摻雜電性，其中該第一區域與該第二區域接觸，該第二區域與該第三區域接觸，及其中於該鰭結構內，該第二區域具有一均勻之第二摻雜濃度，其自該閘極結構下方側向延伸至該閘極結構之一側壁上之一閘極間隙物下方，該第三區域具有一均 勻之第三摻雜濃度，其自該閘極間隙物下方以遠離該閘極結構方向側向延伸超過該閘極間隙物之外緣。
- 如申請專利範圍第1項所述之半導體裝置，其中該第一區域及該閘極結構分別具有於同方向延伸的第一及第二側面尺寸，且其中該第一側面尺寸約為該第二側面尺寸的1/4到7/8。
- 如申請專利範圍第1項所述之半導體裝置，其中該基板為(i)一絕緣基板；或(ii)一塊狀矽基板，且其中該塊狀矽基板及該半導體層具有相反摻雜電性。
- 一種鰭式場效電晶體裝置，包括：一鰭結構，形成於一基板上方，該基板包括下列其中之一：一矽材料及一絕緣材料；一閘極，其形成方式為至少部分包圍該鰭結構的一段；及源/汲極區域，形成於該鰭結構之中；其中：該鰭結構包括一第一部分、一第二部分及一第三部分；該第一部分完全被該閘極包圍；該第二部分至少部分被該閘極包圍且起比該第一部分具有一較高的摻雜濃度；及該第三部分不被該閘極包圍且比起該第二部分具有一較高的摻雜濃度，及其中該第一、第二及第三區域皆具有同樣的摻雜電性， 其中該第一區域與該第二區域接觸，該第二區域與該第三區域接觸，及其中於該鰭結構內，該第二區域具有一均勻之第二摻雜濃度，其自該閘極下方側向延伸至該閘極之一側壁上之一閘極間隙物下方，該第三區域具有一均勻之第三摻雜濃度，其自該閘極間隙物下方以遠離該閘極方向側向延伸超過該閘極間隙物之外緣。
- 如申請專利範圍第4項所述之鰭式場效電晶體裝置，其中：該第二部分設置於該第一部分及該第三部分之間。
- 一種半導體裝置的製造方法，包括：形成一半導體層於一基板上；圖案化該半導體層使其成為一鰭結構；形成一閘極介電層及一閘極電極層於該鰭結構上方；圖案化該閘極介電層及該閘極電極層以形成一閘極結構，形成方式為使該閘極結構包圍該鰭結構的一部分；及實施複數個植入製程以在該鰭結構中形成源/汲極區域，該複數個植入製程的實施方法為使一橫跨該鰭結構的摻雜輪廓為不均勻的，且其中該鰭結構被該閘極結構包圍的該部分之一第一區域比該鰭結構的其餘部分具有一較低的摻雜濃度，其中該鰭結構包括該第一區域、一第二區域及一第三區域，且其中： 該第一區域具有一第一摻雜濃度；該第二區域鄰近該第一區域且部分被該閘極結構包圍且具有一比該第一摻雜濃度更高的第二摻雜濃度；及該第三部分鄰近該第二區域但不被該閘極結構包圍且具有一比該第二摻雜濃度更高的第三摻雜濃度，及其中該第一、第二及第三區域皆具有同樣的摻雜電性，其中該第一區域與該第二區域接觸，該第二區域與該第三區域接觸，及其中於該鰭結構內，該第二區域具有一均勻之第二摻雜濃度，其自該閘極結構下方側向延伸至該閘極結構之一側壁上之一閘極間隙物下方，該第三區域具有一均勻之第三摻雜濃度，其自該閘極間隙物下方以遠離該閘極結構方向側向延伸超過該閘極間隙物之外緣。
- 如申請專利範圍第6項所述之半導體裝置的製造方法，其中該第一區域及該閘極結構各具有於同方向延伸的第一及第二側面尺寸，且其中該第一側面尺寸約為該第二側面尺寸的1/4到7/8。
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| CN102610642B (zh) | 2016-03-30 |
| US20140011748A1 (en) | 2014-01-09 |
| US20120187486A1 (en) | 2012-07-26 |
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| US8916444B2 (en) | 2014-12-23 |
| US8487378B2 (en) | 2013-07-16 |
| US20140024182A1 (en) | 2014-01-23 |
| TW201232780A (en) | 2012-08-01 |
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