TWI476875B - 形成具有無芯封裝之功能化載子結構的技術 - Google Patents

形成具有無芯封裝之功能化載子結構的技術 Download PDF

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TWI476875B
TWI476875B TW100112019A TW100112019A TWI476875B TW I476875 B TWI476875 B TW I476875B TW 100112019 A TW100112019 A TW 100112019A TW 100112019 A TW100112019 A TW 100112019A TW I476875 B TWI476875 B TW I476875B
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die
coreless
carrier
top surface
carrier material
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TW100112019A
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TW201208011A (en
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Ravi K Nalla
John S Guzek
Javier Soto Gonzalez
Drew W Delaney
Hamid R Azimi
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Intel Corp
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Description

形成具有無芯封裝之功能化載子結構的技術
本發明係有關形成具有無芯封裝之功能化載子結構的技術。
隨著半導體技術進步到更高處理器性能，封裝架構中的進步可包括無芯無凸塊增建層(BBUL-C)封裝架構及其他這種組裝件。BBUL-C封裝的目前程序流程涉及在蓋有銅箔之暫時芯/載子上建立基板，並將芯與封裝分離之後蝕刻掉銅箔。
 【發明內容及實施方式】
在下列詳細說明中，參照附圖，其例示性顯示可實行方法的特定實施例。以足夠細節敘述這些實施例使熟悉此技藝人士得以實行實施例。應了解到各種實施例，雖不同，但不一定為互斥。例如，在此所述之特定特徵、結構、或特性可在其他實施例內加以實行而不脫離本發明之精神及範疇。另外，了解到可修改在每一揭露實施例內之個別元件的位置或配置而不脫離本發明之精神及範疇。因此，不應限制性解釋下列詳細說明，且僅由所附之申請專利範圍，連同申請專利範圍應得的完整等效範圍，適當解釋地，界定實施例之範疇。在圖中，類似符號意指在所有這些圖中相同或類似的功能。
敘述形成並利用微電子結構(如封裝結構)的方法及關聯之結構。那些方法可包括附接晶粒到載子材料，其中載子材料包含藉由止蝕刻層分離的頂層及底層；在該晶粒旁形成介電質材料；藉由在該介電質材料上增建諸層來形成無芯基板；以及接著從該底層載子材料移除頂層載子材料及止蝕刻層。實施例之方法致能載子材料之功能化以產生功能化載子結構，例如，如EMI屏蔽、加強件、散熱器、電感器、及PoP島狀結構。
第1a至1h圖繪示形成例如微電子結構(如封裝結構)之方法的實施例。第1a圖描繪載子材料100及100’。在一實施例中，載子材料100可包含多層銅箔，其充當載子，如微電子晶粒載子。在其他實施例中，載子材料可包含任何適合的導電載子材料100。在一實施例中，載子材料100可包含兩層，頂層100及底層100’，如所示，但在其他實施例中可包含一層或多於兩層。
在一實施例中，載子材料100可包含兩層的導電材料，諸如但不限於，銅，例如，其可藉由薄蝕刻阻障(停止)層102分離。在一實施例中，止蝕刻層102可包含如鎳之這種材料，但可包含可用來包含止蝕刻層以促進載子層之間的蝕刻停止之任何這種材料。在一實施例中，止蝕刻層102可例如用來輔助凹部104(第1b圖)的形成，尤其在蝕刻程序期間。在一實施例中，可由在後續組裝步驟期間嵌入載子材料100’內之晶粒的厚度及嵌入深度來決定底載子材料層100’之厚度103。
可在載子材料的一層中形成凹部104，如藉由移除底載子材料層100’的一部分。可利用任何適當的移除程序，如蝕刻程序，如此技藝中已知者，來形成凹部104。例如，可在載子材料100’之底層上層壓一遮罩材料，並可圖形化載子材料100’以形成凹部104，其中可後續放置晶粒於其中。在載子材料層100及100’之間的止蝕刻層102可用為凹部104形成之止蝕刻件並可界定放置晶粒於其上之平坦表面。如此形成之凹部104可包含底部101、傾斜部105、及頂部107，其中頂部包含止蝕刻層102的一部分。
在其他實施例中，可形成凹部104，並且載子材料100的底部可維持實質上平坦，如第1c圖中所示。在一實施例中，晶粒，如微電子晶粒106，例如，可附接在凹部104內(第1c圖)。在一實施例中，晶粒106可包含薄晶粒106，且可包含低於約150微米的厚度。在一實施例中，晶粒106可附接至凹部104的頂部107。在一實施例中，晶粒106可包含至少一側壁108、背側111、及主動側112。在一實施例中，晶粒106的背側111可直接置於凹部104內之止蝕刻層102的一部分上。在一些情況中，黏膜(未圖示)及/或附接程序可用來附接晶粒106到載子材料100’的凹部104中。在一實施例中，可粗糙化載子材料，如銅，以有助於晶粒106的附接。
在一實施例中，黏膜可用為最終封裝的永久部分以保護晶粒106的背側111、提供標記用之表面、及/或應付例如可能發生在晶粒106內的任何翹曲。在一實施例中，黏劑可包含背側膜(DBF)，可在放置之前施加至晶粒106的背側111。可例如以金屬粒子(如銅或銀)填充DBF，以增進當後續連接至散熱器裝置(如微通道散熱器)時之導電性。
可在載子材料100’上及在載子材料100’的凹部104中之晶粒106旁上形成介電質材料110(第1d圖)。在一實施例中，可藉由例如層壓程序形成介電質材料110。可在凹部104的底部101上、凹部104的傾斜部105上、及圍繞晶粒106的載子材料100’之凹部104的頂部107之一部分形成介電質材料110。介電質材料110可提供後續增建程序的水平面。在一實施例中，可在層壓之前粗糙化載子材料100’以幫助至介電質材料110的黏性。
在一實施例中，通孔113可形成在晶粒106的晶粒區域著陸中的介電質材料110中，其中晶粒墊，例如銅晶粒墊，可暴露在晶粒106的主動側112上(第1e圖)。在一實施例中，可使用半添加程序(SAP)來在晶粒106的晶粒墊上形成晶粒墊互連結構112並可在晶粒106旁的介電質材料110上形成第一金屬層114(第1f圖)。可接著使用例如標準基板SAP增建程序來形成後續層，其中可堆疊形成其他的介電層110’及金屬化層114’以藉由利用增建程序來形成無芯封裝結構120之無芯基板部116(第1g圖)。在一實施例中，無芯封裝結構120可包含BBUL無芯封裝結構120，且晶粒106可完全嵌入無芯封裝120中，其中完全嵌入意指其中晶粒106直接附接至層110’而無凹部104的程序。
在一實施例中，當完成增建時，可移除頂載子材料100及止蝕刻層102，暴露出附接至無芯封裝結構120的底載子材料100’(第1h圖)。在某些情況中，可化學處理載子材料100’以減少進一步氧化。在一實施例中，可圖形化底載子材料100’以形成至少一功能化載子結構100’。在一實施例中，功能化載子結構100’可置於無芯封裝結構120的深度122內。可形成功能化載子材料100’以提供各種功能。例如，在一實施例中，保留在無芯封裝120上/內之載子材料100’可作用為加強件100’。在某些情況中，無芯基板部116可直接增建於加強件/功能化載子結構100’上，而無任何外部添加的宏觀黏性附接。在一實施例中，無芯封裝基板120可進一步包含互連結構125，如球柵陣列式(BGA)球，其可附接至封裝結構120。
在一實施例中，藉由調整正確的材料性質，載子材料100，在晶粒106的周圍之存在(其在某些情況中可包含銅環)可減輕無芯封裝結構120之翹曲。在一些先前技術無芯BBUL封裝結構，可採用非常小型的形式因子(~12×12 mm)產品。較大形式因子產品受益於至BBUL封裝結構120之加強件100’的添加而不添加額外的後封裝成本，因為加強件後封裝製造的附接會增加封裝時成本。因此，在此實施例之加強件使此技術得以延伸至更成本敏感市場/架構，像是例如晶片組、及低z高度行動CPU。在其他實施例中，可功能化/形成載子材料100’以提供若干額外的功能，諸如但不限於散熱器、EMI(電磁干擾)屏蔽、等等之形成。在一實施例中，至少一功能化載子結構100’的頂表面115與無芯無凸塊增建封裝120的頂表面113共面且與晶粒106之背側111共面。
在另一實施例中，可使用半添加程序來在晶粒206的晶粒墊上形成晶粒墊互連結構212並可在晶粒206旁的介電質材料210上形成第一金屬層214(第2a圖)。可在晶粒區域外(在非晶粒區域中)形成通孔215以連接底載子層200’，其中可在底載子層200’上設置止蝕刻層202，且其中可在止蝕刻層202上設置頂載子層200(第2a圖)。
可接著使用例如標準基板SAP增建法來形成後續層以形成封裝220的其餘部分，其中可堆疊形成其他的介電層210’及金屬化層214’以藉由利用增建程序來形成無芯封裝結構220之無芯基板部216(第2b圖)。在一實施例中，無芯封裝結構220可包含BBUL無芯封裝結構220。在一實施例中，可移除載子材料200之頂層及止蝕刻層202(第2c圖)。可接著圖形化底層200’以形成電感器結構201。在一實施例中，可在底載子材料層200上層壓乾膜並可進行減法圖形化以形成電感器結構201。在某些情況中，可進行額外化學處理或環氧材料的二次注塑以保護電感器結構201不受機械及環境破壞。
第2d圖描繪顯示在晶粒206兩側上之螺旋電感器結構201的上視圖，並具有通孔在起始及結束點下以電性連接它們至封裝220(通孔未圖示)。在另一實施例中，在移除載子材料200的頂層及止蝕刻層202之後，可圖形化載子材料底層200’以在晶粒206旁形成PoP(封裝於封裝上)島狀結構203(第2e圖)。在一實施例中，可在載子材料200’的頂層上層壓乾膜並執行減法圖形化以形成POP結構203。
在某些情況中，可進行額外的處理以在PoP結構203上形成希望的表面處理。本實施例的一優點在於POP墊203的頂表面231與晶粒206之頂表面(背側)230齊平/共面，其提供改善的Z高度及附接另一封裝至無芯封裝結構220的能力。
第3圖顯示根據本發明之一實施例的電腦系統。在一些實施例中，系統300包括處理器310、記憶體裝置320、記憶體控制器330、圖形控制器340、輸入及輸出(I/O)控制器350、顯示器352、鍵盤354、指示裝置356、及周邊裝置358，其所有可透過匯流排360互相通訊耦合。處理器310可為一般目的處理器或特定應用積體電路(ASIC)。I/O控制器350可包括有線或無線通訊之通訊模組。記憶體裝置320可為動態隨機存取記憶體(DRAM)裝置、靜態隨機存取記憶體(SRAM)裝置、快閃記憶體裝置、或這些記憶體裝置的結合。因此，在一些實施例中，系統300中之記憶體裝置320不需包括DRAM裝置。
顯示在系統300中之一或更多構件可包括在一或更多積體電路封裝中及/或可包括一或更多積體電路封裝，如包括例如第1h、2c、及2e圖之功能化載子材料的封裝結構。例如，處理器310、記憶體裝置320、I/O控制器350的至少一部分、或這些構件的結合可包括在積體電路封裝中，其包括結構的至少一實施例，諸如在此提出之各種功能化載子材料結構，敘述在各種實施例中。
這些元件執行此技藝中眾所皆知的其之傳統功能。尤其，記憶體裝置320可在某些情況中用來提供根據本發明之實施例的用於形成封裝結構之方法的可履行指令之長期貯存，且在其他實施例中可在處理器310的履行期間用來短期儲存根據本發明之實施例的用於形成封裝結構之方法的可履行指令。另外，可儲存指令，或否則與和系統通訊耦合之機器可存取媒體關聯，如光碟唯讀記憶體(CD-ROM)、數位多功能碟(DVD)、及軟碟，載波、及/或其他傳播信號。在一實施例中，記憶體裝置320可供應處理器310可履行指令供履行。
系統300可包括電腦(如桌上型電腦、膝上型電腦、手持裝置、伺服器、網絡家電、路由器、等等)、無線通訊裝置(如手機、無線電話、呼叫器、個人數位助理、等等)、電腦相關周邊裝置(如印表機、掃描器、及監視器)、娛樂裝置(如電視、收音機、音響、卡帶及光碟播放器、錄像機、攝像機、數位相機、MP3(運動圖像專家群，音頻層3)播放器、視頻遊戲、錶、等等)、及之類。
實施例之優點致能新的封裝架構，其可以目前封裝架構大約一半的成本來達成未來行動/手持晶片系統(SoC)處理器的設計要求。各種實施例致能翹曲改善加強件、EMI屏蔽、電感器結構、PoP島狀結構、及散熱器結構之添加而無額外後封裝製造成本。各種實施例的POP島狀結構具有可無需插件以將封裝中的晶粒厚度納入考量下形成的額外優點。
無芯BBUL封裝之先前技術處理流程典型涉及在蓋有銅箔之臨時芯/載子上之基板的建立，在封裝和芯分離之後蝕刻掉該銅箔。在此的實施例包括功能化在載子上之載子材料/銅箔以用於諸如散熱器、翹曲改善、RF構件之電磁干擾(EMI)屏蔽、產生封裝上封裝(POP)應用之墊片等等，因此減少成本並增加產率。
雖上述說明已經指明可用於本發明之實施例中的步驟及材料，熟悉此技藝人士將理解到可做出許多修改及替換。據此，意圖將所有這種修改、變更、替換、及添加視為落入本發明之精神與範疇內，其由所附之申請專利範圍所界定。另外，可理解到各種微電子結構，如封裝結構，為此技藝中眾所週知者。因此，在此提供之圖示僅繪示與本發明之實行有關的一示範微電子裝置的部分。因此，本發明不限於在此所述之結構。
100．．．載子材料
100’．．．載子材料
101．．．底部
102．．．止蝕刻層
103．．．厚度
105．．．傾斜部
106．．．晶粒
107．．．頂部
108．．．側壁
110．．．介電質材料
110’．．．介電層
111．．．背側
112．．．主動側
113．．．通孔
113．．．頂表面
114．．．第一金屬層
114’．．．金屬化層
115．．．頂表面
116．．．無芯基板部
120．．．無芯基板結構
122．．．深度
125．．．互連結構
200’．．．底載子層
200．．．頂載子層
201．．．電感器結構
202．．．止蝕刻層
203．．．島狀結構
206．．．微電子晶粒
210．．．介電質材料
210’．．．介電層
212．．．晶粒墊互連結構
214．．．第一金屬層
214’．．．金屬化層
215．．．通孔
216．．．無芯基板部
220．．．封裝
230．．．頂表面
231．．．頂表面
300．．．系統
310．．．處理器
320．．．記憶體裝置
330．．．記憶體控制器
340．．．圖形控制器
350．．．輸入及輸出控制器
352．．．顯示器
354．．．鍵盤
356．．．指示裝置
358．．．周邊裝置
360．．．匯流排
雖然說明書以特別指出及明確主張本發明之某些實施例的專利權之申請專利範圍作結束，可從本發明之說明連同閱讀附圖更迅速確定本發明之優點，其中：
第1a至1h圖代表根據本發明之一實施例的形成結構之方法。
第2a至2e圖代表根據本發明之一實施例的形成結構之方法。
第3圖代表根據本發明之一實施例的系統。
100’．．．載子材料
106．．．晶粒
110．．．介電質材料
110’．．．介電層
111．．．背側
112．．．主動側
113．．．頂表面
114．．．第一金屬層
114’．．．金屬化層
115．．．頂表面
116．．．無芯基板部
120．．．無芯基板結構
122．．．深度
125．．．互連結構

Claims (24)

  1. 一種用以形成具有無芯封裝之功能化載子結構的方法，包含：在載子材料中形成凹部，其中該載子材料包含藉由止蝕刻層分離的頂層及底層；附接晶粒到該凹部中；在該晶粒旁並在該載子材料底層上形成介電質材料；藉由在該介電質材料上增建諸層來形成無芯基板，其中該無芯基板包含無芯無凸塊的增建層封裝之一部分；從該載子材料的該底層移除該載子材料頂層及止蝕刻層；以及圖形化該底層載子材料以形成電感器及PoP島狀結構的至少一者，其中該PoP島狀結構的頂表面與該無芯無凸塊增建封裝的頂表面共面。
  2. 如申請專利範圍第1項所述之方法，進一步包含其中該載子材料的該底層維持附接至該無芯基板。
  3. 如申請專利範圍第2項所述之方法，進一步包含其中該載子材料的該底層包含散熱器、EMI屏蔽結構、及加強件的至少一者。
  4. 如申請專利範圍第3項所述之方法，進一步包含其中該加強件包含圍繞該晶粒之銅環。
  5. 如申請專利範圍第1項所述之方法，進一步包含在該載子材料頂層及止蝕刻層設置於該無芯基板上的同時 移除它們。
  6. 如申請專利範圍第4項所述之方法，進一步包含其中該加強件附接至該基板而無黏劑。
  7. 如申請專利範圍第1項所述之方法，進一步包含其中該載子材料包含銅。
  8. 一種用以形成具有無芯封裝之功能化載子結構的方法，包含：附接晶粒到載子材料，其中該載子材料包含藉由止蝕刻層分離之頂層及底層；在該晶粒旁並在該載子材料底層上形成介電質材料；在該晶粒區域中形成晶粒墊互連結構；在非晶粒區域中形成通孔以與該底層載子材料連接；藉由在該介電質材料上增建諸層來形成無芯基板，其中該無芯基板包含無芯無凸塊的增建層封裝之一部分；從該底層載子材料移除該頂層載子材料及止蝕刻層；以及圖形化該底層載子材料以形成電感器及PoP島狀結構的至少一者，其中該PoP島狀結構的頂表面與該無芯無凸塊增建封裝的頂表面共面。
  9. 如申請專利範圍第8項所述之方法，進一步包含其中該底層載子材料無需黏劑附接至該無芯基底。
  10. 一種用以形成具有無芯封裝之功能化載子結構的結構，包含： 嵌入無芯基板中之晶粒；在該晶粒旁之介電質材料；設置在該晶粒之晶粒墊區域中的晶粒墊互連結構；以及設置在該無芯基板內之至少一功能化載子結構，其中該至少一功能化載子結構的頂表面與該無芯基板的頂表面共面，其中該功能化載子結構包含電感器及PoP島狀結構的至少一者，以及其中該至少一電感器包含在該晶粒旁的至少一螺旋電感器，其中該至少一螺旋電感器的頂表面與該晶粒的頂表面共面。
  11. 如申請專利範圍第10項所述之結構，其中該至少一功能化結構包含銅材料。
  12. 如申請專利範圍第10項所述之結構，其中該無芯基板包含無芯無凸塊的增建層封裝結構之一部分。
  13. 如申請專利範圍第10項所述之結構，其中該至少一功能化載子結構包含加強件、散熱器、及EMI屏蔽結構的至少一者。
  14. 如申請專利範圍第10項所述之結構，其中該功能化載子結構無需黏劑附接至該無芯基底。
  15. 如申請專利範圍第14項所述之結構，其中該功能化載子結構包含銅。
  16. 如申請專利範圍第12項所述之結構，其中該晶 粒與該功能化載子結構的頂表面共面，以及其中該晶粒完全嵌入該無芯基板之中。
  17. 一種用以形成具有無芯封裝之功能化載子結構的結構，包含嵌入無芯基板中之晶粒；在該晶粒旁之介電質材料；設置在該晶粒之晶粒墊區域中的晶粒墊互連結構；設置在非晶粒區域中於該無芯基板中連接至功能化載子結構的通孔，其中該功能化載子結構設置在該無芯基板內，以及其中該功能化載子結構的頂表面與該無芯基板的頂表面共面，其中該功能化載子結構包含電感器及PoP島狀結構的至少一者，以及其中該至少一電感器包含在該晶粒旁的至少一螺旋電感器，其中該至少一螺旋電感器的頂表面與該晶粒的頂表面共面。
  18. 如申請專利範圍第17項所述之結構，其中該功能化載子結構包含銅材料。
  19. 如申請專利範圍第17項所述之結構，其中該無芯基板包含無芯無凸塊的增建層封裝結構之一部分。
  20. 如申請專利範圍第17項所述之結構，其中該PoP島狀結構的頂表面與該無芯無凸塊增建封裝的頂表面共面。
  21. 如申請專利範圍第20項所述之結構，其中該無 芯無凸塊增建封裝不包含插件。
  22. 如申請專利範圍第17項所述之結構，進一步包含一種系統，包含：通訊耦合至該結構的匯流排；以及通訊耦合至該匯流排的DRAM。
  23. 如申請專利範圍第17項所述之結構，其中該晶粒與該功能化載子結構的頂表面共面，以及其中該晶粒完全嵌入該無芯基板之中。
  24. 如申請專利範圍第17項所述之結構，其中該功能化載子結構無需黏劑附接至該無芯基底。
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