TWI464836B - 具有第二基板以促進核心功率及接地分佈之積體電路 - Google Patents

具有第二基板以促進核心功率及接地分佈之積體電路 Download PDF

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TWI464836B
TWI464836B TW095144184A TW95144184A TWI464836B TW I464836 B TWI464836 B TW I464836B TW 095144184 A TW095144184 A TW 095144184A TW 95144184 A TW95144184 A TW 95144184A TW I464836 B TWI464836 B TW I464836B
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substrate
integrated circuit
conductors
circuit die
conductor
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TW095144184A
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TW200731478A (en
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Donald E Hawk
James C Parker
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Agere Systems Inc
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Description

具有第二基板以促進核心功率及接地分佈之積體電路
本發明一般而言係關於積體電路，且更特定言之，係關於一已封裝積體電路內之功率、接地或其他信號線之分佈。
多種不同的積體電路封裝類型在該技術中已為吾人所知。一種稱為導線結合封裝之封裝類型通常利用導線結合來將一引線框架或其他類型基板之引線與在一積體電路晶粒上之相應結合襯墊連接起來。此類封裝可利用一塑膠球狀柵格陣列(PBGA)基板，且因此被稱為導線結合PBGA封裝。
雖然該封裝具有低成本之優勢，但其可能未能在經由功率及接地導體而不經歷顯著電壓降落的情況下，傳遞必要之功率至積體電路晶粒之核心(尤其在高功率應用中)。因此，覆晶封裝通常用於該高功率應用中。然而，覆晶封裝歸因於諸如通常用於封裝基板中之細線路由之因素而極為昂貴。雖然覆晶封裝之成本可藉由在基板中使用較粗糙之線路由而減小，但所得封裝可能未能在每單元邊緣上容納所要數目之信號。
許多不同的堆疊晶粒積體電路組態亦已為吾人所知。該等堆疊晶粒積體電路組態包括(作為實例)在標題為"Stacked Flip Chip Assemblies"之美國專利申請公開案第2002/0074637號、標題為"Integrated Circuit with Re－Route Layer and Stacked Die Assembly"之美國專利申請公開案第2005/0194674號及標題為"Electrical Shielding in Stacked Dies by Using Conductive Die Attach Adhesive"之PCT國際申請案第WO 2005/034238號中所描述之配置。
以發明者Thaddeus J.Gabara之名字於2004年12月13日申請且標題為"Integrated Circuit with Stacked－Die Configuration Utilizing Substrate Conduction"(其在此共同讓渡且以引用的方式併入本文中)之美國專利申請案序號11/010,721揭示了用於在一具有堆疊晶粒組態之積體電路中提供基板傳導之技術。在此申請案中所揭示之一配置中，一積體電路包含排列在一堆疊中之複數個積體電路晶粒，其中一給定晶粒而非堆疊之一上晶粒為其自身及堆疊之經由基板傳導之至少一額外晶粒承載電流。
雖然上文所引用之參考案中所描述之類型的堆疊晶粒配置可提供優於單一晶粒積體電路之多個優勢，但該等配置通常並不能充分地處理上文指出之導線結合PBGA封裝及其他類型的習知導線結合封裝的核心功率及接地分佈問題。
因此，所需要的為一經改良之積體電路封裝配置，其可適應高功率應用而沒有習知導線結合封裝之顯著電壓降落且沒有與典型覆晶封裝之細線路由相關聯之成本。
本發明之說明性實施例提供經改良之封裝配置，其中一覆於附著至封裝基板之積體電路晶粒上之額外基板用於促進核心功率及接地分佈。
根據本發明之一態樣，一積體電路包含一第一基板、一附著至該第一基板之積體電路晶粒及一覆於該積體電路晶粒之至少一部分上之第二基板。該第二基板包含至少一導線結合至該第一基板之一導體且電連接至該積體電路晶粒之一導體之導體。
在說明性實施例中之一者中，第二基板之導體用於為積體電路晶粒提供核心功率及接地連接。更具體言之，第二基板可包含在該第二基板之上表面上之複數個導體、在該第二基板之下表面上之複數個導體及自其上表面至其下表面穿過該第二基板之複數個通道。通道之每一者在第二基板之上表面導體中之一或多者與第二基板之下表面導體中之一或多者之間提供電連接。第二基板之上表面導體導線結合至第一基板之各別導體，且第二基板之下表面導體經由各別焊料凸塊或其他適當類型之基板至晶粒之互連件而電連接至積體電路晶粒之各別導體。
根據本發明之另一態樣，提供一種形成一積體電路之方法。該方法包括以下步驟：將一積體電路晶粒附著至一第一基板；提供一覆於該積體電路晶粒之至少一部分上之第二基板及將該第二基板之至少一導體導線結合至該第一基板之一導體，其中該第二基板之該導體電連接至該積體電路晶粒之一導體。該第二基板可在將晶粒附著至該第一基板之前(例如，在晶圓階段)連接至該積體電路晶粒。或者，第二基板可在將晶粒附著至該第一基板之後而連接至該積體電路晶粒。
說明性實施例提供優於之前所描述之習知技術之許多顯著優勢。舉例而言，該等實施例克服了上文指出之導線結合PBGA封裝及其他類型之習知導線結合封裝的核心功率及接地分佈問題。其可在沒有習知導線結合封裝之顯著電壓降落且沒有與具有細線路由之典型覆晶封裝相關聯之成本的情況下適應高功率之應用。
本發明在此處將在許多例示性積體電路及相關聯封裝配置之背景中來說明。然而，應瞭解，所展示之特定積體電路及封裝配置僅作為說明性實例來提供，且不欲以任何方式限制本發明之範疇。顯而易見的，本發明之技術可應用於多種需要相對於習知導線結合及覆晶封裝提供改良之其他積體電路組態中。
圖1展示一根據本發明之第一說明性實施例而組態之已封裝積體電路100。該積體電路100包含一積體電路晶粒102、一第一基板104及一第二基板106。積體電路晶粒102使用習知晶粒附著技術附著至第一基板104。如所展示，第二基板106覆於積體電路晶粒102上。通常，第二基板106包含至少一導體，其以導線結合至第一基板104之一導體且電連接至積體電路晶粒102之一導體。在此特定實施例中，如將在下文中更詳細描述，第二基板106之各導體用於在第一基板104與積體電路晶粒102之間提供核心功率及接地連接。
此實施例中之第一基板104包含一球狀柵格陣列基板，或更具體言之，一PBGA基板，而第二基板106則包含一覆晶基板。然而，應瞭解，在其他實施例中可使用任何組合之其他類型的基板。
積體電路100進一步包含一散熱器110，其附著至第二基板106之一上表面且經組態以協助耗散來自積體電路晶粒102之熱量。該散熱器可使用如將由熟習此項技術者所瞭解之習知技術由金屬或其他適當材料形成。在其他實施例中，可排除該散熱器。
在此實施例中之積體電路100包含一利用一導線結合類型之封裝之已封裝積體電路。利用導線結合108以將第一基板104之導體與積體電路晶粒102之上表面導體連接起來。額外之導線結合108用於將第一基板104之導體與第二基板106之上表面導體連接起來。在此說明性實施例中，後者之此等導體為功率及接地導體，其經利用以自第一基板104對積體電路晶粒102供應核心功率及接地。於本文中，術語"功率"在無限制之情況下可稱為(例如)VDD電源、VSS電源或其他正或負供電電壓。
積體電路100使用一諸如塑膠之習知囊封材料112進行囊封以形成一已封裝積體電路。在此例示性封裝配置中，第一基板104之下表面包含複數個焊球或其他類型之連接件114以協助該已封裝積體電路安裝於電路板或其他安裝結構上。已整合已封裝之導線結合類型之該等及其他習知態樣在此項技術中已較好地為吾人所瞭解，且因此在此處將不進一步描述。
此實施例中之第二基板106包含在其上表面上之複數個導體、在其下表面上之複數個導體及自其上表面至其下表面穿過該第二基板之複數個通道115。通道之每一者在第二基板之上表面導體中之一或多者與第二基板之下表面導體中之一或多者之間提供電連接。如上文所指示，第二基板106之上表面導體導線結合至第一基板104之各別導體。第二基板106之下表面導體經由各別焊料凸塊或其他適當類型之基板至晶粒的互連件而電連接至積體電路晶粒102之各別導體。
圖2以一積體電路200之形式來展示本發明之另一實施例。此實施例類似於圖1之實施例，但具有不同的第一及第二基板之組態。為更好地展示諸如第一及第二基板及積體電路晶粒之上表面導體的特徵，在該圖中提供透視圖而非圖1之側橫截面圖。除此之外，散熱器及囊封材料為說明之簡單及清楚起見而自該視圖中省略。
積體電路200包含一附著至一第一基板204之積體電路晶粒202。第二基板206覆於該積體電路晶粒上。第二基板之上表面包含耦接至通道215之導體220，該通道215穿過第二基板206至其下表面。在下表面，通道215耦接至第二基板206之下表面導體(未圖示)。該等下表面導體經由互連件222(其說明性地包含焊料凸塊)而耦接至積體電路晶粒202之上表面上之相應導體(未圖示)。
第一基板204包括周邊導體224，其導線結合至第二基板206或積體電路晶粒202上之相應導體。更具體言之，第一基板204之某些周邊導體224導線結合至積體電路晶粒202之相應周邊導體，而第一基板204之其他周邊導體224導線結合至第二基板206之相應周邊導體。在此實施例中之導線結合出現在與各別導體相關聯之結合襯墊處，但術語"導體"於本文中使用時意欲經一般解釋以包含以任何組合之結合襯墊、導電跡線、焊球或其他互連件或類似之導電電路元件。
關於結合襯墊，可見積體電路晶粒202具有一上表面，在該上表面之周邊鄰近排列有複數個結合襯墊。積體電路晶粒可進一步包含在上表面之中心區域中排列之複數個結合襯墊或其他類型之導體，但該等導體為說明之簡單及清楚起見未在圖中展示。第二基板206覆於積體電路晶粒202之上表面之中心區域上且具有與積體電路晶粒202之中心區域之結合襯墊或其他導體電接觸之下表面導體。在此實施例中，第二基板206以其並未延伸超出積體電路晶粒之上表面之任何周邊邊緣之方式覆於積體電路晶粒之上表面之中心區域上。除此之外，第二基板206大體上處於積體電路晶粒202之上表面之相對周邊邊緣之間的中心。然而，應瞭解，可使用用於堆疊第一基板、積體電路晶粒及第二基板之多個替代排列。舉例而言，第二基板可延伸超出下面積體電路晶粒之一或多個邊緣。在該等及其他排列中，預期在第二基板與積體電路晶粒之間存在至少部分重疊。除此之外，一給定堆疊可包括多個額外基板、交替晶粒及基板或多種其他堆疊排列。因此，應瞭解，本發明不限於一單一基板－晶粒－基板堆疊或任何其他特定的堆疊排列。
如在之前的實施例中，與第二基板206相關聯之導體用於為積體電路晶粒202供應功率及接地連接。因此，第一基板204之鄰近周邊導體可具有大體上小於第二基板206之鄰近周邊導體之寬度之各別寬度。除此之外，第一基板204之鄰近周邊導體可由一大體上小於第二基板206之鄰近周邊導體之間據之間距來分離。該寬度及間距排列並未明確地展示在該簡化圖中，且不應視為本發明之要求。
上文所描述之實施例提供許多相對於習知實踐之顯著優勢。舉例而言，該等經改良之積體電路封裝排列克服了上文指出之導線結合PBGA封裝及其他類型之習知導線結合封裝的核心功率及接地分佈問題。其可在沒有習知導線結合封裝之顯著電壓降落且沒有與典型覆晶封裝相關聯之成本的情況下而適應高功率之應用。第二基板106或206可為一成本減小的覆晶類型之基板，此係因為僅需要粗糙線路由用於功率及接地分佈。第一基板104或204可為一低廉的PBGA基板，其在每單位邊緣上提供較高數目之信號。
除此之外，在說明性實施例中之第一基板、積體電路晶粒及第二基板之經堆疊之排列提供導線結合之三維分離，其允許電源及接地導體較好地與輸入－輸出(IO)信號線隔離。
另外，第二基板之導體可形成為相對較厚之金屬結構，其可將所需要的核心功率傳遞至積體電路晶粒(尤其在高功率應用中)而不經歷可由習知互連件所導致之顯著之電壓降落。
此外，說明性實施例在積體電路晶粒上保存區域資源，因為不再必要經由一在積體電路晶粒上之習知IO環而帶來核心功率及接地。此可導致在襯墊受限情形中所減小的晶粒尺寸。
此外，減少傳遞核心功率及接地所需之積體電路金屬資源可藉由(例如)增加核心中之路由密度、減少積體電路中之金屬層之數目等而導致較低的積體電路成本。
雖然用於核心功率及接地分佈之說明性實施例中，但第二基板可用於將其他類型之信號自封裝基板分佈至積體電路晶粒，且本發明在此方面不受限制。
應注意，圖1及圖2中所展示之特定組態僅作為說明性實例來呈現，且不應解釋為以任何方式限制本發明之範疇。除此之外，某些習知元件為說明之清楚及簡單起見已自圖中省略。如將為熟習此項技術者所瞭解，該等所省略之元件可包括於本發明之給定實施例中。
本發明之一替代實施例可包含(例如)多個額外基板，其各覆於積體電路晶粒之上表面之一不同部分上。
亦可能在一單一已封裝積體電路中具有多個積體電路晶粒，其中各晶粒具有至少一以本文所描述之方式覆於其至少一部分上之額外基板。
如上文所指示，本發明之一給定實施例可包含一或多個積體電路晶粒。在此種配置中，複數個相同晶粒通常以重複樣式形成於一晶圓之一表面上。每一晶粒可包括多個結構或電路。可將個別晶粒自晶圓切割或分割，接著封裝為一積體電路。熟習此項技術者知道如何分割晶圓及封裝晶粒以產生積體電路。如此製造之積體電路被認為係本發明之部分。
在根據上文所描述之其中一實施例來製造一積體電路時，較佳在晶粒附著至封裝基板104或204之前(在晶圓階段)將上方基板106或206連接至各別積體電路晶粒102或202。舉例而言，若焊料凸塊用於在上方基板與積體電路晶粒之間提供互連，則吾人不欲使封裝基板經受焊料之回焊操作，此焊料之回焊操作係在上方基板之導體與積體電路晶粒之相應導體之間建立電連接所需。在晶圓階段將上方基板附著至各別晶粒後，切割或分割該晶圓並使用習知技術將所得裝置(每一者包含一晶粒加上一上方基板)附著至封裝基板且接著如本文之前所描述進行導線結合。亦可在晶粒已附著至封裝基板後將上方基板連接至積體電路晶粒。
同樣地，本發明之上述實施例意欲僅為說明性的。熟習此項技術者可在不偏離以下申請專利範圍之範疇的情況下設計多個替代實施例。舉例而言，可使用諸如基板、晶粒、導線結合、結合襯墊、堆疊配置或封裝類型之積體電路元件之各種替代實施例。除此之外，多種替代處理步驟可用於形成一根據本發明之積體電路。熟習此項技術者將易瞭解該等及其他替代實施例。
100、200．．．積體電路
102、202．．．積體電路晶粒
104、204．．．第一基板
106、206．．．第二基板
108．．．導線結合
110．．．熱量散播器
112．．．囊封材料
114．．．連接件
115、215．．．通道
220．．．導體
222．．．互連件
224．．．周邊導體
圖1為利用一根據本發明之第一說明性實施例而組態之導線結合封裝之一已封裝積體電路之側橫截面圖。
圖2為利用一與圖1中所展示之類型類似的導線結合封裝之本發明之第二說明性實施例中的一已封裝積體電路之一暴露部分的透視圖。
100．．．積體電路
102．．．積體電路晶粒
104．．．第一基板
106．．．第二基板
108．．．導線結合
110．．．散熱器
112．．．囊封材料
114．．．連接件
115．．．通道

Claims (9)

  1. 一種積體電路，其包含：一第一基板；一積體電路晶粒，其附著至該第一基板；及一第二基板，其覆於該積體電路晶粒之至少一部分上；以導線結合至該積體電路晶粒之一第一導體之該第一基板之一第一周邊導體；該第二基板包含至少一導體，其係以導線結合至該第一基板之一第二周邊導體且電連接至該積體電路晶粒之一第二導體；其中該第二基板包含在該第二基板之一上表面上之複數個導體、在該第二基板之一下表面上之複數個導體及自其上表面至其下表面穿過該第二基板之複數個通道，該等通道中之每一者在該第二基板之該等上表面導體中之一或多者與該第二基板之該等下表面導體中之一或多者之間提供一電連接。
  2. 如請求項1之積體電路，其中該第一基板包含一球狀柵格陣列基板。
  3. 如請求項1之積體電路，其中該第二基板包含一覆晶基板。
  4. 如請求項1之積體電路，其中該第二基板之該等上表面導體中之多個導體係以導線結合至該第一基板之各別導體。
  5. 如請求項1之積體電路，其中該第二基板之該等下表面導體中之多個導體電連接至該積體電路晶粒之各別導體。
  6. 如請求項1之積體電路，其中該積體電路晶粒具有一上表面，該上表面具有在該上表面之一周邊附近排列之複數個結合襯墊及在該上表面之一中心區域中排列之複數個導體，該第二基板覆於該積體電路晶粒之該上表面之該中心區域上且具有與該中心區域之該等導體電接觸之導體。
  7. 一種積體電路，其包含：一積體電路晶粒，其耦接於第一與第二基板之間；以導線結合至該積體電路晶粒之一第一導體之該第一基板之一第一周邊導體；及該第二基板之至少一導體，其係以導線結合至該第一基板之一第二周邊導體且透過該第二基板內之至少一通道電連接至該積體電路晶粒之一第二導體；該第一基板支撐該積體電路晶粒且以導線結合至該積體電路晶粒及該第二基板；該第二基板覆於該積體電路晶粒上且與該積體電路晶粒電接觸。
  8. 一種形成一積體電路之方法，該方法包含以下步驟：將一積體電路晶粒附著至一第一基板；提供一第二基板覆於該積體電路晶粒之至少一部分上； 將該第一基板之一第一周邊導體以導線結合至該積體電路晶粒之一第一導體；及將該第二基板之至少一導體以導線結合至該第一基板之一第二周邊導體，亦使該第二基板之該導體透過該第二基板電連接至該積體電路晶粒之一第二導體；其中該第二基板包含在該第二基板之一上表面上之複數個導體、在該第二基板之一下表面上之複數個導體及自其上表面至其下表面穿過該第二基板之複數個通道，該等通道中之每一者在該第二基板之該等上表面導體中之一或多者與該第二基板之該等下表面導體中之一或多者之間提供一電連接。
  9. 如請求項8之方法，其中在將該晶粒附著至該第一基板之前將該第二基板連接至該積體電路晶粒。
TW095144184A 2006-01-13 2006-11-29 具有第二基板以促進核心功率及接地分佈之積體電路 TWI464836B (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8411234B2 (en) 2008-03-31 2013-04-02 Au Optronics Corp. Active array substrate, electrode substrate, and liquid crystal display panel capable of locating ions in a non-display region

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010192680A (ja) * 2009-02-18 2010-09-02 Elpida Memory Inc 半導体装置
US8405214B2 (en) * 2011-08-12 2013-03-26 Nanya Technology Corp. Semiconductor package structure with common gold plated metal conductor on die and substrate
US11227846B2 (en) 2019-01-30 2022-01-18 Mediatek Inc. Semiconductor package having improved thermal interface between semiconductor die and heat spreading structure
US11413760B2 (en) 2019-03-29 2022-08-16 RIOA Intelligent Machines, Inc. Flex-rigid sensor array structure for robotic systems
CN115831935B (zh) * 2023-02-15 2023-05-23 甬矽电子(宁波)股份有限公司 芯片封装结构和芯片封装方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040051119A1 (en) * 2000-09-04 2004-03-18 Fujitsu Limited Stacked semiconductor device and method of producing the same
US20050073054A1 (en) * 2003-10-03 2005-04-07 Kelly Michael G. Integrated circuit incorporating flip chip and wire bonding

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0563137A (ja) * 1991-08-30 1993-03-12 Fujitsu Ltd 半導体装置
JP3268740B2 (ja) * 1997-08-20 2002-03-25 株式会社東芝 Ａｓｉｃの設計製造方法、スタンダードセル、エンベッテドアレイ、及びマルチ・チップ・パッケージ
US6265771B1 (en) * 1999-01-27 2001-07-24 International Business Machines Corporation Dual chip with heat sink
US6605875B2 (en) * 1999-12-30 2003-08-12 Intel Corporation Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size
JP2002076250A (ja) * 2000-08-29 2002-03-15 Nec Corp 半導体装置
US20020074637A1 (en) * 2000-12-19 2002-06-20 Intel Corporation Stacked flip chip assemblies
US6441483B1 (en) * 2001-03-30 2002-08-27 Micron Technology, Inc. Die stacking scheme
US6680219B2 (en) * 2001-08-17 2004-01-20 Qualcomm Incorporated Method and apparatus for die stacking
JP2003086733A (ja) * 2001-09-11 2003-03-20 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法およびそれを用いた電子機器
US6476506B1 (en) * 2001-09-28 2002-11-05 Motorola, Inc. Packaged semiconductor with multiple rows of bond pads and method therefor
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
JP2003273317A (ja) * 2002-03-19 2003-09-26 Nec Electronics Corp 半導体装置及びその製造方法
US20030178719A1 (en) * 2002-03-22 2003-09-25 Combs Edward G. Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package
US7053477B2 (en) * 2002-10-08 2006-05-30 Chippac, Inc. Semiconductor multi-package module having inverted bump chip carrier second package
TWI313049B (en) * 2003-04-23 2009-08-01 Advanced Semiconductor Eng Multi-chips stacked package
US7422930B2 (en) * 2004-03-02 2008-09-09 Infineon Technologies Ag Integrated circuit with re-route layer and stacked die assembly
JP4494249B2 (ja) * 2005-02-16 2010-06-30 富士通マイクロエレクトロニクス株式会社 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040051119A1 (en) * 2000-09-04 2004-03-18 Fujitsu Limited Stacked semiconductor device and method of producing the same
US20050073054A1 (en) * 2003-10-03 2005-04-07 Kelly Michael G. Integrated circuit incorporating flip chip and wire bonding

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8411234B2 (en) 2008-03-31 2013-04-02 Au Optronics Corp. Active array substrate, electrode substrate, and liquid crystal display panel capable of locating ions in a non-display region

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