CN102290394B - 散热型电子封装结构及其制备方法 - Google Patents

散热型电子封装结构及其制备方法 Download PDF

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CN102290394B
CN102290394B CN201110165653.1A CN201110165653A CN102290394B CN 102290394 B CN102290394 B CN 102290394B CN 201110165653 A CN201110165653 A CN 201110165653A CN 102290394 B CN102290394 B CN 102290394B
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chip
substrate
heat radiating
electron package
nano carbon
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CN102290394A (zh
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刘安鸿
王伟
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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    • H05K7/2039—Modifications to facilitate cooling, ventilating, or heating characterised by the heat transfer by conduction from the heat generating element to a dissipating body
    • H05K7/205—Heat-dissipating body thermally connected to heat generating element via thermal paths through printed circuit board [PCB]
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    • B82—NANOTECHNOLOGY
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Abstract

一种散热型电子封装结构包含一芯片、一基板、一黏胶和一封胶。黏胶或封胶混合有多个纳米碳球，基板包含一绝缘层和一线路层，且线路层形成于绝缘层上。黏胶设置于芯片与基板之间，芯片电性连接线路层，且封胶覆盖芯片和基板。

Description

散热型电子封装结构及其制备方法
技术领域
本发明关于一种散热型电子封装结构，特别关于一种具高散热能力的散热型电子封装结构。
背景技术
对半导体产品性能上的不断要求导致更高的操作频率及更大的功率消耗。因此，这些半导体产品需要具有高热传导效率，以能有效率地散热，降低互连接点温度的电子封装结构。在该类型半导体中，液晶显示器(LCD)的驱动半导体装置即为其中一例。而另一种使用基板作为芯片载具(chip carrier)的高功率封装结构相同的也需要高热传导效率的热传导方式。
图1显示一种被称为微细间距球格阵列(fine pitch ball grid array；FBGA)封装结构的典型高功率封装结构。FBGA封装结构10包含一芯片11和一基板14。基板14可以为硬质或软性印刷电路板。芯片11以黏晶材料15(例如：黏着膜)固定在基板14上。金属线13连接芯片11的主动面与基板14。封装材料12覆盖芯片11、基板14和金属线13，以保护芯片11与金属线13免于受到破坏。焊球16设置于基板14上，作为FBGA封装结构10的输出入端子(input/output terminals)。随着设置在芯片11的有限面积上的电路的密集化，将产生更多的热，使FBGA封装结构10遭受散热不良的问题。再者，封装材料12包括环氧树脂(epoxy resin)，其具有不良的热传导性，因此容易将热累积在FBGA封装结构10内。一般来说，基板14的绝缘层为高分子材料制作而成，而高分子材料也有不良的热传导性的问题，于是该结构累积的热能不容易从绝缘层传导到FBGA封装结构10外。
另外，新一代的三维集成电路和组件构装为目前封装的趋势。此类装置的构装是关于一种堆栈二个或多个集成电路，以获得三维芯片堆栈的制造方法，而该制造方法需在各迭层间利用穿透硅通孔(through silicon vias；TSVs)，来形成垂直电性连接。所谓穿透硅通孔是蚀穿(etch through)硅晶圆和以金属材料填充其中所形成的垂直连接结构。以TSVs以作为三维连接的方法可在三维层间大量增加传导路径。
图2显示使用TSVs的三维集成电路封装结构。三维集成电路封装结构20包含多个集成电路芯片(211和212)、TSVs(231和232)和一基板24。TSVs(231和232)贯穿集成电路芯片(211和212)。多个微凸块(micro bumps)或软金属覆盖物(softmetal caps)233个别地形成在TSVs(231和232)的表面。多个微凸块233用于电性连接彼此间的集成电路芯片(211和212)，以及连接基板24和与其相邻的TSVs(231和232)。黏胶25将集成电路芯片(211和212)接合一起，并将集成电路芯片(211和212)固定在基板24上。封装材料22覆盖集成电路芯片(211和212)和基板24。数个被动集成电路芯片241嵌在基板24内，多个输出端点(terminals)或电极(electrodes)242设置在基板24的下表面，以做为对外输出电性之用。
在传统的三维集成电路封装结构20中，许多集成电路芯片(211和212)被放入同一封装体内。各芯片(211或212)产生的热能，累积在封装体内，无法有效地经由封装材料22或基板24逸散至外部。为去除传统封装结构既有缺点，因此，需要新的材料与方法，来增进封装结构的热传导效能。
发明内容
本发明的一方面提供一散热型电子封装结构。特别是指一种混合纳米碳球的绝缘树脂材料使用在电子构装中，以增进散热效能。由于纳米碳球会将热能转化成以红外线辐射的方式来传输与散逸，混合纳米碳球的材料可有效率地进行散热，因此能降低电子封装结构的操作温度。
鉴于前述，本发明揭示一种散热型电子封装结构，其包含一芯片、一基板、一黏胶和一封胶材。黏胶或/及封胶材混合有多个纳米碳球，该基板包含一绝缘层和一线路层，线路层形成于绝缘层上。芯片通过黏胶设置于基板上，且芯片电性连接于线路层，而封胶材密封该芯片和基板。
本发明更揭露一种散热型电子封装结构，其包含多个芯片、一基板、一第一黏胶、多个第二黏胶和一封胶材。第一黏胶、多个第二黏胶或封胶材可混合有多个纳米碳球。该基板包含一绝缘层和一线路层，而线路层形成于该绝缘层上。这些芯片中之一通过第一黏胶至基板。其它的芯片则利用第二黏胶垂直堆栈一起。多个芯片电性连接线路层。而封胶材则覆盖这些芯片和基板。
本发明另揭露一种晶圆级芯片尺寸封装结构，其包含一芯片、多个焊垫、多个重分布焊垫、一重配线金属层、一树脂材料和多个纳米碳球。重配线金属层用以将多个焊垫重新分配成重分布焊垫。树脂材料覆盖于芯片上，其中，多个纳米碳球可混合于树脂材料内，以达到红外线辐射散热的效果。
上文已相当广泛地概述本揭露的技术特征及优点，以使下文的本揭露详细描述得以获得较佳了解。构成本揭露的权利要求标的的其它技术特征及优点将描述于下文。本揭露所属技术领域中具有通常知识者应了解，可相当容易地利用下文揭示的概念与特定实施例可作为修改或设计其它结构或制程而实现与本揭露相同的目的。本揭露所属技术领域中具有通常知识者亦应了解，这类等效建构无法脱离后附的权利要求所界定的本揭露的精神和范围。
附图说明
图1显示一传统FBGA封装结构的截面图；
图2显示使用TSVs的传统三维集成电路封装结构；
图3是本发明一实施例的FBGA封装结构的截面示意图；
图4显示本发明一实施例的基板型封装结构的截面示意图；
图5显示本发明一实施例的覆晶球格阵列封装结构的截面示意图；
图6显示本发明一实施例的使用薄膜覆盖焊线胶材的多芯片封装结构的截面示意图；
图7显示本发明一实施例的使用穿透硅通孔的三维集成电路封装结构的截面示意图；
图8显示本发明一实施例的覆晶球格阵列封装结构的截面示意图；
图9至12是截面图，其是根据本发明一实施例，显示在晶圆级芯片尺寸封装制程中，使用混合纳米碳球的黏胶的步骤；及
图13显示本发明一实施例的散热型WLCSP电子封装结构的截面示意图。
具体实施方式
本发明关于将纳米碳球(carbon nanocapsules；CNC)应用在半导体封装结构中，以让半导体封装结构具有加强散热特性。特而言之，一绝缘材料或树脂混合多个纳米碳球，并使用在电子封装的应用上，藉此达到改进半导体芯片的散热的目的。此混合材料或树脂可直接或间接与半导体芯片接触，藉其改善热传导或热散逸(heatdissipation)的效率。在半导体封装构造中，混合材料可应用的部分，例如有：覆晶底胶层、无流动底部密封(non-flow underfill)层、芯片封胶体、芯片披覆(chip coating)层、黏晶胶(die-attach adhesives)、不导电胶/膜(non-conductive paste/film)、导电胶/膜(non-conductive paste/film)或薄膜覆盖焊线(film over wire；FOW)胶材等等。
在混合材料中的纳米碳球具有将热能转化成以红外线辐射的方式来传输与散逸的特性，而此种特性对电子产品封装而言，是理想的散热方式。在一些实施例中，纳米碳球的表面可进一步被处理，以确保他们是电性绝缘，避免使用时产生寄生效应(parasitic effect)或电性短路情形。再者，并可使该纳米碳球粒子与原料树脂间的接触面具有良好的界面黏着力(interfacial adhesion)，因此使用于半导体封装中将更能进一步的提升原有封装结构的散热效率。
在混合材料中的纳米碳球的尺寸可介于1纳米至100纳米。纳米碳球可具有大约30纳米的平均直径。有两种的纳米碳球：中空和填充金属(metal filled)。在混合材料中的纳米碳球包含中空纳米碳球、填充金属纳米碳球或两者。填充金属纳米碳球可填充金属、金属氧化物(metal oxides)、金属碳化物(metal carbides)或合金。
在一些实施例中，在混合材料中的纳米碳球可经处理，以使其具电绝缘层。在一些实施例中，纳米碳球的表面可进一步被处理，以使其与树脂间有良好的界面黏着性(interfacial adhesion)。
因此，前述的混合材料适合与在半导体封装内的一具功能的硅晶粒直接接触。与利用传统热传导与热对流散热的半导体封装结构比较，利用红外线辐射方式来传输与散逸硅芯片的热能，能更有效率地移除热能，降低芯片的温度。此混合材料的应用包含封胶体、覆晶底胶和被覆层(coatings)。前述的混合材料也适合使用在将晶粒黏着在基板(硬质或软性)或使用在晶粒堆栈上等不同晶粒黏着运用。这些黏胶包含一般在本领域中熟知者，例如：网印黏晶胶(screen-on die attach paste)、黏晶薄膜(die attachment film；DAF)、薄膜覆盖焊线(film over wire；FOW)胶材和不导电胶(non-conducting paste；NCP)。
图3是本发明其一实施例的一FBGA封装结构的截面示意图。
FBGA封装结构30包含一芯片31和一基板34。基板34可为硬质或软性印刷电路板，并具有一开口341。芯片31利用黏晶材料35，以其主动面311面向基板34的方式，固定在基板34上，其中该黏晶材料35可为黏着膜(adhesive film)或黏着剂(adhesive paste)或B-stage黏晶胶材。多条金属线33穿过开口341电性连接芯片31与基板34。封胶32包覆芯片31、基板34和金属线33，藉此保护芯片31与金属线33，以避免损坏。焊球36设置于基板34的下表面，作为FBGA封装结构30的输出入端(input/output terminals)。封胶32和黏晶材料35与多个纳米碳球38混合。因此，芯片31所产生的热，除传统常见的热传导与热对流的散热方式外，更可利用红外线辐射的方式，散逸至FBGA封装结构30之外。即，纳米碳球38可帮助移除FBGA封装结构30内的积热。尽管在本实施例中纳米碳球38是混合在封胶32和黏晶材料35两者内，但在其它实施例中，纳米碳球38可单独混合在封胶32或单独混合在黏晶材料35内。
如图4所示，以基板型(substrate-based)封装结构40包含一芯片41和一基板44。芯片41利用黏晶材料45固定在基板44上，其中该黏晶材料45可为黏着膜(adhesive film)或黏着剂(adhesive paste)或B-stage黏晶胶材。一被覆层49覆盖在芯片41的主动面上。封胶42覆盖芯片41、基板44和金属线43，藉以保护芯片41与金属线43避免损坏。封胶42和被覆层49与纳米碳球48混合。于本实施例中，该纳米碳球48混合在封胶42、黏晶材料45及/或被覆层49，如此芯片41所产生的热可透过纳米碳球48有效地以红外线辐射的方式散逸。
图5显示本发明一实施例的覆晶球格阵列(flip chip BGA)封装结构的截面示意图。覆晶球格阵列封装结构50包含一芯片51、一不导电胶(non-conductive paste；NCP)55(或底胶(underfill))、和一基板54。该基板54包含一绝缘层541和一线路层(wiring layer)542(或铜箔(copper foil))，其中线路层542形成于绝缘层541上。芯片51以覆晶接合于基板54上。多个凸块(bumps)57形成在芯片51上，并连接基板54的线路层542。不导电胶55可完全填充芯片51和基板54之间的间隙，并将芯片51固定在基板54上。封胶52覆盖芯片51、基板54和凸块57。封胶52保护芯片51，以避免其受到损坏。焊球56设置于基板54的下表面，以作为覆晶球格阵列封装结构50的输出入端(input/output terminals)。其中，纳米碳球58混合在不导电胶55及/或封胶52内，如此芯片51所产生的热可通过纳米碳球58有效地以红外线辐射的方式散逸。
图6显示本发明一实施例的使用薄膜覆盖焊线胶材(film over wire；FOW)的多芯片封装结构(multi-chip package)的截面示意图。多芯片封装结构60包含多个集成电路芯片61、复数层FOW膜652和一基板64。黏胶651接合最底层的芯片61和基板64。封胶62覆盖芯片61和一部分的基板64。端接点(terminals)或电极(electrodes)642设置于基板64的下表面。线路层643设置于基板64的上表面。柱状凸块(stud bumps)67形成在线路层643上。金属线63连接基板64上的柱状凸块67和芯片61的主动面。其一较佳的做法为该金属线的第一端先于基板上形成一柱状凸块67后使其第二端形成于芯片61的主动面上，就是所谓的逆焊线(ReverseBonding)。
FOW膜652用于包覆金属线63连接在芯片61上的部分，其中FOW膜652可对金属线63提供额外的支撑，以保护金属线63避免损坏或造成短路。又，FOW膜652可帮助相同或相似大小的两邻近且垂直堆栈的芯片61间的黏合。当相同或相似大小的两芯片61垂直堆栈(即，一芯片在另一芯片的上面)时，因位在下方芯片上焊垫(bonding pads)无法延伸出被上方芯片所覆盖的区域，因此在打线接合制程时会产生问题。在下方芯片61的金属线63为FOW膜652包覆的情形下，当上方芯片51进行打线接合时，FOW膜652可提供打线接合所需的支撑。
于本实施例中，纳米碳球68可混合在覆盖芯片61的封胶62、黏胶651和FOW膜652内，从而使得芯片61产生的热可轻易地以红外线辐射的方式散逸至外界环境中。
图7显示本发明一实施例的使用穿透硅通孔(TSVs)的三维集成电路封装结构的截面示意图。三维集成电路封装结构70包含多个集成电路芯片(711和712)、穿透硅通孔(731和732)以及一基板74。穿透硅通孔(731和732)对应地贯穿各个集成电路芯片(711和712)。多个微凸块(micro bumps)或软金属覆盖物(soft metal caps)733和734分别形成在穿透硅通孔(731和732)上作为连接之用。如图7所示，堆栈的集成电路芯片(711和712)和基板74以这些微凸块或软金属覆盖物(733和734)相互连接。黏胶75用于将集成电路芯片(711和712)接合在一起，并将这些芯片(711和712)固定在基板74上。封胶72覆盖芯片(711和712)和部分的基板74。多个被动集成电路芯片741嵌入在基板74内。端接点(terminals)或电极(electrodes)742设置在基板74的下表面。该封胶72和黏胶75混合有纳米碳球78，并予以覆盖各芯片(711和712)，使得从芯片(711和712)产生的热可轻易地透过红外线辐射的方式散逸至外界环境中。
图8显示本发明一实施例的覆晶球格阵列(flip-chip ball grid array；BGA)封装结构的截面示意图。覆晶球格阵列封装结构80包含一芯片81、一底胶层(underfilllayer)85和一基板84。芯片81以覆晶接合方式固定在基板84上。形成在芯片81上的多个凸块87用以连接在基板84上的线路层842。并于基板84的下表面形成有多个焊球86。底胶层85可完全填充芯片81和基板84间的间隙。且封胶82覆盖芯片81、底胶层85和部分的基板84。其中，该纳米碳球88混合在底胶层85及/或封胶82内，使得芯片81所产生的热可有效地透过红外线辐射的方式被透过基板84而散逸。
图9至11是根据本发明一实施例的截面图，主要是揭示在晶圆级芯片尺寸(wafer level chip scale package；WLCSP)封装制程中，使用混合纳米碳球的黏胶的步骤。如图9所示，本发明提供一具有多个集成电路芯片的晶圆91。在图10中，混合有纳米碳球的树脂材料93被涂布在晶圆91的表面上，其中该表面与多个焊球92是相对的。其中，焊球92形成的时机可在涂布树脂材料93之前或之后。值得注意的是该树脂材料93涂布在晶圆91的背面上。在图11中，涂布树脂材料93的晶圆91接着被切割成个别WLCSP电子封装结构94，而各个WLCSP电子封装结构94可以覆晶接合的方式，固定在一基板95上(如图12所示)，其中WLCSP电子封装结构94和基板95之间可依实际需求选择填充或不填充底胶层96，而基板95可为印刷电路板或其它类似者。在一实施例中，底胶层96亦可混合有多个纳米碳球。
如图13所示，散热型WLCSP电子封装结构(thermally enhanced WLCSPelectronic package)94可利用晶圆级封装技术(wafer level packaging technology)，其中晶圆级封装技术可为重新分配层和凸块技术(redistribution layer and bumptechnology)、密封铜柱技术(encapsulated copper post technology)、密封打线接合技术(encapsulated wire bond technology)或其它类似者。制作完成的WLCSP电子封装结构94所具有的尺寸可与芯片90相当。在一实施例中，WLCSP电子封装结构94包含一芯片90，芯片90包含多个焊垫1202，多个重分布焊垫(redistributed bondpad)1203、一重配线金属层(redistributed metal layer)1204、复数层绝缘层(1205、1206和1207)、树脂材料93和多个纳米碳球，其中重配线金属层1204用于将多个焊垫1202重新分配成重分布焊垫1203；复数层绝缘层(1205、1206和1207)部分地将重配线金属层1204与芯片90分离，和将重配线金属层1204与多个重分布焊垫1203分离；树脂材料93覆盖芯片90；纳米碳球则混合在树脂材料93内。进一步而言，树脂材料93可位于芯片90的背面。多个重分布焊垫1203可为底层金属焊垫(underbump metal pads)或铜柱(未绘示)。复数层绝缘层(1205、1206和1207)可包含高分子绝缘材料，例如：以苯并环丁烯为基础的(benzocyclobutene-based)高分子绝缘材料。在一实施例中，纳米碳球可混合在任何或所有的复数层绝缘层(1205、1206和1207)。重配线金属层1204可包含铜或铝。焊球92可接合在重分布焊垫1203上。
本揭露的技术内容及技术特点已揭示如上，然而本揭露所属技术领域中具有通常知识者应了解，在不背离后附权利要求所界定的本揭露精神和范围内，本揭露的教示及揭示可作种种的替换及修饰。例如，上文揭示的许多制程可以不同的方法实施或以其它制程予以取代，或者采用上述二种方式的组合。
此外，本案的权利范围并不局限于上文揭示的特定实施例的制程装置、方法或步骤。本揭露所属技术领域中具有通常知识者应了解，基于本揭露教示及揭示制程、装置、方法或步骤，无论现在已存在或日后开发者，其与本案实施例揭示者以实质相同的方式执行实质相同的功能，而达到实质相同的结果，亦可使用于本揭露。因此，以下的权利要求用以涵盖用以此类制程装置、方法或步骤。

Claims (18)

1.一种散热型电子封装结构，包含：
一基板，包含：
一绝缘层；及
一线路层，形成于该绝缘层上；
一芯片，电性连接该线路层；
一黏胶，设置于该芯片与该基板之间；
一封胶，覆盖该芯片和该基板；以及
多个纳米碳球，混合于该黏胶及该封胶内；
其中，所述纳米碳球的表面是可处理的，以具有电绝缘层，所述电绝缘层防止有寄生效应或电性短路现象发生。
2.根据权利要求1所述的散热型电子封装结构，其特征在于，其更包含一被覆层，该被覆层覆盖在该芯片的一主动面上，其中该多个纳米碳球均匀地分布在该被覆层中。
3.根据权利要求1所述的散热型电子封装结构，其特征在于，其更包含多根金属线，该多根金属线电性连接该芯片和该线路层。
4.根据权利要求1所述的散热型电子封装结构，其特征在于，其包含多个凸块，该多个凸块电性连接该芯片和该线路层。
5.根据权利要求1所述的散热型电子封装结构，其特征在于，该芯片包含一主动面，其中该主动面面向该基板。
6.根据权利要求1所述的散热型电子封装结构，其特征在于，其更包含一开口及多根金属线，该多根金属线穿过该开口，以电性连接该芯片和该线路层。
7.根据权利要求1所述的散热型电子封装结构，其特征在于，该黏胶是一黏晶材料、一不导电胶或一底胶层。
8.根据权利要求1所述的散热型电子封装结构，其特征在于，其更包含多个焊球，该多个焊球设置于该基板上。
9.一种散热型电子封装结构，包含：
一基板，包含：
一绝缘层；及
一线路层，形成于该绝缘层上；
多个芯片，垂直堆栈且电性连接该线路层；
一第一黏胶，黏接该多个芯片中的一者至该基板；
多个第二黏胶，黏接该多个芯片；
一封胶，覆盖该多个芯片和该基板；以及
多个纳米碳球，混合于该第一黏胶、该多个第二黏胶及该封胶内；
其中，所述纳米碳球的表面是可处理的，以具有电绝缘层，所述电绝缘层防止有寄生效应或电性短路现象发生。
10.根据权利要求9所述的散热型电子封装结构，其特征在于，其更包含多根金属线，该多个芯片透过该多根金属线电性连接该线路层。
11.根据权利要求10所述的散热型电子封装结构，其特征在于，该多个第二黏胶为薄膜覆盖焊线胶材。
12.根据权利要求9所述的散热型电子封装结构，其特征在于，其更包含多个穿透硅通孔，其中该多个芯片透过该多个穿透硅通孔电性连接该线路层。
13.根据权利要求9所述的散热型电子封装结构，其特征在于，包含多个穿透硅通孔是形成在该多个芯片上且填充金属的通孔。
14.根据权利要求9所述的散热型电子封装结构，其特征在于，该多个芯片是依序一个堆栈在另一个上。
15.根据权利要求12所述的散热型电子封装结构，其特征在于，其更包含多个被动集成电路芯片，其中该多个被动集成电路芯片嵌置于该基板内。
16.一种散热型电子封装结构的制备方法，包含下列步骤：
提供一晶圆，该晶圆包含多个集成电路芯片在一表面上；
涂布一树脂材料于该晶圆包含多个集成电路芯片的该表面相反的的一表面，其中该树脂材料包含多个纳米碳球；
切割涂布该树脂材料的该晶圆，以获得多个电子封装结构；
将该电子封装结构覆晶接合于一基板上；以及
形成一底胶层于该电子封装结构与该基板之间，其中该底胶层混合多个纳米碳球，所述纳米碳球的表面是可处理的，以具有电绝缘层，所述电绝缘层防止有寄生效应或电性短路现象发生。
17.根据权利要求16所述的制备方法，其特征在于，其更包含将多个焊球接合在该晶圆上与涂布该树脂材料的该表面相对的一表面的步骤。
18.一种晶圆级散热型芯片尺寸封装结构，包含：
一基板；
一晶圆包含多个集成电路芯片与多个焊球位於一表面上；
一混有多个纳米碳球的树脂材料，覆盖该芯片的一表面，其中该表面与该多个焊球相对；以及
一底胶层于该具有多个焊球的表面与该基板之间；其中该底胶层混合多个纳米碳球，所述纳米碳球的表面是可处理的，以具有电绝缘层，所述电绝缘层防止有寄生效应或电性短路现象发生。
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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006098367A1 (ja) 2005-03-17 2006-09-21 Yamaha Corporation 磁気センサ及びその製造方法
US8237293B2 (en) * 2009-11-25 2012-08-07 Freescale Semiconductor, Inc. Semiconductor package with protective tape
US20110309481A1 (en) * 2010-06-18 2011-12-22 Rui Huang Integrated circuit packaging system with flip chip mounting and method of manufacture thereof
KR20120000282A (ko) * 2010-06-25 2012-01-02 삼성전자주식회사 히트 스프레더 및 그를 포함하는 반도체 패키지
JP2012104790A (ja) * 2010-10-12 2012-05-31 Elpida Memory Inc 半導体装置
KR20120122266A (ko) * 2011-04-28 2012-11-07 매그나칩 반도체 유한회사 칩온필름형 반도체 패키지
US8643155B2 (en) * 2011-06-09 2014-02-04 Shenzhen China Star Optoelectronics Technology Co., Ltd. Liquid crystal display and chip on film thereof
TW201320263A (zh) * 2011-11-11 2013-05-16 Chipmos Technologies Inc 加強散熱的封裝結構
JP5924725B2 (ja) * 2011-11-14 2016-05-25 ヤマハ株式会社 歪みセンサ及び歪みセンサの製造方法
TWI504852B (zh) * 2012-09-07 2015-10-21 Compal Electronics Inc 散熱模組
CN103066036A (zh) * 2012-12-30 2013-04-24 杨渊翔 一种主动式散热基板
US20140233166A1 (en) * 2013-02-19 2014-08-21 Norman E. O'Shea Flexible powered cards and devices, and methods of manufacturing flexible powered cards and devices
US9385091B2 (en) 2013-03-08 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Reinforcement structure and method for controlling warpage of chip mounted on substrate
EP2801549B1 (en) 2013-05-10 2018-01-31 Yamaha Corporation Strain sensor based on carbon nanotubes and method for its manufacture
US20150001736A1 (en) * 2013-06-29 2015-01-01 Hualiang Shi Die connections using different underfill types for different regions
US9190399B2 (en) 2014-03-06 2015-11-17 International Business Machines Corporation Thermally enhanced three-dimensional integrated circuit package
TWI575673B (zh) * 2014-11-07 2017-03-21 瑞鼎科技股份有限公司 雙面覆晶薄膜封裝結構及其製造方法
TWI611740B (zh) * 2015-02-05 2018-01-11 頎邦科技股份有限公司 可撓性基板
US10128207B2 (en) * 2015-03-31 2018-11-13 Stmicroelectronics Pte Ltd Semiconductor packages with pillar and bump structures
US9978663B2 (en) 2015-12-09 2018-05-22 Samsung Display Co., Ltd. Integrated circuit assembly with heat spreader and method of making the same
US9741677B1 (en) 2016-03-01 2017-08-22 Infineon Technologies Ag Semiconductor device including antistatic die attach material
DE102016103862A1 (de) * 2016-03-03 2017-09-07 Osram Opto Semiconductors Gmbh Optoelektronische Leuchtvorrichtung, Träger für einen optoelektronischen Halbleiterchip und optoelektronisches Leuchtsystem
CN105927869A (zh) * 2016-06-15 2016-09-07 重庆惠科金扬科技有限公司 灯条、背光模组及显示装置
US10535632B2 (en) * 2016-09-02 2020-01-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method of manufacturing the same
CN107644861A (zh) * 2017-10-27 2018-01-30 无锡吉迈微电子有限公司 芯片再布线封装结构及其实现工艺
US10897824B2 (en) * 2017-10-30 2021-01-19 Baker Hughes, A Ge Company, Llc Encapsulation of downhole microelectronics and method the same
KR102567412B1 (ko) * 2018-10-31 2023-08-16 삼성전자주식회사 복수의 레이어를 포함하는 차폐 필름 및 그것을 사용하는 전자 장치
KR102586072B1 (ko) * 2019-05-21 2023-10-05 삼성전기주식회사 반도체 패키지 및 이를 포함하는 안테나 모듈
TWI724592B (zh) * 2019-10-25 2021-04-11 大陸商北京集創北方科技股份有限公司 散熱元件及半導體封裝件
TWI760806B (zh) * 2020-07-31 2022-04-11 大陸商河南烯力新材料科技有限公司 薄膜覆晶封裝結構與顯示裝置
TWI761060B (zh) * 2021-02-03 2022-04-11 南茂科技股份有限公司 薄膜覆晶封裝結構
CN114721188A (zh) * 2022-03-29 2022-07-08 颀中科技（苏州）有限公司 覆晶封装结构的形成方法、覆晶封装结构及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2662449Y (zh) * 2003-02-19 2004-12-08 立卫科技股份有限公司 基板堆栈式封装结构
CN1574349A (zh) * 2003-05-22 2005-02-02 松下电器产业株式会社 大规模集成电路封装
US6951811B2 (en) * 2003-05-12 2005-10-04 Shinko Electric Industries Co., Ltd. Method of producing vias and other conductor parts on an electrode terminal forming surface of a semiconductor wafer
TW200735303A (en) * 2006-03-07 2007-09-16 Der-Ho Wu Epoxy molding compound reinforced with carbon nanotubes
CN101330076A (zh) * 2007-06-20 2008-12-24 海力士半导体有限公司 穿透硅通道芯片堆叠封装
CN201229937Y (zh) * 2008-07-15 2009-04-29 力成科技股份有限公司 具有非阵列凸块的倒装芯片封装结构
CN101447443A (zh) * 2006-08-15 2009-06-03 南茂科技股份有限公司 高频集成电路封装构造的制造方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6825550B2 (en) * 1999-09-02 2004-11-30 Micron Technology, Inc. Board-on-chip packages with conductive foil on the chip surface
DE10058593A1 (de) * 2000-11-25 2002-06-06 Bosch Gmbh Robert Verpacktes elektronisches Bauelement und Verfahren zur Verpackung eines elektronischen Bauelements
WO2003021018A1 (en) 2001-08-31 2003-03-13 Nano-C, Llc Method for combustion synthesis of fullerenes
US6965513B2 (en) 2001-12-20 2005-11-15 Intel Corporation Carbon nanotube thermal interface structures
TW575520B (en) 2002-02-27 2004-02-11 Ind Tech Res Inst Preparation of hollow carbon nanocapsules
US6813866B2 (en) * 2002-04-17 2004-11-09 Building Materials Investment Corporation Laminated hip and ridge asphalt shingle
TWI251580B (en) 2002-08-02 2006-03-21 Ind Tech Res Inst Preparation of magnetic metal filled carbon nanocapsules
TW577856B (en) 2002-12-25 2004-03-01 Ind Tech Res Inst Organically functionalized carbon nanocapsules
TWI312353B (en) * 2002-12-26 2009-07-21 Ind Tech Res Inst Polymer chain grafted carbon nanocapsule
US7723406B2 (en) 2002-12-26 2010-05-25 Industrial Technology Research Institute Polymer-chain-grafted carbon nanocapsule
TWI242465B (en) 2003-07-21 2005-11-01 Ind Tech Res Inst Carbon nanocapsule as catalyst support
US7109581B2 (en) * 2003-08-25 2006-09-19 Nanoconduction, Inc. System and method using self-assembled nano structures in the design and fabrication of an integrated circuit micro-cooler
US6982492B2 (en) * 2003-10-23 2006-01-03 Intel Corporation No-flow underfill composition and method
CN1318536C (zh) * 2003-12-13 2007-05-30 鸿富锦精密工业（深圳）有限公司<Del/> 散热装置及其相变导热片
CN100376655C (zh) 2004-06-30 2008-03-26 鸿富锦精密工业（深圳）有限公司 热介面材料
TWI310368B (en) 2004-07-12 2009-06-01 Ind Tech Res Inst Heteroatom containing carbon nanocapsule and method of preparing the same
TWI388042B (zh) * 2004-11-04 2013-03-01 Taiwan Semiconductor Mfg 基於奈米管基板之積體電路
TW200633171A (en) * 2004-11-04 2006-09-16 Koninkl Philips Electronics Nv Nanotube-based fluid interface material and approach
US7623349B2 (en) * 2005-03-07 2009-11-24 Ati Technologies Ulc Thermal management apparatus and method for a circuit substrate
US20060280912A1 (en) * 2005-06-13 2006-12-14 Rong-Chang Liang Non-random array anisotropic conductive film (ACF) and manufacturing processes
US20070035930A1 (en) * 2005-08-10 2007-02-15 Chien-Min Sung Methods and devices for cooling printed circuit boards
US7295441B1 (en) * 2006-05-12 2007-11-13 Giga-Gyte Technology Co. Ltd. Heat dissipating type printed circuit board and structure thereof for conducting heat with heap pipe
US8890312B2 (en) * 2006-05-26 2014-11-18 The Hong Kong University Of Science And Technology Heat dissipation structure with aligned carbon nanotube arrays and methods for manufacturing and use
US7687890B2 (en) * 2007-03-29 2010-03-30 Intel Corporation Controlling substrate surface properties via colloidal coatings
US20090001599A1 (en) * 2007-06-28 2009-01-01 Spansion Llc Die attachment, die stacking, and wire embedding using film
CN100573856C (zh) 2007-07-11 2009-12-23 南茂科技股份有限公司 增进散热效益的卷带式半导体封装构造
CN101114623B (zh) * 2007-08-30 2010-06-16 威盛电子股份有限公司 封装模块及电子装置
KR101361828B1 (ko) * 2007-09-03 2014-02-12 삼성전자주식회사 반도체 디바이스, 반도체 패키지, 스택 모듈, 카드, 시스템및 반도체 디바이스의 제조 방법
US20100052156A1 (en) * 2008-08-27 2010-03-04 Advanced Semiconductor Engineering, Inc. Chip scale package structure and fabrication method thereof
US9041228B2 (en) * 2008-12-23 2015-05-26 Micron Technology, Inc. Molding compound including a carbon nano-tube dispersion
TWI475103B (zh) * 2009-12-15 2015-03-01 Ind Tech Res Inst 散熱結構

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2662449Y (zh) * 2003-02-19 2004-12-08 立卫科技股份有限公司 基板堆栈式封装结构
US6951811B2 (en) * 2003-05-12 2005-10-04 Shinko Electric Industries Co., Ltd. Method of producing vias and other conductor parts on an electrode terminal forming surface of a semiconductor wafer
CN1574349A (zh) * 2003-05-22 2005-02-02 松下电器产业株式会社 大规模集成电路封装
TW200735303A (en) * 2006-03-07 2007-09-16 Der-Ho Wu Epoxy molding compound reinforced with carbon nanotubes
CN101447443A (zh) * 2006-08-15 2009-06-03 南茂科技股份有限公司 高频集成电路封装构造的制造方法
CN101330076A (zh) * 2007-06-20 2008-12-24 海力士半导体有限公司 穿透硅通道芯片堆叠封装
CN201229937Y (zh) * 2008-07-15 2009-04-29 力成科技股份有限公司 具有非阵列凸块的倒装芯片封装结构

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US20110304991A1 (en) 2011-12-15
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