TWI452639B - 製造整合被動元件的半導體裝置及方法 - Google Patents

製造整合被動元件的半導體裝置及方法 Download PDF

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TWI452639B
TWI452639B TW097139646A TW97139646A TWI452639B TW I452639 B TWI452639 B TW I452639B TW 097139646 A TW097139646 A TW 097139646A TW 97139646 A TW97139646 A TW 97139646A TW I452639 B TWI452639 B TW I452639B
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layer
forming
substrate
insulating layer
semiconductor device
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TW097139646A
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TW200926322A (en
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Yaojian Lin
Haijing Cao
Qing Zhang
Kang Chen
Jianmin Fang
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Stats Chippac Ltd
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Description

製造整合被動元件的半導體裝置及方法
本發明一般有關於半導體裝置，以及更特別有關於製造整合被動元件的半導體裝置及方法。
半導體裝置在娛樂、通信、網路、電腦以及家用市場領域中之許多產品中找到。半導體裝置亦在軍事、航空、汽車、工業控制器以及辦公室設備中找到。此半導體裝置執行每個上述應用所需之各種電性功能。
此半導體裝置之製造包含形成具有複數個晶粒之晶圓。各半導體晶粒包括數百或數千個電晶體與其他主動與被動元件以實施各種電性功能。對於一給定晶圓，自此晶圓之各個晶粒典型執行相同之電性功能。前端製造通常是指在此晶圓上形成半導體裝置。此完成之晶圓具有主動面，其包含電晶體與其他主動與被動構件。後端製造是指將已完成之晶圓切割或單一化成個別晶粒，以及然後將此晶粒封裝用於結構支持與環境隔離。
半導體製造之一目標為生產一種較低成本封裝，其適合用於較快、可靠、較小以及較高密度之積體電路(IC)。覆晶封裝或晶圓級晶粒尺寸封裝(WLCSP)理想適合於要求高速率、高密度以及較多接腳數之IC。覆晶式封裝包含架置一朝下面對著一晶片載體基板或印刷電路板(PCB)之該晶粒的主動面。該晶粒上主動元件間之電性與機械互連與在 載體基板上之導電軌是由包含大量導電焊接凸塊或球之焊接凸塊結構而達成。該焊接凸塊是藉由施加於沉積在此設置於半導體基板上接觸墊上之焊接材料之回焊製程而形成。然後，將該焊接凸塊焊接至該載體基板。此覆晶半導體封裝提供從晶粒上主動元件至載體基板之短的電性傳導路徑，以便減少信號傳播、降低電容以及達成整體較佳之電路性能。
在許多應用中，渴求在該半導體晶粒上形成被動電路構件，例如：電感器、電容器以及電阻器。作為使用於最終產品之高Q射頻(RF)應用之大部份矽基板為主之晶圓為在製造製程中高成本項目。此作為高Q RF應用之矽基板亦已知具有高電阻。因此，渴求排除包含被動電路組件之半導體裝置中高電阻矽基板以節省製造成本，同時維持矽基板製程。
在某一實施例中，本發明為一種製造半導體裝置之方法，其包括以下步驟：在此半導體裝置之背側上提供第一基板；在此第一基板上形成第一絕緣層；在此第一絕緣層上形成第一導電層；在此第一導電層上形成第二絕緣層；在此第二絕緣層上形成第二導電層；在此第一絕緣層上形成第三導電層；在此第一、第二以及第三導電層上形成第一鈍化層；在此第一鈍化層上形成與第三導電層電性接觸之第四導電層；在此第一鈍化層上形成第二鈍化層；將一 載體裝附於此第二鈍化層；移除此第一基板；在此半導體裝置背側之第一絕緣層上形成一非矽基板；以及去除此載體。
在另一實施例中，本發明為一種製造半導體裝置之方法，其包括以下步驟：在此半導體裝置之背側上提供第一基板；在此第一基板上形成第一絕緣層；在此第一絕緣層上形成第一導電層；在此第一導電層上形成第一鈍化層；在此第一鈍化層上形成與第一導電層電性接觸之第二導電層；在此第一鈍化層上形成第二鈍化層；將一載體裝附於此第二鈍化層；移除此第一基板；在此半導體裝置背側上之第一絕緣層上形成一非矽基板；以及移除此載體。
在另一實施例中，本發明為一種製造半導體裝置之方法，其包括以下步驟：在此半導體裝置之背側上提供第一基板；在此第一基板上形成一絕緣層；在此絕緣層上形成一被動電路組件；在此被動電路組件上形成一鈍化層；將一載體裝附於此鈍化層；移除此第一基板；在此半導體裝置背側之絕緣層上形成一非矽基板；以及移除此載體。
在另一實施例中，本發明為一種半導體裝置，其包括：一非矽基板與形成於此非矽基板上之一絕緣層。一被動電路組件形成於此絕緣層上。一鈍化層形成於此被動電路組件上。一凸塊下金屬化形成於鈍化層上並與被動電路組件電性接觸。一焊接凸塊形成於此凸塊下金屬化上。
本發明參考圖式之下述說明中之一或多個實施例中敘述，其中，相似符號代表相同或類似組件。雖然，本發明是以達成本發明目的之最佳模式而敘述，熟習此技術人士瞭解，其可意圖包括在本發明精神與範疇中所涵蓋之替代、修正以及等效物，其如同由附加申請專利範圍所界定與以下所揭示內容與圖式所支持之等效物。
此半導體裝置之製造包含形成具有複數個晶粒之晶圓。各晶粒包括數百或數千個電晶體與其他主動與被動元件以實施一或多個電性功能。對一給定晶圓，來自此晶圓之各晶粒典型實施相同之電性功能。前端製造通常是指在此晶圓上形成半導體裝置。此已完成之晶圓具有包含電晶體與其他主動與被動元件之主動面。後端製造是指將已完成晶圓切割或單一化成個別晶粒，以及然後將此晶粒封裝作為結構支持及/或環境隔離。
一半導體晶圓通常包括：一主動表面，其具有半導體裝置設置其上；以及一背側表面，其形成具有例如矽之塊材半導體材料。此主動側表面包含複數個半導體晶粒。此主動表面藉由各種半導體製程而形成，其包括：疊層、圖案化、掺雜以及熱處理。在此疊層製程中，藉由包括熱氧化、氮化、化學氣相沉積(CVD)、物理氣相沉積(PVD)、蒸發以及濺鍍之技術，將半導體材料成長或沉積於該基板上。微影術包含將表面區域遮蔽，且蝕刻掉不想要之材料以形成特定結構。此掺雜製程藉由熱擴散或離子佈植注入掺雜材料之濃度。
覆晶半導體封裝與晶圓級封裝(WLP)是與積體電路(IC)共同使用，其要求高速率、高密度以及較多接腳數。覆晶式半導體裝置10包括架置一朝下面對著一晶片載體基板或印刷電路板(PCB)16之該晶粒14的主動區域12，如圖1所示。根據晶粒之電性設計，主動區域12包含主動與被動元件、導電層以及介電層。此電性與機械互連經由包括大量之個別導電焊接凸塊或球22之焊接凸塊結構20而達成。此焊接凸塊形成於設置在主動區域12上之凸塊墊或互連位置24上。此凸塊墊24藉由在主動區域12中導電軌而連接至主動電路。此焊接凸塊22藉由回焊製程而電性與機械連接至在載體基板16上之接觸墊或互連位置26。此覆晶半導體裝置提供從在晶粒14上主動元件至載體基板16上導電軌之短的電性傳導路徑，以便減少信號傳播、降低電容以及達成整體較佳之電路性能。
圖2a－2e說明形成半導體裝置之製程，此半導體裝置包括在半導體晶圓28上之整合被動電路元件(IPD)。在圖2a中，提供以矽(Si)假性晶圓材料製成之低成本假性基板30。一絕緣層32沉積在基板30上。此絕緣層32是以矽氮化物(Six Ny )、二氧化矽(SiO2 )、氮氧化矽(SiON)、五氧化鉭(Ta2 O5 )、鋯石(ZrO2 )、氧化鋁(Al2 O3 )或具有介電絕緣性質之其他材料所製成。此絕緣層32之沉積可以包含以厚度範圍從大約500至50 μm之PVD、CVD、印刷以及燒結。在一替代實施例中，絕緣層32有從1000至5000之厚度範圍。
一電性傳導層34使用圖案化與沉積製程而形成於絕緣層32上。導電層34可以藉鋁(Al)、鋁合金、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他電性傳導材料所製成，該電性傳導材料具有位在其下之選擇性黏著層與阻障層或將絕緣層32之主體夾在其中。黏著層與阻障層可以為鈦(Ti)、鈦鎢(TiW)、氮化鈦(TiN)、鉭(Ta)或氮化鉭(TaN)。此導電層34之沉積使用PVD、CVD、電解電鍍或無極電鍍製程。
將電阻層36圖案化且沉積在導電層34與絕緣層32上。電阻層36由矽化物鉭(TaSi2 )或其他金屬矽化物、TaN、鎳鉻(NiCr)、氮化鈦(TiN)或具有電阻大約5至100ohm/sq之經摻雜之多晶矽所製成。在一替代實施例中，電阻層36有7至10ohm/sq之電阻。此電阻層36之沉積可以包括以匹配所設計之表面電阻(Rs)厚度之PVD或CVD。
使用圖案化與沉積製程，將絕緣層38形成於電阻層36上與周圍。形成在導電層34上絕緣層38之部份，以提供一開口並曝露電阻層36作為互連，如同所示。此絕緣層38以Six Ny 、SiO2 、SiON、Ta2 O5 、ZnO、ZrO2 、Al2 O3 或具有介電絕緣性質之其他材料所製成。此絕緣層38之沉積可以包括具有大約100至4000厚度之PVD或CVD。
將電性傳導層40圖案化且沉積於絕緣層32與電阻層36上。電性傳導層42與部份導電層40是經由在絕緣層38中之開口而圖案化且沉積於絕緣層38與電阻層36上。取決於形成於基板30上個別裝置之連接性而此導電層40與42之個別部份可以為電性共同或電性隔離。導電層40與 42可以Al、Cu或具有選擇性導電之黏著層與阻障層之其他電性傳導材料所製成。此導電層40與42之沉積使用PVD、CVD、電解電鍍或無極電鍍製程。
一鈍化層44形成於上述結構上作為結構支持及物理與電性隔離。選擇具有對矽蝕刻劑良好之選擇性之鈍化層44，所以其可以使用作為一蝕刻停止層。鈍化層44可以Six Ny 、Si3 N4 、SiN、SiO2 、SiON、聚醯亞胺(PI)、苯環丁烯(BCB)、聚苯噁唑(PBO)或其他絕緣材料之一或多層所製成。使用遮罩界定蝕刻製程移除部份鈍化層44以曝露導電層40與42。
此電性傳導層46與48如同所示藉由圖案化與沉積而形成。層46作為導電層48之黏著與阻障層。取決於形成於基板30上個別裝置之連接性，此導電層46與48之個別部份可以為電性共同或電性隔離。例如，導電層46之一部份接觸導電層40，而導電層46之另一部份接觸導電層42，此導電層42與導電層40電性隔離。導電層46可以包括Ti、TiW、鉻(Cr)、Ta、TaN或其他電性傳導材料。導電層48可以由Al、Cu或其他電性傳導材料製成。導電層46與48之沉積使用PVD、CVD、電解電鍍或無極電鍍製程。
鈍化層50形成於鈍化層44與導電層48上作為結構支持以及物理與電性隔離。鈍化層50可以由Six Ny 、SiO2 、SiON、PI、BCB、PBO或其他絕緣材料製成。使用遮罩界定蝕刻製程移除部分鈍化層50以曝露導電層48，其在稍後使用於焊接凸塊之形成中。
將電性傳導黏著層52沉積在導電層48上。黏著層52可以由Ti、TiW、Cr、Ni或Ta製成。其次，將電性傳導層54沉積在黏著層52上。導電層54可以由Al、Cu、Sn、Ni、Au、Ag或其他電性傳導材料製成。交替地，導電層54可以包含多層，此多層包含阻障層與濕層。此阻障層可以為Ni、鎳釩(NiV)、鉻銅(CrCu)、TiW以及TaN。此濕層可以為Cu、Au或Ag。
導電層52與54構成凸塊下金屬化(UBM)結構作為焊接凸塊。此導電層52與54之沉積使用PVD、CVD、電解電鍍或無極電鍍製程，接著蝕刻。取決於特定UBM結構而可以改變UBM蝕刻劑。例如，此用於Cu之蝕刻劑為A70，具有11.15%硝酸與6.3%之醋酸。此蝕刻劑可以為A75，具有75.74%磷酸與7.35%之醋酸。此用於Ti之蝕刻劑可以為1%緩衝氫氟酸(HF)。
可以使用最右之導電層40作為線接合墊。導電層52與54可以覆蓋線接合墊作為良好電性連接。
在圖2b中，將黏著層56沉積在圖2a所形成之結構上。將暫時晶圓載體58接合至晶圓28前側上之黏著層56，用於處理且支持此沒有基板30之個別半導體晶片。此載體58可以為玻璃、金屬或其他堅固材料。黏著層56可以被活化且以紫外(UV)光或熱固化。
在圖2c中，藉由背面研磨、矽濕蝕刻、電漿蝕刻或化學機械拋光(CMP)以移除假性基板30。在某一實施例中，此矽濕蝕刻劑可以為0.5－10% HF與0.5－10%之過氧化氫 (H2 O2 )。在移除假性基板30後，可於標準切割或晶圓製程之鋸道上實施額外步驟切割或劃溝槽以減少在模封或層壓後半導體晶圓28之潛在翹曲。
在圖2d中，在電漿清洗或適當濕式清洗之後，藉由將此基板接合至絕緣層32，在晶圓28之背側上形成具有大約1000ohm－cm高電阻之非矽基板62。基板62是由非矽材料製成，例如：玻璃、玻璃纖維強化環氧樹脂複合物、模封化合物以及具有高電阻與適當損失正切之其他聚合物基複合物。例如，有K值3.7之EMC G770具有一增至15GHz之損失正切0.009以及體電阻1e12 ohm－cm。交替地，MSL－BE－67G(H)具有在2GHz之損失正切0.01以及體電阻1e15 ohm－cm。在另一實施例中，將基板62塗覆、印刷、模封或層壓在絕緣層32上然後固化。可以將具有錐形之鋸道應用於模封製程中。
在圖2e中，在晶圓單一化之前或之後將黏著層56與載體58移除。由焊接膏印刷、焊接球裝附、電解電鍍或無極電鍍製程，將電性傳導焊接材料沉積於導電層52與54上。此焊接材料可以為任何金屬或電性傳導材料，例如：Sn、鉛(Pb)、Ni、Au、Ag、Cu、鉍(Bi)以及其合金或其他電性傳導材料之混合。在某一實施例中，此焊接材料為63重量百分比之Sn與37重量百分比之Pb。藉由將導電材料加熱至其熔點以上而回焊此焊接材料以形成球或凸塊66。在某一實施例中，此焊接凸塊66高度大約75 μm。在一些應用中，二次回焊此焊接凸塊66以改善於UBM結構之電性接觸。 在半導體裝置上形成複數個焊接凸塊66。
導電層34、絕緣層38以及導電層42a、46a以及48a之組合構成具有電容性質之整合被動元件(IPD)，即一金屬－絕緣體－金屬(MIM)電容器。電阻層36a與36b提供電阻器組件至被動電路。在圖3中顯示等效電路圖。MIM電容器38包括界定節點34與42a之導電層。將電阻器36a提供於節點34與42b之間。將電阻器36b提供於節點40a與40b之間。導電層48b是在半導體晶圓28上之一電感器。此導電層在基板62之表面上平面圖中典型地纏繞或捲繞以產生或顯示渴望之電感性質，如同圖2e之橫截面中三個區域48b所示。此被動電路組件經由導電層48而電性連接至一或多個焊接凸塊66。此上述IPD可以實施一或多個電性功能，例如：濾波器、平衡至不平衡轉換器或雙工器。
圖4說明一實施例，其具有形成於非矽基板62與IPD間之黏著層68。黏著層68可以環氧樹脂為主或混合樹脂黏著劑製成。
圖5說明在鈍化層44與絕緣層32中製造通孔或溝渠70以加強在基板62與IPD結構間之結構整體性。通孔70可以如基板62或黏著劑68相同材料填滿。
總而言之，此IPD使用低成本犧牲基板30形成。暫時載體與半導體晶片保持在一起，直至在晶圓背側上形成非矽基板62為止。此非矽基板為對於矽之低成本替代，例如：聚合物基複合物薄膜、玻璃或模封化合物。以上製程包括以非矽基板取代高成本矽晶圓之使用，此矽晶圓具有如同 通常使用在習知技術中之高電阻。
雖然，已經詳細說明本發明之一或多個實施例，熟習此技術人士將瞭解，在不違背以下申請專利範圍中所設定之本發明之範疇，可以對此實施例作修正與調整。
10‧‧‧覆晶式半導體裝置
12‧‧‧主動區域
14‧‧‧晶片
16‧‧‧印刷電路板(PCB)
20‧‧‧焊接凸塊結構
22‧‧‧球
24‧‧‧凸塊墊
26‧‧‧互連位置
28‧‧‧半導體晶圓
30‧‧‧假性基板
32‧‧‧絕緣層
34‧‧‧電性傳導層
36‧‧‧電阻層
36a‧‧‧電阻層
36b‧‧‧電阻層
38‧‧‧絕緣層
40‧‧‧導電層
40a‧‧‧節點
40b‧‧‧節點
42‧‧‧導電層
42a‧‧‧導電層
44‧‧‧鈍化層
46‧‧‧導電層
46a‧‧‧導電層
48‧‧‧導電層
48a‧‧‧導電層
48b‧‧‧導電層
50‧‧‧鈍化層
52‧‧‧電性傳導黏著層
54‧‧‧電性傳導層
56‧‧‧黏著層
58‧‧‧載體
62‧‧‧基板
66‧‧‧焊接凸塊
68‧‧‧黏著層
70‧‧‧溝渠
圖1為具有焊接凸塊之覆晶半導體裝置，此等焊接凸塊提供在此晶粒主動區域與晶片載體基板間電性互連；圖2a－2e說明在晶圓上形成整合被動元件(IPD)之過程；圖3為IPD之等效電路；圖4說明在非矽基板與IPD間之一黏著層；以及圖5說明在非矽基板與IPD周圍的鈍化層間所形成之通孔。
28‧‧‧半導體晶圓
30‧‧‧假性基板
32‧‧‧絕緣層
34‧‧‧電性傳導層
36‧‧‧電阻層
38‧‧‧絕緣層
40‧‧‧導電層
42‧‧‧導電層
44‧‧‧鈍化層
46‧‧‧導電層
48‧‧‧導電層
50‧‧‧鈍化層
52‧‧‧電性傳導黏著層
54‧‧‧電性傳導層
56‧‧‧黏著層
58‧‧‧載體

Claims (15)

  1. 一種製造半導體裝置之方法，包括：提供矽基板；在該矽基板上形成第一絕緣層；在該第一絕緣層上形成包含電感器或電容器的整合被動元件；在該整合被動元件上形成鈍化層；將一載體裝附於該鈍化層；移除該矽基板以暴露該第一絕緣層；在相對於該載體之該第一絕緣層上形成一非矽基板；以及移除該載體。
  2. 如申請專利範圍第1項之方法，其中該非矽基板包括選自群組之材料，該群組由玻璃、模封化合物、環氧樹脂、聚合物以及聚合物複合物所構成。
  3. 如申請專利範圍第1項之方法，其中該非矽基板包括具有約1000ohm-cm的電阻率的材料。
  4. 如申請專利範圍第1項之方法，更包括：在該鈍化層上形成一凸塊下金屬化；以及在該凸塊下金屬化上形成一焊接凸塊。
  5. 如申請專利範圍第1項之方法，更包括在該第一絕緣層上形成一電阻層。
  6. 一種製造半導體裝置之方法，包括：提供矽基板； 在該矽基板上形成第一絕緣層；在該矽基板上形成具有電容性質或電感性質的一整合被動元件；在該整合被動元件上形成一鈍化層；移除該矽基板以暴露該第一絕緣層；以及在該整合被動元件和該第一絕緣層上形成一非矽基板。
  7. 如申請專利範圍第6項之方法，其中該非矽基板包括選自群組之材料，該群組由玻璃、模封化合物、環氧樹脂、聚合物以及聚合物複合物所構成。
  8. 如申請專利範圍第6項之方法，更包括在該非矽基板上形成一黏著層。
  9. 如申請專利範圍第6項之方法，其中形成該整合被動元件包括：在該第一絕緣層上形成第一導電層；在該第一導電層上形成第二絕緣層；以及在該第二絕緣層上形成第二導電層。
  10. 如申請專利範圍第6項之方法，更包括在該鈍化層上形成一凸塊下金屬化。
  11. 一半導體裝置，包括：一非矽基板；在該非矽基板上形成一絕緣層；在該非矽基板和該絕緣層上形成具有電容性質或電感性質的一整合被動元件； 在該整合被動元件和該非矽基板上形成一鈍化層；以及在該鈍化層上形成一導電層。
  12. 如申請專利範圍第11項之半導體裝置，其中該非矽基板包括具有約1000ohm-cm的電阻率的材料。
  13. 如申請專利範圍第11項之半導體裝置，更包括在該鈍化層中形成一通孔。
  14. 如申請專利範圍第11項之半導體裝置，其中該整合被動元件包括一電感器、一電容器或一電阻器。
  15. 如申請專利範圍第11項之半導體裝置，其中該非矽基板包括選自群組之材料，該群組由玻璃、模封化合物、環氧樹脂、聚合物以及聚合物複合物所構成。
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