TWI436431B - 源極/汲極應力件及其形成方法 - Google Patents

源極/汲極應力件及其形成方法 Download PDF

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Publication number
TWI436431B
TWI436431B TW097103705A TW97103705A TWI436431B TW I436431 B TWI436431 B TW I436431B TW 097103705 A TW097103705 A TW 097103705A TW 97103705 A TW97103705 A TW 97103705A TW I436431 B TWI436431 B TW I436431B
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TW
Taiwan
Prior art keywords
type
semiconductor device
semiconductor
semiconductor material
forming
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Application number
TW097103705A
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English (en)
Chinese (zh)
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TW200847299A (en
Inventor
Da Zhang
Brian A Winstead
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Freescale Semiconductor Inc
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Publication of TW200847299A publication Critical patent/TW200847299A/zh
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Publication of TWI436431B publication Critical patent/TWI436431B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/601Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/791Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/025Manufacture or treatment forming recessed gates, e.g. by using local oxidation
    • H10D64/027Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01Manufacture or treatment
    • H10D62/021Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/021Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
TW097103705A 2007-02-28 2008-01-31 源極/汲極應力件及其形成方法 TWI436431B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/680,181 US7572706B2 (en) 2007-02-28 2007-02-28 Source/drain stressor and method therefor

Publications (2)

Publication Number Publication Date
TW200847299A TW200847299A (en) 2008-12-01
TWI436431B true TWI436431B (zh) 2014-05-01

Family

ID=39714887

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097103705A TWI436431B (zh) 2007-02-28 2008-01-31 源極/汲極應力件及其形成方法

Country Status (7)

Country Link
US (1) US7572706B2 (enExample)
EP (1) EP2115778A4 (enExample)
JP (1) JP5559547B2 (enExample)
KR (1) KR101399208B1 (enExample)
CN (1) CN101622713B (enExample)
TW (1) TWI436431B (enExample)
WO (1) WO2008106304A1 (enExample)

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US8080452B2 (en) 2006-08-01 2011-12-20 Nxp, B.V. Effecting selectivity of silicon or silicon-germanium deposition on a silicon or silicon-germanium substrate by doping
KR100746232B1 (ko) * 2006-08-25 2007-08-03 삼성전자주식회사 스트레인드 채널을 갖는 모스 트랜지스터 및 그 제조방법
US20080248598A1 (en) * 2007-04-09 2008-10-09 Rohit Pal Method and apparatus for determining characteristics of a stressed material using scatterometry
US7745847B2 (en) * 2007-08-09 2010-06-29 United Microelectronics Corp. Metal oxide semiconductor transistor
US20100102393A1 (en) * 2008-10-29 2010-04-29 Chartered Semiconductor Manufacturing, Ltd. Metal gate transistors
US8124487B2 (en) * 2008-12-22 2012-02-28 Varian Semiconductor Equipment Associates, Inc. Method for enhancing tensile stress and source/drain activation using Si:C
US20110049582A1 (en) * 2009-09-03 2011-03-03 International Business Machines Corporation Asymmetric source and drain stressor regions
US8928094B2 (en) * 2010-09-03 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Strained asymmetric source/drain
CN102456739A (zh) * 2010-10-28 2012-05-16 中国科学院微电子研究所 半导体结构及其形成方法
CN102683385B (zh) * 2012-05-30 2014-12-24 清华大学 半导体结构及其形成方法
KR20140042460A (ko) * 2012-09-28 2014-04-07 삼성전자주식회사 반도체 소자
KR102137371B1 (ko) * 2013-10-29 2020-07-27 삼성전자 주식회사 반도체 장치 및 이의 제조 방법
CN106960838B (zh) * 2016-01-11 2019-07-02 中芯国际集成电路制造(上海)有限公司 静电保护器件及其形成方法
US10032868B2 (en) 2016-09-09 2018-07-24 Texas Instruments Incorporated High performance super-beta NPN (SBNPN)
CN114072544A (zh) * 2019-07-26 2022-02-18 应用材料公司 各向异性的外延生长

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JPS6313378A (ja) * 1986-07-04 1988-01-20 Nippon Telegr & Teleph Corp <Ntt> 半導体装置およびその製造方法
EP0412701B1 (en) * 1989-07-31 1996-09-25 Canon Kabushiki Kaisha Thin film transistor and preparation thereof
JPH0423329A (ja) * 1990-05-14 1992-01-27 Fujitsu Ltd 半導体装置の製造方法
US5427964A (en) * 1994-04-04 1995-06-27 Motorola, Inc. Insulated gate field effect transistor and method for fabricating
JPH0992825A (ja) * 1995-09-26 1997-04-04 Fuji Film Micro Device Kk 半導体装置およびその製造方法
US6621131B2 (en) 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6833307B1 (en) * 2002-10-30 2004-12-21 Advanced Micro Devices, Inc. Method for manufacturing a semiconductor component having an early halo implant
JP2004241755A (ja) * 2003-01-15 2004-08-26 Renesas Technology Corp 半導体装置
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
KR100488196B1 (ko) * 2003-09-29 2005-05-09 삼성전자주식회사 돌출된 드레인을 가지는 트랜지스터 및 이의 제조 방법
US7244654B2 (en) * 2003-12-31 2007-07-17 Texas Instruments Incorporated Drive current improvement from recessed SiGe incorporation close to gate
JP4837902B2 (ja) * 2004-06-24 2011-12-14 富士通セミコンダクター株式会社 半導体装置
US7642607B2 (en) * 2005-08-10 2010-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with reduced recess on substrate surface
US7449753B2 (en) * 2006-04-10 2008-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Write margin improvement for SRAM cells with SiGe stressors
US20070298557A1 (en) * 2006-06-22 2007-12-27 Chun-Feng Nieh Junction leakage reduction in SiGe process by tilt implantation
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Also Published As

Publication number Publication date
KR101399208B1 (ko) 2014-05-27
KR20090125757A (ko) 2009-12-07
US7572706B2 (en) 2009-08-11
CN101622713B (zh) 2013-10-23
EP2115778A4 (en) 2011-11-02
EP2115778A1 (en) 2009-11-11
US20080203449A1 (en) 2008-08-28
CN101622713A (zh) 2010-01-06
WO2008106304A1 (en) 2008-09-04
TW200847299A (en) 2008-12-01
JP2010520620A (ja) 2010-06-10
JP5559547B2 (ja) 2014-07-23

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