CN100578812C - 半导体器件以及半导体器件的制造方法 - Google Patents

半导体器件以及半导体器件的制造方法 Download PDF

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CN100578812C
CN100578812C CN200610132154A CN200610132154A CN100578812C CN 100578812 C CN100578812 C CN 100578812C CN 200610132154 A CN200610132154 A CN 200610132154A CN 200610132154 A CN200610132154 A CN 200610132154A CN 100578812 C CN100578812 C CN 100578812C
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丁明镇
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Abstract

一种半导体器件，包括形成在半导体衬底上方的第一和第二硅层。在第一与第二硅层之间形成有绝缘层。在第二硅层上方形成有栅绝缘层、栅电极和间隔层。在栅电极两侧的第二硅层上方形成有源极/漏极杂质区。

Description

半导体器件以及半导体器件的制造方法
本申请要求韩国专利申请No.10-2005-0095897(申请日为2005年10月12日)的优先权，该申请的全部内容通过参考援引于此。
技术领域
本发明涉及半导体器件以及半导体器件的制造方法，尤其涉及在沟道区的下部形成绝缘层的半导体器件以及半导体器件的制造方法。
背景技术
半导体工业一直稳定发展。半导体工业在数量上和质量上不断提高以满足市场和技术的需求。半导体工业的发展方向集中于半导体晶体管的最小化和集成化。通过将包含在半导体器件中的元件的尺寸降至最小可以实现半导体晶体管的最小化和集成化。
制造的半导体器件的尺寸越小，在单个芯片上可集成的器件越多。因此，电子能够更快地通过器件，从而提高了半导体器件的处理速度。另外，当半导体器件的尺寸降低时，通过半导体的电子数减少，从而降低了功耗。
半导体器件的高集成化、高速度和低功耗通常表明随着时间的推移半导体器件的历史性能提高。在1971年晶体管的最小线宽为10μm。然而，在1997年晶体管的最小线宽提高至0.25μm，并且在2003年提高至90nm。
在过去的30年中，半导体器件在尺寸、集成度和芯片速度方面得到提高。例如，半导体器件尺寸的减小系数一般为大约50，集成度的增加系数一般为大约10000倍，而芯片速度的提高系数为大约1000。已经研究出具有大约90nm线宽的晶体管。此外，具有大约65nm线宽的晶体管正处于开发中。
在0.13微米的半导体制造工艺中，在尺寸大约为200mm的晶片中形成宽度大约为70nm的栅极。在90nm的半导体制造工艺中，在尺寸大约为300mm的晶片中能形成宽度大约为50nm的栅极。将来，有可能通过65nm的半导体制造工艺在至少300mm的晶片中形成宽度大约为35nm的栅极。
与0.13微米的半导体制造工艺相比，90nm的半导体制造工艺表现出许多优点。例如，通过90nm的半导体制造工艺可以制造1.2nm的栅极氧化物层、50nm的栅极层和50nm的应变硅层，从而可以制造高速度和低功耗的晶体管。另外，由于90nm的半导体制造工艺可以使用300nm的晶片，因此能够降低制造成本。半导体工艺的这些发展在将来能够继续。
晶体管的一种结构是MOSFET晶体管(金属氧化物硅场效应晶体管)。晶体管的基本工作原理是基于漂移-扩散方程。即使随着时间的推移半导体器件尺寸的减小系数为至少50时，这种基本工作原理也不会改变。因此在半导体器件最小化的开发过程中，MOSFET技术的基本原理保持不变。然而，在线宽为0.1μm或更小的半导体器件(例如纳米级的半导体器件)的制造过程中，MOSFET器件面临着挑战。
已经开发出生长应变硅的技术。在生长应变硅时，将锗样品放置在硅衬底上并进行加热以从硅衬底生长锗(Ge)。从而，将硅(Si)与锗(Ge)接合并进行加热以生长应变硅。该应变硅可具有大体上与锗(Ge)相同的晶粒尺寸。
使用应变硅的半导体器件的尺寸比较小。然而，电子和空穴的迁移率可能降低。因此，需要具有足够电子和空穴迁移率的应变硅MOSFET器件。
在应变硅MOSFET器件的制造过程中，可以从硅(Si)上生长锗(Ge)，从而使硅原子之间的距离增大以对应于锗原子之间的距离。然后生长硅(Si)以形成应变硅。该应变硅可用于形成应变硅MOSFET以使其晶格(grid)结构的间距大于硅(Si)。
图1为示出在使用应变硅的半导体器件中电子迁移率提高的典型曲线图。Y轴表示电子的有效迁移率，X轴表示垂直有效场。与没有应变硅的半导体器件(例如，标号10)相比，应变硅半导体器件(例如，标号15)具有更高的有效迁移率，该应变硅半导体器件包含使用具有大约15％的锗原子密度的硅锗而发生应变的硅。同样，包含使用具有大约16％的锗原子密度的硅锗而发生应变的硅的半导体器件(参见标号16)具有更大的有效迁移率。
通常，用于半导体器件的垂直有效场的范围为500至600K(V/cm)。例如，没有应变硅的硅半导体器件(例如用标号10表示)可表现大约270Cm2/V0s的电子迁移率。包含使用具有大约15％的锗原子密度的硅锗而发生应变的硅的半导体器件(例如参见标号15)可表现大约450Cm2/V0s的电子迁移率。同样，包含使用具有大约16％的锗原子密度的硅锗而发生应变的硅的半导体器件(例如，参见标号16)可表现大约480Cm2/V0s的电子迁移率。因此，当有源硅层使用具有大约16％的锗原子密度的硅锗外延层而发生应变时，电子迁移率可以提高大约70％或更多。
虽然使用应变硅的半导体器件可以通过增加电子和空穴的迁移率来提高性能，但是它不能降低DIBL(漏感应势垒下降效应)。纳米级半导体器件中的DIBL是由漏电流和/或结击穿电压引起的。
发明内容
本发明的实施例涉及半导体器件以及半导体器件的制造方法。在本发明的实施例中，在沟道区的下部形成绝缘层。在本发明的实施例中，绝缘层可以减小沟道尺寸并可以充分防止漏电流，因此能够减小半导体器件的尺寸。同样，在本发明的实施例中，绝缘层可以降低结击穿电压并可以使MOSFET以较高的工作电压工作。
在本发明的实施例中，半导体器件包括：第一硅层和第二硅层，形成在半导体衬底上；第一绝缘层，形成在该第一硅层与该第二硅层之间；栅绝缘层、栅电极和间隔层，顺序形成在该第二硅层上；以及源极/漏极杂质区，形成在该栅电极两侧的第二硅层上，其中，所述第一绝缘层的下表面和侧表面与所述第一硅层相接触，所述第一绝缘层的上表面与所述第二硅层相接触。
本发明的实施例还涉及一种半导体器件的制造方法，该方法包括以下步骤：在半导体衬底上形成第一硅层；在该第一硅层中形成沟槽；用绝缘层填充该沟槽；在该第一硅层和该绝缘层上形成第二硅层；以及在该第二硅层上形成MOSFET晶体管。
附图说明
图1为示出使用应变硅的半导体器件中电子迁移率提高的典型曲线图。
图2为根据本发明实施例的半导体器件的典型横截面图。
图3A至图3F为示出根据本发明实施例的典型半导体器件制造工艺和典型半导体器件结构的典型横截面图。
具体实施方式
图2为示出根据本发明实施例的半导体器件的典型横截面图。半导体器件包括硅衬底101，在硅衬底101上定义绝缘区和有源区。隔离层108形成在硅衬底101的隔离层中。第一硅层102和第二硅层107顺序形成在硅衬底101上方。第二绝缘层106形成在第一硅层102与第二硅层107之间的有源区中心。
栅电极110形成在第二硅层107上方。栅绝缘层109形成在栅电极110与第二硅层107之间。间隔层112形成在栅电极110的侧面上。LDD(轻掺杂漏极)区111和源极/漏极杂质区113形成在栅电极110两侧的第二硅层107上方。根据本发明的实施例，在处理过程中第二绝缘层106形成在具有预定深度的沟槽中。第二绝缘层106形成在第一硅层102中。第二绝缘层106包括氧化物层和/或氮化物层。
图3A至图3F为示出根据本发明实施例的半导体器件制造工艺的典型横截面图。如图3A所示，通过外延工艺从硅衬底101生长锗样品(specimen)以形成第一硅层102。第一绝缘层103(例如包括氧化物层和/或氮化物层)形成在第一硅层102上方。光致抗蚀剂层104形成在第一绝缘层103上方。通过处理(例如曝光和显影工艺)选择性地图案化光致抗蚀剂层104。
在本发明的实施例中，可省略第一绝缘层103。光致抗蚀剂层104可直接形成在第一硅层102的上方，然后被图案化。
如图3B所示，使用光致抗蚀剂层104选择性地蚀刻第一绝缘层103和第一硅层102以形成沟槽105。光致抗蚀剂层104具有作为掩模的掩模图案。沟槽105具有进入到第一硅层102中的预定深度。
如图3C所示，在去除光致抗蚀剂层104和第一绝缘层103之后，第二绝缘层106形成在包括沟槽105的硅衬底101的整个表面上方。
如图3D所示，在第二绝缘层106的整个表面和第一硅层102上进行化学机械抛光处理，直到在沟槽105中形成的第二绝缘层106的表面为外部表面为止。在本发明的实施例中，第一硅层102和第二绝缘层106的表面是共面的。
如图3E所示，在硅衬底101上进行外延处理以在第一硅层102和第二绝缘层106的上方形成第二硅层107。
如图3F所示，在包括第二硅层107的硅衬底101上可选择性地进行至少一次光刻处理。进行至少一次光刻处理以选择性地去除第二硅层107、第一硅层102和硅衬底101以形成沟槽。可用绝缘材料填充该沟槽以形成隔离层108。隔离层108具有浅沟槽隔离(STI)结构。
形成栅绝缘层109和多晶硅层以形成栅电极。栅绝缘层109和多晶硅层顺序形成在硅衬底101的整个表面上。可选择性地去除(例如通过光刻处理)多晶硅层和栅绝缘层109以在第二硅层107的预定部分形成栅电极110。
低密度的n型或p型掺杂剂被注入到硅衬底101中(例如使用栅电极110作为掩模)。在栅电极110两侧的第二硅层107上形成LDD区111。
在硅衬底101(例如包括栅电极110)的整个表面上沉积绝缘层。在硅衬底101的整个表面上进行回蚀(etch back)处理以在栅电极110的侧部形成间隔层112。
高密度的n型或p型掺杂剂被注入到硅衬底101的整个表面中。栅电极110和间隔层112可用作掩模。在栅电极110两侧的第二硅层107上形成源极/漏极杂质区113。晕离子(Halo ions)能以预定的角度注入到硅衬底101中(例如使用栅电极110作为掩模)。
在本发明的实施例中，在纳米级(或者在实施例中较小的)半导体器件中电子和空穴的迁移率可得到提高。在本发明的实施例中，在沟道区(例如源极/漏极杂质区之间)的下部形成绝缘层，这样可以降低漏电流。在应变硅MOSFET中漏电流可能是导致DIBL(漏感应势垒下降效应)的问题。
在本发明的实施例中，在沟道区(例如源极/漏极杂质区之间)的下部形成绝缘层，这样可以降低结击穿电压。结击穿电压可能由较大的漏电流引起。
在本发明的实施例中，在ULSI(特大规模集成)和SOI(绝缘体上硅)MOSFET中在防止由较大漏电流引起的半导体器件的性能退化的同时，半导体器件能够提高数据的存储特性。
显然，对本领域的技术人员来说能够对本发明的实施例进行各种修改和变化。然而，本发明涵盖落入所附权利要求范围内的对本发明实施例的修改和变化。

Claims (9)

1.一种半导体器件的制造方法，包括以下步骤：
在半导体衬底上方形成第一硅层；
在该第一硅层中形成沟槽；
在该沟槽上方形成第一绝缘层；
在该第一硅层上方和该第一绝缘层上方形成第二硅层；以及
在该第二硅层上方形成MOSFET晶体管。
2.如权利要求1所述的方法，其中形成所述MOSFET晶体管的步骤包括：
在该第二硅层上方形成栅绝缘层和栅电极；
通过注入掺杂剂形成轻掺杂的漏极区；
在该栅电极的两侧形成间隔层；以及
通过注入掺杂剂形成源极/漏极区。
3.如权利要求1所述的方法，其中通过外延工艺在该半导体衬底上生长锗来形成该第一硅层。
4.如权利要求1所述的方法，其中所述形成第一绝缘层的步骤包括：
在具有该沟槽的第一硅层上方形成第一绝缘层；以及
在该第一硅层和该第一绝缘层上进行化学机械抛光处理。
5.如权利要求1所述的方法，其中该第一硅层包含应变硅，该应变硅具有不同于非应变硅的晶格间距。
6.如权利要求1所述的方法，其中该第一硅层包含使用锗而发生应变的硅。
7.如权利要求1所述的方法，其中该第一绝缘层包括氧化物层。
8.如权利要求1所述的方法，其中该第一绝缘层包括氮化物层。
9.如权利要求1所述的方法，其中该第一绝缘层形成在该栅电极下方。
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