CN101622713A - 源/漏应力器及其方法 - Google Patents

源/漏应力器及其方法 Download PDF

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CN101622713A
CN101622713A CN200880006470A CN200880006470A CN101622713A CN 101622713 A CN101622713 A CN 101622713A CN 200880006470 A CN200880006470 A CN 200880006470A CN 200880006470 A CN200880006470 A CN 200880006470A CN 101622713 A CN101622713 A CN 101622713A
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张达
布赖恩·A·温斯特德
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NXP USA Inc
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Abstract

提供了一种形成半导体器件(10)的方法。该方法包括形成覆盖在衬底(12)上的栅极结构(22)。该方法进一步包括形成邻近栅极结构(22)的侧壁间隔物(24)。该方法进一步包括在半导体器件(10)的源极侧的方向上执行成角注入(26)。该方法进一步包括对半导体器件(10)退火。该方法进一步包括在衬底中邻近侧壁间隔物(24)的相对端处形成凹部(32，34)，以暴露第一类型的半导体材料(16)。该方法进一步包括在凹部中外延生长第二类型的半导体材料(36，38)，其中第二类型的半导体材料具有与第一类型的半导体材料的晶格常数不同的晶格常数，以在半导体器件(10)的沟道区中造成应力。

Description

源/漏应力器及其方法
技术领域
本公开总体上涉及半导体器件，并且更具体地，涉及具有源/漏应力器(stressor)的半导体器件。
背景技术
已经开发源/漏应力器在沟道区中提供应变以提高晶体管的性能。已经发现对沟道施加拉伸应力提高N型沟道晶体管的电子迁移率，同时已经发现对沟道施加压缩应力提高空穴迁移率。施加的应力越大，通常提高的程度也越大。源/漏应力器的途径包括移除靠近沟道区的半导体材料以在那里形成凹部区域，并且然后通过生长不同类型的半导体材料来填充凹部区域。典型地，以硅作为起始半导体材料，通过生长碳化硅可以施加拉伸应力并且通过生长锗化硅可以施加压缩应力。对应力的一种限制是碳和锗的浓度。增加这些浓度就增加了应力，但是也增加了位错的概率。位错降低应力。所以碳和硅的浓度的大小尽可能不导致形成位错。然而，进一步提高应变将提高晶体管的性能而没有造成其他问题，诸如增加晶体管泄漏。
因此，需要进一步提高具有源/漏应力器的器件的性能。
附图说明
本发明通过示例来说明并且不受附图限制，在附图中相同的标记指示相同的元件。附图中的元件为了简单和清楚来说明并且不一定按照比例绘制。
图1是在一个实施例的工艺中的一阶段的半导体器件的横截面；
图2是图1的半导体器件在处理中的后续阶段的横截面；
图3是图2的半导体器件在处理中的后续阶段的横截面；
图4是图3的半导体器件在处理中的后续阶段的横截面；
图5是图4的半导体器件在处理中的后续阶段的横截面；
图6是图1的半导体器件在处理中的后续阶段的横截面；
图7是图6的半导体器件在处理中的后续阶段的横截面；以及
图8是与图1的半导体器件类似的半导体器件在根据另一实施例的工艺中的一阶段的横截面。
具体实施方式
从晶体管的源极侧执行成角注入以形成在至少接近栅极边缘的下面的源极注入区域。该栅极在注入时具有薄侧壁间隔物。栅极用作漏极侧的掩膜，使得通过注入在漏极侧形成的掺杂区域与栅极隔开。后续的退火保证了源极侧的掺杂区域至少与栅极的边缘对准并且可以少量延伸到栅极下面。蚀刻利用作为掩膜的栅极和侧壁间隔来移除半导体材料，以形成一个与具有薄侧壁间隔物的源极对准的凹部区域和与具有薄侧壁间隔物的漏极侧对准的另一凹部区域。在漏极侧区域形成凹部区域移除了通过对漏极侧注入而形成的掺杂区域。然而，源极注入区域具有延伸到侧壁间隔物下的部分使得没有通过形成源极侧凹部区域被移除。然后，在凹部区域生长不同类型的半导体材料。然后，该不同的半导体材料与源极掺杂区域的剩余部分接触，并且也在漏极侧形成漏极。不同的半导体材料优选在原位置掺杂以避免需要将倾向于放松应力的源/漏注入。因此，源极注入区域的剩余部分保证源极至少延伸到栅极的边缘。因为施加到漏极的电压将倾向于以任何方式耗尽直接邻近漏极的区域，所以这是漏极侧的最小后果。进一步地，在漏极侧上具有电压将增加整体的寄生电容。这通过以下说明和附图更容易理解。
图1所示是半导体器件10，半导体器件10包括支撑衬底12、在支撑衬底12上的绝缘层14、在绝缘层14上的半导体层16、确立半导体层16的边界的绝缘区18、在部分半导体层16上的栅极电介质20、在栅极电介质20上的栅极22和在栅极22侧壁上的侧壁间隔无24器件。支撑衬底12、绝缘层14和半导体层16的组合是在作为常见衬底的绝缘体上半导体(SOI)衬底。也可以采用不具有绝缘层的很多半导体类型的衬底。在这样的情况下，衬底的顶部可以被视为半导体层。而且，半导体层16可以是多层的。例如，半导体层16可以是在下部并相对较厚的硅层以及覆盖在上面的较薄的SiGe层。栅极22可以是多个层或单个层。为此目的多晶硅的单个层是有效的，但是还可以使用金属单层或多层或金属层和硅层的组合。栅极电介质20优选为生长氧化物，它典型地用于栅极电极，但是可以使用其他的材料。例如，可以使用高K电介质。侧壁间隔物24优选由氮化物构成，但是可以使用其他的材料。侧壁间隔物24优选相对较薄。在该描述的示例中，侧壁间隔物24的厚度优选大约为50埃，但是可以变化。可预见的范围是大约40至100埃，但也可已变化。
图2所示是在执行成角注入26之后的半导体器件。该角度优选从垂直方向到源极侧的方向为10度，使得栅极22用作漏极侧的掩膜。其他的角度也可能是有效的，例如5至30度。成角注入26导致形成掺杂区域28和掺杂区域30。掺杂区域28在源极侧上。掺杂区域30在漏极侧上。掺杂区域28具有延伸到侧壁间隔物24以下的部分。另一方面，掺杂区域30与栅极22和侧壁间隔物24隔开。注入26在形成源极和漏极中是有用的。因此，在半导体器件10是N沟道晶体管的情况下，注入26可以是注入砷或磷或者两者。对P沟道的情况，注入26可以是注入硼或二氟化硼(BF2)。将掺杂区28的厚度选择为希望用于沟道界面处源极的厚度的厚度。可以由角度和能量来确定掺杂区域28延伸到侧壁间隔物24和潜在栅极22下的程度。在该示例中，掺杂区域28大致延伸到栅极的边缘，它是在源极侧上的栅极22和侧壁间隔物24之间的的分界面。该能量也用于设置厚度。该角度对厚度也有影响。
图3所示是在退火之后的半导体器件10，退火对扩展掺杂区域28和30以及激活在掺杂区域28中的掺杂物有影响。该退火保证了掺杂区域28至少延伸至栅极22的边缘并将通常少量延伸到栅极22下面。
图4所示是在使用作为掩膜的侧壁间隔物24和栅极22蚀刻以导致在与侧壁间隔物24对准的源极侧上的凹部32和与侧壁间隔物24对准的漏极侧上的凹部34之后的半导体器件10。凹部32和34在凹部32和34和绝缘层14之间留下了一些半导体层16。凹部32和34可以被视为在侧壁间隔物24相对端上。
图5所示是在通过外延生长在凹部32中形成半导体区域36并在凹部34中形成半导体区域38之后的半导体器件10。半导体区域36和38是用于沟道区的应力器，沟道区直接在栅极电介质20下面并且在掺杂区域28的剩余部分和半导体区域38之间。在半导体器件10是N沟道器件的情况下，半导体区域36和38施加拉伸应力。可以通过生长碳化硅(SiC)实现拉伸应力以形成半导体区域36和38。在半导体器件10是P沟道器件的情况下，半导体区域36和38施加压缩应力。可以通过生长锗化硅(SiGe)实现压缩应力以形成半导体区域36和38。可以发现其他半导体材料也可用于该目的。应力是由于籽晶层的晶格常数与生长中的半导体区域的自然晶格常数不同而产生的。迫使生长半导体层进入籽晶层的晶格结构，并且由此造成施加应力。在执行外延生长之前，一般必须对半导体层16执行清洗。在执行了形成凹部32和34的蚀刻之后，一般不可避免地在半导体层16上形成天然氧化物层。为了执行外延生长，希望该层起到籽晶的作用而没有其他的材料。这是特别正确的，如在形成半导体区域36和38的情况下，这时生长材料需要没有位错。为了实现所希望的外延生长的表面，执行了表面清洗。这一般需要用于移除氧化物的化学剂，诸如HF。清洗也可以是多个步骤的组合。一个示例是在外延腔里在氢气预焙后使用HF在原位置湿式清洗。在栅极电介质20是氧化物的情况下，重要的是使清洗不接触栅极电介质20，因为这将蚀刻栅极电介质20。掺杂区域28的剩余部分保护栅极电介质20避开在源极侧清洗所使用的化学剂。在漏极侧，在侧壁间隔物24下面的半导体层16的部分保护栅极电介质20避开清洗所使用的化学剂。在源极侧和漏极侧两者上的侧壁间隔物24保护栅极电介质20避开清洗所使用的化学剂。在它们的生长过程中，半导体区域36和38可以原位置掺杂，因为它们可以被掺杂成希望的导电类型P或N。对于P型，原位置掺杂通常是硼，并且对于N型，通常是磷或砷或两者。对于一般的晶体管形成，形成与掺杂区域28导电类型相同的半导体区域36和38。在这样的情况下，半导体区域36和掺杂区域28的剩余部分形成适于用作源极的连续导电类型。在半导体区域36和38生长之后可以执行可以代替之前描述的退火步骤的退火步骤，但是风险在于将导致应力的放松或者过度掺杂物的扩散。因此，期望一般最好是在生长半导体区域36和38之前执行任何退火。
图6所示是在侧壁间隔物24上形成侧壁间隔物40之后的半导体器件10。侧壁间隔物40优选是氮化物，但也可以是其他的材料或者材料的组合。侧壁间隔物40优选比侧壁间隔物24更厚。这样的横向厚度的示例在最厚的点处大约是400埃。
图7所示是在半导体区域36和38的上表面上形成硅化物区域42和44之后的半导体器件10。侧壁间隔物以通常的方式保护沟道和栅极电介质避开硅化物。在硅化物形成之前，可以通过诸如注入来进行深源极/漏极形成。可以继续进一步的处理，诸如形成夹层电介质层和收缩层。
在另一实施例中，在栅极层叠形成之后，施加漏极侧保护层，用于仅仅在源极侧上形成掺杂区域。图8所示是具有暴露源极侧并覆盖漏极侧的图案化光阻层50的图1中的半导体器件10。在光阻层图案化之后，执行了注入和退火。由于图案化光阻层50的遮蔽，注入和退火导致如图3所示的掺杂区域28但在漏极侧上没有掺杂区域。如图4-7所示处理继续以实现具有源极/漏极应力器的半导体器件。虽然在用作漏极的半导体区域38和在漏极侧上的栅极22的边缘之间具有间隔，但是这不会引出太多的其他问题。在操作中，将电压施加到栅极和漏极上，这导致载流子克服在源极处的静电势垒。只要漏极不太远离在沟道中由栅极造成的反转，导电的开始受到漏极侧的影响是微不足道的。在侧壁间隔物24下的空间增加了一点阻抗，但是该不利条件通过将漏极和栅极进一步远距离隔开来降低寄生电容而抵消。
到目前为止，应当理解，半导体器件接近沟道具有应力器，这使栅极电介质避免在用于生长应力器的制备中暴露于清洗剂中。一个应力器实际上尽可能地接近沟道，因为在它处于漏极沟道交界面处，并且另一应力器仅仅距离沟道一小段距离，大约是侧壁间隔物24的厚度。该靠近沟道的接近与远离沟道的应力器相比增加了应力。
此外，如果有的话，在说明书和权利要求书中术语“前”、“后”、“顶”、“底”、“上”、“下”等等用于描述性目的并且不一定用于描述永久的相对位置。应当理解，如此使用的术语在合适的环境下可以互换，使得在此描述的本发明的实施例例如与在此所说明或以其他方式描述的那些相比也能够在其他方向上操作。
虽然在此参考具体实施例描述了本发明，但是在不背离如权利要求所阐述的本发明的范围的情况下，可以进行各种修改和改变。例如，可以使用其他材料。半导体层可以本身是多个层。一个这样的示例可以是SiGe层直接在硅层上的硅层。在这样的情况下，形成凹部的蚀刻将移除SiGe和硅。可以重新生长SiGe以替代硅和SiGe的组合。而且铟或BF2可以用于P型掺杂，并且锑可以用于N型掺杂。而且，给出的尺寸是示例性的，并且可以使用其他的尺寸。因此，说明书和附图应当认为是说明性而不是限制性的，并且所有这样的修改都意在被包括在本发明的范围内。针对具体实施例在此描述的任何益处、优点或对问题的解决方案并不意在被解释为任何或全部权利要求的关键、必需或必要特征或元素。
此外，如在此使用的术语“一”或“一个”被定义为一个或多于一个。而且，在权利要求中诸如“至少一个”和“一个或多个”的介绍性短语的使用不应当被解释成暗示：通过不定冠词“一”或“一个”引入其他的请求保护的元素将包含这样的引入的请求保护的元素的任何特定的权利要求限制到只包含一个这样的元素的发明中，即使当同一权利要求包括介绍性短语“一个或多个”或“至少一个”和诸如“一”或“一个”的不定冠词时。同样适用于对定冠词的使用。
除非另外说明，诸如“第一”和“第二”的术语用于在这样的术语所描述的元素之间任意地区分。因此，这些术语不一定意在指示这样的元素的时间上或其他的优先级。

Claims (20)

1.一种用于形成半导体器件的方法，包括：
形成覆盖在衬底上的栅极结构；
形成邻近于所述栅极结构的侧壁间隔物；
在所述半导体器件的源极侧的方向执行成角注入；
对所述半导体器件退火；
在衬底中邻近所述侧壁间隔物相对端处形成凹部，以暴露第一类型的半导体材料；以及
在所述凹部中外延生长第二类型的半导体材料，其中，第二类型的半导体材料具有与第一类型的半导体材料的晶格常数不同的自然晶格常数，以在所述半导体器件的沟道区中造成应力。
2.根据权利要求1所述的方法，进一步包括使用原位掺杂材料执行原位掺杂到第二类型的半导体材料中。
3.根据权利要求2所述的方法，其中，所述成角注入以相对于垂直轴成5度至30度的角度来执行。
4.根据权利要求2所述的方法，其中，所述半导体器件是P沟道器件且其中所述掺杂材料包括由硼、BF2和铟组成的组中的一个，并且其中第二类型的半导体材料是锗化硅。
5.根据权利要求2所述的方法，其中，所述半导体器件是N沟道器件且其中所述掺杂材料包括由磷、砷和锑组成的组中的一个，并且其中第二类型的半导体材料是碳化硅。
6.根据权利要求2所述的方法，其中，所述半导体器件是P沟道器件，并且其中所述原位掺杂材料是硼。
7.根据权利要求2所述的方法，其中，所述半导体器件是N沟道器件，并且其中所述原位掺杂材料包括由磷和砷组成的组中的一个。
8.根据权利要求1所述的方法，其中，在所述凹部中外延生长第二类型的半导体材料之后，执行所述退火步骤。
9.根据权利要求1所述的方法，其中，所述侧壁间隔物具有40埃至100埃范围内的宽度。
10.根据权利要求1所述的方法，进一步包括形成与半导体器件相对应的源极/漏极部分，并且在源极/漏极部分和栅极结构的上面形成硅化物层。
11.根据权利要求1所述的方法，其中，以以下方式执行到衬底中的所述成角注入：将掺杂材料注入到至少在仅在所述半导体器件的源极侧上的侧壁间隔物下面的区域中。
12.一种用于形成半导体器件的方法，包括：
形成覆盖在衬底上的栅极结构；
形成邻近所述栅极结构的侧壁间隔物；
图案化光阻层，使得覆盖所述半导体器件的漏极侧但暴露所述半导体器件的源极侧；
执行到衬底中的注入；
移除光阻层；
对所述半导体器件退火；
在衬底中邻近所述侧壁间隔物相对端处形成凹部，以暴露第一类型的半导体材料；以及
在所述凹部中外延生长第二类型的半导体材料，其中，第二类型的半导体材料具有与第一类型的半导体材料的晶格常数不同的晶格常数，以在所述半导体器件的沟道区中造成应力。
13.根据权利要求12所述的方法，进一步包括使用原位掺杂材料执行原位掺杂到第二类型的半导体材料中。
14.根据权利要求13所述的方法，其中，所述半导体器件是P沟道器件且其中所述掺杂材料包括由硼、BF2和铟组成的组中的一个，并且其中第二类型的半导体材料是锗化硅。
15.根据权利要求13所述的方法，其中，所述半导体器件是N沟道器件且其中所述掺杂材料包括由磷、砷和锑组成的组中的一个，并且其中第二类型的半导体材料是碳化硅。
16.根据权利要求12所述的方法，其中，在所述凹部中外延生长第二类型的半导体之后，执行所述退火步骤。
17.一种包括覆盖在衬底上的栅极结构的半导体器件，包括：
侧壁间隔物，所述侧壁间隔物邻近所述栅极结构而形成；
沟道区，所述沟道区在所述栅极结构下使用第一类型的半导体材料而形成；
外延生长应力器，所述外延生长应力器在所述半导体器件的源/漏区域中形成，其中使用第二类型的半导体材料形成应力器，并且其中第二类型的半导体材料具有与第一类型的半导体材料的晶格常数不同的晶格常数，以在所述沟道区中造成应力；以及
第一类型的半导体材料的第一掺杂区域和第一类型的半导体材料的第二掺杂区域，所述第一掺杂区域在侧壁间隔物的源极侧上的侧壁间隔物下形成，所述第二掺杂区域在侧壁间隔物的漏极侧上的侧壁间隔物下形成，其中第一掺杂区域的最高掺杂密度高于第二掺杂区域的最高掺杂密度。
18.根据权利要求17所述的半导体器件，其中，所述侧壁间隔物具有在40埃至100埃范围内的宽度。
19.根据权利要求17所述的半导体器件，其中，所述半导体器件是P沟道器件且其中第一掺杂区域用包括由硼、BF2和铟组成的组中的一个的掺杂材料来掺杂，并且其中第二类型的半导体材料是锗化硅。
20.根据权利要求17所述的半导体器件，其中，所述半导体器件是N沟道器件且其中第一掺杂区域用包括由磷、砷和锑组成的组中的一个的掺杂材料来掺杂，并且其中第二类型的半导体材料是碳化硅。
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